net/ice/base: enable HW to prefetch Rx descriptors
Currently we are always setting prefena to 0. This is causing the hardware to only fetch descriptors when there are none free in the cache for a received packet instead of prefetching when it has used the last descriptor regardless of incoming packets. Fix this by allowing the hardware to prefetch Rx descriptors. Signed-off-by: Brett Creeley <brett.creeley@intel.com> Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Signed-off-by: Leyi Rong <leyi.rong@intel.com> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
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@ -1213,6 +1213,7 @@ static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
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ICE_CTX_STORE(ice_rlan_ctx, tphdata_ena, 1, 195),
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ICE_CTX_STORE(ice_rlan_ctx, tphhead_ena, 1, 196),
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ICE_CTX_STORE(ice_rlan_ctx, lrxqthresh, 3, 198),
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ICE_CTX_STORE(ice_rlan_ctx, prefena, 1, 201),
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{ 0 }
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};
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@ -1223,7 +1224,8 @@ static const struct ice_ctx_ele ice_rlan_ctx_info[] = {
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* @rxq_index: the index of the Rx queue
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*
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* Converts rxq context from sparse to dense structure and then writes
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* it to HW register space
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* it to HW register space and enables the hardware to prefetch descriptors
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* instead of only fetching them on demand
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*/
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enum ice_status
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ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
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@ -1231,6 +1233,11 @@ ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
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{
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u8 ctx_buf[ICE_RXQ_CTX_SZ] = { 0 };
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if (!rlan_ctx)
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return ICE_ERR_BAD_PTR;
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rlan_ctx->prefena = 1;
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ice_set_ctx((u8 *)rlan_ctx, ctx_buf, ice_rlan_ctx_info);
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return ice_copy_rxq_ctx_to_hw(hw, ctx_buf, rxq_index);
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}
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@ -807,6 +807,7 @@ struct ice_rlan_ctx {
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u8 tphdata_ena;
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u8 tphhead_ena;
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u16 lrxqthresh; /* bigger than needed, see above for reason */
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u8 prefena; /* NOTE: normally must be set to 1 at init */
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};
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struct ice_ctx_ele {
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