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net/mlx5: fix layer bits to be unique

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The layer bits should be unique otherwise layer info will be
interpreted wrongly.

Fixes: 70d84dc797b7 ("net/mlx5: add internal tag item and action")
Fixes: 55deee1715f0 ("net/mlx5: extend flow mark support")

Signed-off-by: Xiaoyu Min <jackmin@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
This commit is contained in:
Xiaoyu Min 2019-11-13 11:29:59 +02:00 committed by Ferruh Yigit
parent 50d23b9ace
commit 20ac796641
1 changed files with 8 additions and 8 deletions
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16
drivers/net/mlx5/mlx5_flow.h
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@ -109,18 +109,18 @@ enum mlx5_feature_name {
#define MLX5_FLOW_ITEM_MARK (1u << 19)
/* Pattern MISC bits. */
#define MLX5_FLOW_LAYER_ICMP (1u << 19)
#define MLX5_FLOW_LAYER_ICMP6 (1u << 20)
#define MLX5_FLOW_LAYER_GRE_KEY (1u << 21)
#define MLX5_FLOW_LAYER_ICMP (1u << 20)
#define MLX5_FLOW_LAYER_ICMP6 (1u << 21)
#define MLX5_FLOW_LAYER_GRE_KEY (1u << 22)
/* Pattern tunnel Layer bits (continued). */
#define MLX5_FLOW_LAYER_IPIP (1u << 21)
#define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 22)
#define MLX5_FLOW_LAYER_NVGRE (1u << 23)
#define MLX5_FLOW_LAYER_GENEVE (1u << 24)
#define MLX5_FLOW_LAYER_IPIP (1u << 23)
#define MLX5_FLOW_LAYER_IPV6_ENCAP (1u << 24)
#define MLX5_FLOW_LAYER_NVGRE (1u << 25)
#define MLX5_FLOW_LAYER_GENEVE (1u << 26)
/* Queue items. */
#define MLX5_FLOW_ITEM_TX_QUEUE (1u << 25)
#define MLX5_FLOW_ITEM_TX_QUEUE (1u << 27)
/* Outer Masks. */
#define MLX5_FLOW_LAYER_OUTER_L3 \