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examples/ip_pipeline: fix IPv6 endianness

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Fix IPv6 endianness from big endian to CPU order.

Fixes: a3a95b7d58 ("examples/ip_pipeline: add table entry commands")
Cc: stable@dpdk.org

Signed-off-by: Reshma Pattan <reshma.pattan@intel.com>
Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
This commit is contained in:
Reshma Pattan 2018-09-28 17:18:55 +01:00 committed by Cristian Dumitrescu
parent e1c0b44553
commit 223be676c3
1 changed files with 24 additions and 16 deletions
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40
examples/ip_pipeline/thread.c
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@ -2244,29 +2244,37 @@ match_convert(struct table_rule_match *mh,
ml->acl_add.field_value[0].mask_range.u8 =
mh->match.acl.proto_mask;
ml->acl_add.field_value[1].value.u32 = sa32[0];
ml->acl_add.field_value[1].value.u32 =
rte_be_to_cpu_32(sa32[0]);
ml->acl_add.field_value[1].mask_range.u32 =
sa32_depth[0];
ml->acl_add.field_value[2].value.u32 = sa32[1];
ml->acl_add.field_value[2].value.u32 =
rte_be_to_cpu_32(sa32[1]);
ml->acl_add.field_value[2].mask_range.u32 =
sa32_depth[1];
ml->acl_add.field_value[3].value.u32 = sa32[2];
ml->acl_add.field_value[3].value.u32 =
rte_be_to_cpu_32(sa32[2]);
ml->acl_add.field_value[3].mask_range.u32 =
sa32_depth[2];
ml->acl_add.field_value[4].value.u32 = sa32[3];
ml->acl_add.field_value[4].value.u32 =
rte_be_to_cpu_32(sa32[3]);
ml->acl_add.field_value[4].mask_range.u32 =
sa32_depth[3];
ml->acl_add.field_value[5].value.u32 = da32[0];
ml->acl_add.field_value[5].value.u32 =
rte_be_to_cpu_32(da32[0]);
ml->acl_add.field_value[5].mask_range.u32 =
da32_depth[0];
ml->acl_add.field_value[6].value.u32 = da32[1];
ml->acl_add.field_value[6].value.u32 =
rte_be_to_cpu_32(da32[1]);
ml->acl_add.field_value[6].mask_range.u32 =
da32_depth[1];
ml->acl_add.field_value[7].value.u32 = da32[2];
ml->acl_add.field_value[7].value.u32 =
rte_be_to_cpu_32(da32[2]);
ml->acl_add.field_value[7].mask_range.u32 =
da32_depth[2];
ml->acl_add.field_value[8].value.u32 = da32[3];
ml->acl_add.field_value[8].value.u32 =
rte_be_to_cpu_32(da32[3]);
ml->acl_add.field_value[8].mask_range.u32 =
da32_depth[3];
@ -2308,36 +2316,36 @@ match_convert(struct table_rule_match *mh,
mh->match.acl.proto_mask;
ml->acl_delete.field_value[1].value.u32 =
sa32[0];
rte_be_to_cpu_32(sa32[0]);
ml->acl_delete.field_value[1].mask_range.u32 =
sa32_depth[0];
ml->acl_delete.field_value[2].value.u32 =
sa32[1];
rte_be_to_cpu_32(sa32[1]);
ml->acl_delete.field_value[2].mask_range.u32 =
sa32_depth[1];
ml->acl_delete.field_value[3].value.u32 =
sa32[2];
rte_be_to_cpu_32(sa32[2]);
ml->acl_delete.field_value[3].mask_range.u32 =
sa32_depth[2];
ml->acl_delete.field_value[4].value.u32 =
sa32[3];
rte_be_to_cpu_32(sa32[3]);
ml->acl_delete.field_value[4].mask_range.u32 =
sa32_depth[3];
ml->acl_delete.field_value[5].value.u32 =
da32[0];
rte_be_to_cpu_32(da32[0]);
ml->acl_delete.field_value[5].mask_range.u32 =
da32_depth[0];
ml->acl_delete.field_value[6].value.u32 =
da32[1];
rte_be_to_cpu_32(da32[1]);
ml->acl_delete.field_value[6].mask_range.u32 =
da32_depth[1];
ml->acl_delete.field_value[7].value.u32 =
da32[2];
rte_be_to_cpu_32(da32[2]);
ml->acl_delete.field_value[7].mask_range.u32 =
da32_depth[2];
ml->acl_delete.field_value[8].value.u32 =
da32[3];
rte_be_to_cpu_32(da32[3]);
ml->acl_delete.field_value[8].mask_range.u32 =
da32_depth[3];