net/mlx4: drop checksum offloads support
The Verbs API used to implement Tx and Rx checksum offloads is deprecated. Support for these will be added back after refactoring the PMD. Signed-off-by: Adrien Mazarguil <adrien.mazarguil@6wind.com>
This commit is contained in:
Adrien Mazarguil
Ferruh Yigit
parent
4bd2aa1198
commit
22aadcc696
@ -14,10 +14,6 @@ MTU update = Y
|
||||
Jumbo frame = Y
|
||||
Scattered Rx = Y
|
||||
SR-IOV = Y
|
||||
L3 checksum offload = Y
|
||||
L4 checksum offload = Y
|
||||
Inner L3 checksum = Y
|
||||
Inner L4 checksum = Y
|
||||
Packet type parsing = Y
|
||||
Basic stats = Y
|
||||
Stats per queue = Y
|
||||
|
||||
@ -80,8 +80,6 @@ Features
|
||||
- Multi arch support: x86_64 and POWER8.
|
||||
- Link state information is provided.
|
||||
- Scattered packets are supported for TX and RX.
|
||||
- Inner L3/L4 (IP, TCP and UDP) TX/RX checksum offloading and validation.
|
||||
- Outer L3 (IP) TX/RX checksum offloading and validation for VXLAN frames.
|
||||
- RX interrupts.
|
||||
|
||||
Configuration
|
||||
|
||||
@ -1258,17 +1258,6 @@ mlx4_tx_burst(void *dpdk_txq, struct rte_mbuf **pkts, uint16_t pkts_n)
|
||||
++elts_comp;
|
||||
send_flags |= IBV_EXP_QP_BURST_SIGNALED;
|
||||
}
|
||||
/* Should we enable HW CKSUM offload */
|
||||
if (buf->ol_flags &
|
||||
(PKT_TX_IP_CKSUM | PKT_TX_TCP_CKSUM | PKT_TX_UDP_CKSUM)) {
|
||||
send_flags |= IBV_EXP_QP_BURST_IP_CSUM;
|
||||
/* HW does not support checksum offloads at arbitrary
|
||||
* offsets but automatically recognizes the packet
|
||||
* type. For inner L3/L4 checksums, only VXLAN (UDP)
|
||||
* tunnels are currently supported. */
|
||||
if (RTE_ETH_IS_TUNNEL_PKT(buf->packet_type))
|
||||
send_flags |= IBV_EXP_QP_BURST_TUNNEL;
|
||||
}
|
||||
if (likely(segs == 1)) {
|
||||
uintptr_t addr;
|
||||
uint32_t length;
|
||||
@ -2140,41 +2129,6 @@ rxq_cq_to_pkt_type(uint32_t flags)
|
||||
return pkt_type;
|
||||
}
|
||||
|
||||
/**
|
||||
* Translate RX completion flags to offload flags.
|
||||
*
|
||||
* @param[in] rxq
|
||||
* Pointer to RX queue structure.
|
||||
* @param flags
|
||||
* RX completion flags returned by poll_length_flags().
|
||||
*
|
||||
* @return
|
||||
* Offload flags (ol_flags) for struct rte_mbuf.
|
||||
*/
|
||||
static inline uint32_t
|
||||
rxq_cq_to_ol_flags(const struct rxq *rxq, uint32_t flags)
|
||||
{
|
||||
uint32_t ol_flags = 0;
|
||||
|
||||
if (rxq->csum)
|
||||
ol_flags |=
|
||||
TRANSPOSE(flags,
|
||||
IBV_EXP_CQ_RX_IP_CSUM_OK,
|
||||
PKT_RX_IP_CKSUM_GOOD) |
|
||||
TRANSPOSE(flags,
|
||||
IBV_EXP_CQ_RX_TCP_UDP_CSUM_OK,
|
||||
PKT_RX_L4_CKSUM_GOOD);
|
||||
if ((flags & IBV_EXP_CQ_RX_TUNNEL_PACKET) && (rxq->csum_l2tun))
|
||||
ol_flags |=
|
||||
TRANSPOSE(flags,
|
||||
IBV_EXP_CQ_RX_OUTER_IP_CSUM_OK,
|
||||
PKT_RX_IP_CKSUM_GOOD) |
|
||||
TRANSPOSE(flags,
|
||||
IBV_EXP_CQ_RX_OUTER_TCP_UDP_CSUM_OK,
|
||||
PKT_RX_L4_CKSUM_GOOD);
|
||||
return ol_flags;
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n);
|
||||
|
||||
@ -2362,7 +2316,7 @@ mlx4_rx_burst_sp(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
|
||||
PORT(pkt_buf) = rxq->port_id;
|
||||
PKT_LEN(pkt_buf) = pkt_buf_len;
|
||||
pkt_buf->packet_type = rxq_cq_to_pkt_type(flags);
|
||||
pkt_buf->ol_flags = rxq_cq_to_ol_flags(rxq, flags);
|
||||
pkt_buf->ol_flags = 0;
|
||||
|
||||
/* Return packet. */
|
||||
*(pkts++) = pkt_buf;
|
||||
@ -2517,7 +2471,7 @@ mlx4_rx_burst(void *dpdk_rxq, struct rte_mbuf **pkts, uint16_t pkts_n)
|
||||
PKT_LEN(seg) = len;
|
||||
DATA_LEN(seg) = len;
|
||||
seg->packet_type = rxq_cq_to_pkt_type(flags);
|
||||
seg->ol_flags = rxq_cq_to_ol_flags(rxq, flags);
|
||||
seg->ol_flags = 0;
|
||||
|
||||
/* Return packet. */
|
||||
*(pkts++) = seg;
|
||||
@ -2626,15 +2580,6 @@ rxq_rehash(struct rte_eth_dev *dev, struct rxq *rxq)
|
||||
/* Number of descriptors and mbufs currently allocated. */
|
||||
desc_n = (tmpl.elts_n * (tmpl.sp ? MLX4_PMD_SGE_WR_N : 1));
|
||||
mbuf_n = desc_n;
|
||||
/* Toggle RX checksum offload if hardware supports it. */
|
||||
if (priv->hw_csum) {
|
||||
tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
|
||||
rxq->csum = tmpl.csum;
|
||||
}
|
||||
if (priv->hw_csum_l2tun) {
|
||||
tmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
|
||||
rxq->csum_l2tun = tmpl.csum_l2tun;
|
||||
}
|
||||
/* Enable scattered packets support for this queue if necessary. */
|
||||
assert(mb_len >= RTE_PKTMBUF_HEADROOM);
|
||||
if (dev->data->dev_conf.rxmode.enable_scatter &&
|
||||
@ -2808,11 +2753,6 @@ rxq_setup(struct rte_eth_dev *dev, struct rxq *rxq, uint16_t desc,
|
||||
" multiple of %d)", (void *)dev, MLX4_PMD_SGE_WR_N);
|
||||
return EINVAL;
|
||||
}
|
||||
/* Toggle RX checksum offload if hardware supports it. */
|
||||
if (priv->hw_csum)
|
||||
tmpl.csum = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
|
||||
if (priv->hw_csum_l2tun)
|
||||
tmpl.csum_l2tun = !!dev->data->dev_conf.rxmode.hw_ip_checksum;
|
||||
/* Enable scattered packets support for this queue if necessary. */
|
||||
assert(mb_len >= RTE_PKTMBUF_HEADROOM);
|
||||
if (dev->data->dev_conf.rxmode.max_rx_pkt_len <=
|
||||
@ -3416,18 +3356,8 @@ mlx4_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
|
||||
info->max_tx_queues = max;
|
||||
/* Last array entry is reserved for broadcast. */
|
||||
info->max_mac_addrs = 1;
|
||||
info->rx_offload_capa =
|
||||
(priv->hw_csum ?
|
||||
(DEV_RX_OFFLOAD_IPV4_CKSUM |
|
||||
DEV_RX_OFFLOAD_UDP_CKSUM |
|
||||
DEV_RX_OFFLOAD_TCP_CKSUM) :
|
||||
0);
|
||||
info->tx_offload_capa =
|
||||
(priv->hw_csum ?
|
||||
(DEV_TX_OFFLOAD_IPV4_CKSUM |
|
||||
DEV_TX_OFFLOAD_UDP_CKSUM |
|
||||
DEV_TX_OFFLOAD_TCP_CKSUM) :
|
||||
0);
|
||||
info->rx_offload_capa = 0;
|
||||
info->tx_offload_capa = 0;
|
||||
if (priv_get_ifname(priv, &ifname) == 0)
|
||||
info->if_index = if_nametoindex(ifname);
|
||||
info->speed_capa =
|
||||
@ -4655,19 +4585,6 @@ mlx4_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev)
|
||||
goto port_error;
|
||||
}
|
||||
|
||||
priv->hw_csum =
|
||||
((exp_device_attr.exp_device_cap_flags &
|
||||
IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) &&
|
||||
(exp_device_attr.exp_device_cap_flags &
|
||||
IBV_EXP_DEVICE_RX_CSUM_IP_PKT));
|
||||
DEBUG("checksum offloading is %ssupported",
|
||||
(priv->hw_csum ? "" : "not "));
|
||||
|
||||
priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags &
|
||||
IBV_EXP_DEVICE_VXLAN_SUPPORT);
|
||||
DEBUG("L2 tunnel checksum offloads are %ssupported",
|
||||
(priv->hw_csum_l2tun ? "" : "not "));
|
||||
|
||||
priv->inl_recv_size = mlx4_getenv_int("MLX4_INLINE_RECV_SIZE");
|
||||
|
||||
if (priv->inl_recv_size) {
|
||||
|
||||
@ -179,8 +179,6 @@ struct rxq {
|
||||
struct rxq_elt (*no_sp)[]; /* RX elements. */
|
||||
} elts;
|
||||
unsigned int sp:1; /* Use scattered RX elements. */
|
||||
unsigned int csum:1; /* Enable checksum offloading. */
|
||||
unsigned int csum_l2tun:1; /* Same for L2 tunnels. */
|
||||
struct mlx4_rxq_stats stats; /* RX queue counters. */
|
||||
unsigned int socket; /* CPU socket ID for allocations. */
|
||||
struct ibv_exp_res_domain *rd; /* Resource Domain. */
|
||||
@ -248,8 +246,6 @@ struct priv {
|
||||
uint16_t mtu; /* Configured MTU. */
|
||||
uint8_t port; /* Physical port number. */
|
||||
unsigned int started:1; /* Device started, flows enabled. */
|
||||
unsigned int hw_csum:1; /* Checksum offload is supported. */
|
||||
unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */
|
||||
unsigned int vf:1; /* This is a VF device. */
|
||||
unsigned int pending_alarm:1; /* An alarm is pending. */
|
||||
unsigned int isolated:1; /* Toggle isolated mode. */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user