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net/qede/base: update

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This patch updates the base driver and incorporates necessary changes
required to bring in the new firmware 8.10.9.0.

In addition, it would allow driver to add new functionalities that might
be needed in future.

Signed-off-by: Rasesh Mody <rasesh.mody@qlogic.com>
This commit is contained in:
Rasesh Mody 2016-10-18 21:11:25 -07:00 committed by Bruce Richardson
parent 252b88b58f
commit 22d07d939c
50 changed files with 6910 additions and 3578 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
doc/guides/nics/features/qede.ini
View File

@ -19,6 +19,8 @@ VLAN filter = Y
Flow control = Y
CRC offload = Y
VLAN offload = Y
L3 checksum offload = Y
L4 checksum offload = Y
Packet type parsing = Y
Basic stats = Y
Extended stats = Y

2
doc/guides/nics/features/qede_vf.ini
View File

@ -20,6 +20,8 @@ VLAN filter = Y
Flow control = Y
CRC offload = Y
VLAN offload = Y
L3 checksum offload = Y
L4 checksum offload = Y
Packet type parsing = Y
Basic stats = Y
Extended stats = Y

15
doc/guides/nics/qede.rst
View File

@ -32,7 +32,7 @@ QEDE Poll Mode Driver
======================
The QEDE poll mode driver library (**librte_pmd_qede**) implements support
for **QLogic FastLinQ QL4xxxx 25G/40G CNA** family of adapters as well
for **QLogic FastLinQ QL4xxxx 25G/40G/100G CNA** family of adapters as well
as their virtual functions (VF) in SR-IOV context. It is supported on
several standard Linux distros like RHEL7.x, SLES12.x and Ubuntu.
It is compile-tested under FreeBSD OS.
@ -55,14 +55,15 @@ Supported Features
- TSS
- Multiple MAC address
- Default pause flow control
- SR-IOV VF for 25G/40G modes
- SR-IOV VF
- MTU change
- Multiprocess aware
Non-supported Features
----------------------
- Scatter-Gather Rx/Tx frames
- Unequal number of Rx/Tx queues
- MTU change (dynamic)
- SR-IOV PF
- Tunneling offloads
- Reload of the PMD after a non-graceful termination
@ -75,10 +76,10 @@ Supported QLogic Adapters
Prerequisites
-------------
- Requires firmware version **8.7.x.** and management firmware
version **8.7.x or higher**. Firmware may be available
- Requires firmware version **8.10.x.** and management firmware
version **8.10.x or higher**. Firmware may be available
inbox in certain newer Linux distros under the standard directory
``E.g. /lib/firmware/qed/qed_init_values_zipped-8.7.7.0.bin``
``E.g. /lib/firmware/qed/qed_init_values_zipped-8.10.9.0.bin``
- If the required firmware files are not available then visit
`QLogic Driver Download Center <http://driverdownloads.qlogic.com>`_.
@ -120,7 +121,7 @@ enabling debugging options may affect system performance.
- ``CONFIG_RTE_LIBRTE_QEDE_FW`` (default **""**)
Gives absolute path of firmware file.
``Eg: "/lib/firmware/qed/qed_init_values_zipped-8.7.7.0.bin"``
``Eg: "/lib/firmware/qed/qed_init_values_zipped-8.10.9.0.bin"``
Empty string indicates driver will pick up the firmware file
from the default location.

6
drivers/net/qede/base/bcm_osal.h
View File

@ -9,8 +9,6 @@
#ifndef __BCM_OSAL_H
#define __BCM_OSAL_H
#include <string.h>
#include <rte_byteorder.h>
#include <rte_spinlock.h>
#include <rte_malloc.h>
@ -43,6 +41,8 @@ void qed_link_update(struct ecore_hwfn *hwfn);
#endif
#endif
#define OSAL_WARN(arg1, arg2, arg3, ...) (0)
/* Memory Types */
typedef uint8_t u8;
typedef uint16_t u16;
@ -330,6 +330,8 @@ u32 qede_find_first_zero_bit(unsigned long *, u32);
#define OSAL_IOV_VF_VPORT_UPDATE(hwfn, vfid, p_params, p_mask) 0
#define OSAL_VF_UPDATE_ACQUIRE_RESC_RESP(_dev_p, _resc_resp) 0
#define OSAL_IOV_GET_OS_TYPE() 0
#define OSAL_IOV_VF_MSG_TYPE(hwfn, vfid, vf_msg_type) 0
#define OSAL_IOV_PF_RESP_TYPE(hwfn, vfid, pf_resp_type) 0
u32 qede_unzip_data(struct ecore_hwfn *p_hwfn, u32 input_len,
u8 *input_buf, u32 max_size, u8 *unzip_buf);

166
drivers/net/qede/base/ecore.h
View File

@ -29,12 +29,13 @@
#include "mcp_public.h"
#define MAX_HWFNS_PER_DEVICE (4)
#define NAME_SIZE 64 /* @DPDK */
#define NAME_SIZE 128 /* @DPDK */
#define VER_SIZE 16
/* @DPDK ARRAY_DECL */
#define ECORE_WFQ_UNIT 100
#include "../qede_logs.h" /* @DPDK */
#define ISCSI_BDQ_ID(_port_id) (_port_id)
#define FCOE_BDQ_ID(_port_id) (_port_id + 2)
/* Constants */
#define ECORE_WID_SIZE (1024)
@ -153,8 +154,11 @@ enum DP_MODULE {
ECORE_MSG_IOV = 0x80000,
ECORE_MSG_SP = 0x100000,
ECORE_MSG_STORAGE = 0x200000,
ECORE_MSG_OOO = 0x200000,
ECORE_MSG_CXT = 0x800000,
ECORE_MSG_LL2 = 0x1000000,
ECORE_MSG_ILT = 0x2000000,
ECORE_MSG_RDMA = 0x4000000,
ECORE_MSG_DEBUG = 0x8000000,
/* to be added...up to 0x8000000 */
};
@ -174,6 +178,7 @@ struct ecore_sb_attn_info;
struct ecore_cxt_mngr;
struct ecore_dma_mem;
struct ecore_sb_sp_info;
struct ecore_ll2_info;
struct ecore_igu_info;
struct ecore_mcp_info;
struct ecore_dcbx_info;
@ -196,6 +201,7 @@ enum ecore_tunn_clss {
ECORE_TUNN_CLSS_MAC_VNI,
ECORE_TUNN_CLSS_INNER_MAC_VLAN,
ECORE_TUNN_CLSS_INNER_MAC_VNI,
ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE,
MAX_ECORE_TUNN_CLSS,
};
@ -228,35 +234,16 @@ struct ecore_tunn_update_params {
u8 tunn_clss_ipgre;
};
struct ecore_hw_sriov_info {
/* standard SRIOV capability fields, mostly for debugging */
int pos; /* capability position */
int nres; /* number of resources */
u32 cap; /* SR-IOV Capabilities */
u16 ctrl; /* SR-IOV Control */
u16 total_vfs; /* total VFs associated with the PF */
u16 num_vfs; /* number of vfs that have been started */
u64 active_vfs[3]; /* bitfield of active vfs */
#define ECORE_IS_VF_ACTIVE(_p_dev, _rel_vf_id) \
(!!(_p_dev->sriov_info.active_vfs[_rel_vf_id / 64] & \
(1ULL << (_rel_vf_id % 64))))
u16 initial_vfs; /* initial VFs associated with the PF */
u16 nr_virtfn; /* number of VFs available */
u16 offset; /* first VF Routing ID offset */
u16 stride; /* following VF stride */
u16 vf_device_id; /* VF device id */
u32 pgsz; /* page size for BAR alignment */
u8 link; /* Function Dependency Link */
bool b_hw_channel; /* Whether PF uses the HW-channel */
};
/* The PCI personality is not quite synonymous to protocol ID:
* 1. All personalities need CORE connections
* 2. The Ethernet personality may support also the RoCE protocol
* 2. The Ethernet personality may support also the RoCE/iWARP protocol
*/
enum ecore_pci_personality {
ECORE_PCI_ETH,
ECORE_PCI_FCOE,
ECORE_PCI_ISCSI,
ECORE_PCI_ETH_ROCE,
ECORE_PCI_IWARP,
ECORE_PCI_DEFAULT /* default in shmem */
};
@ -269,11 +256,10 @@ struct ecore_qm_iids {
#define MAX_PF_PER_PORT 8
/*@@@TBD MK RESC: need to remove and use MCP interface instead */
/* HW / FW resources, output of features supported below, most information
* is received from MFW.
*/
enum ECORE_RESOURCES {
enum ecore_resources {
ECORE_SB,
ECORE_L2_QUEUE,
ECORE_VPORT,
@ -282,24 +268,30 @@ enum ECORE_RESOURCES {
ECORE_RL,
ECORE_MAC,
ECORE_VLAN,
ECORE_RDMA_CNQ_RAM,
ECORE_ILT,
ECORE_LL2_QUEUE,
ECORE_CMDQS_CQS,
ECORE_MAX_RESC,
ECORE_RDMA_STATS_QUEUE,
ECORE_MAX_RESC, /* must be last */
};
/* Features that require resources, given as input to the resource management
* algorithm, the output are the resources above
*/
enum ECORE_FEATURE {
enum ecore_feature {
ECORE_PF_L2_QUE,
ECORE_PF_TC,
ECORE_VF,
ECORE_EXTRA_VF_QUE,
ECORE_VMQ,
ECORE_RDMA_CNQ,
ECORE_ISCSI_CQ,
ECORE_FCOE_CQ,
ECORE_MAX_FEATURES,
};
enum ECORE_PORT_MODE {
enum ecore_port_mode {
ECORE_PORT_MODE_DE_2X40G,
ECORE_PORT_MODE_DE_2X50G,
ECORE_PORT_MODE_DE_1X100G,
@ -308,11 +300,16 @@ enum ECORE_PORT_MODE {
ECORE_PORT_MODE_DE_4X20G,
ECORE_PORT_MODE_DE_1X40G,
ECORE_PORT_MODE_DE_2X25G,
ECORE_PORT_MODE_DE_1X25G
ECORE_PORT_MODE_DE_1X25G,
ECORE_PORT_MODE_DE_4X25G,
};
enum ecore_dev_cap {
ECORE_DEV_CAP_ETH,
ECORE_DEV_CAP_FCOE,
ECORE_DEV_CAP_ISCSI,
ECORE_DEV_CAP_ROCE,
ECORE_DEV_CAP_IWARP
};
#ifndef __EXTRACT__LINUX__
@ -341,10 +338,20 @@ struct ecore_hw_info {
RESC_NUM(_p_hwfn, resc))
#define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc])
u8 num_tc;
/* Amount of traffic classes HW supports */
u8 num_hw_tc;
/* Amount of TCs which should be active according to DCBx or upper layer driver
* configuration
*/
u8 num_active_tc;
/* Traffic class used for tcp out of order traffic */
u8 ooo_tc;
/* The traffic class used by PF for it's offloaded protocol */
u8 offload_tc;
u8 non_offload_tc;
u32 concrete_fid;
u16 opaque_fid;
@ -352,10 +359,14 @@ struct ecore_hw_info {
u32 part_num[4];
unsigned char hw_mac_addr[ETH_ALEN];
u64 node_wwn; /* For FCoE only */
u64 port_wwn; /* For FCoE only */
u16 num_iscsi_conns;
u16 num_fcoe_conns;
struct ecore_igu_info *p_igu_info;
/* Sriov */
u32 first_vf_in_pf;
u8 max_chains_per_vf;
u32 port_mode;
@ -429,6 +440,7 @@ struct ecore_qm_info {
u8 pf_wfq;
u32 pf_rl;
struct ecore_wfq_data *wfq_data;
u8 num_pf_rls;
};
struct storm_stats {
@ -466,6 +478,7 @@ struct ecore_hwfn {
bool hw_init_done;
u8 num_funcs_on_engine;
u8 enabled_func_idx;
/* BAR access */
void OSAL_IOMEM *regview;
@ -502,9 +515,17 @@ struct ecore_hwfn {
struct ecore_sb_attn_info *p_sb_attn;
/* Protocol related */
bool using_ll2;
struct ecore_ll2_info *p_ll2_info;
struct ecore_ooo_info *p_ooo_info;
struct ecore_iscsi_info *p_iscsi_info;
struct ecore_fcoe_info *p_fcoe_info;
struct ecore_rdma_info *p_rdma_info;
struct ecore_pf_params pf_params;
bool b_rdma_enabled_in_prs;
u32 rdma_prs_search_reg;
/* Array of sb_info of all status blocks */
struct ecore_sb_info *sbs_info[MAX_SB_PER_PF_MIMD];
u16 num_sbs;
@ -547,6 +568,10 @@ struct ecore_hwfn {
* calculate th
* doorbell address
*/
/* If one of the following is set then EDPM shouldn't be used */
u8 dcbx_no_edpm;
u8 db_bar_no_edpm;
};
#ifndef __EXTRACT__LINUX__
@ -557,6 +582,23 @@ enum ecore_mf_mode {
};
#endif
/* @DPDK */
struct ecore_dbg_feature {
u8 *dump_buf;
u32 buf_size;
u32 dumped_dwords;
};
enum qed_dbg_features {
DBG_FEATURE_BUS,
DBG_FEATURE_GRC,
DBG_FEATURE_IDLE_CHK,
DBG_FEATURE_MCP_TRACE,
DBG_FEATURE_REG_FIFO,
DBG_FEATURE_PROTECTION_OVERRIDE,
DBG_FEATURE_NUM
};
struct ecore_dev {
u32 dp_module;
u8 dp_level;
@ -608,7 +650,7 @@ struct ecore_dev {
(CHIP_REV_IS_EMUL_B0(_p_dev) || \
CHIP_REV_IS_FPGA_B0(_p_dev) || \
(_p_dev)->chip_rev == 1)
#define CHIP_REV_IS_ASIC(_p_dev) (!CHIP_REV_IS_SLOW(_p_dev))
#define CHIP_REV_IS_ASIC(_p_dev) !CHIP_REV_IS_SLOW(_p_dev)
#else
#define CHIP_REV_IS_A0(_p_dev) (!(_p_dev)->chip_rev)
#define CHIP_REV_IS_B0(_p_dev) ((_p_dev)->chip_rev == 1)
@ -630,12 +672,14 @@ struct ecore_dev {
enum ecore_mf_mode mf_mode;
#define IS_MF_DEFAULT(_p_hwfn) \
(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)
#define IS_MF_SI(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
#define IS_MF_SD(_p_hwfn) (((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
#define IS_MF_SI(_p_hwfn) \
(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_NPAR)
#define IS_MF_SD(_p_hwfn) \
(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_OVLAN)
int pcie_width;
int pcie_speed;
u8 ver_str[VER_SIZE];
u8 ver_str[NAME_SIZE]; /* @DPDK */
/* Add MF related configuration */
u8 mcp_rev;
u8 boot_mode;
@ -644,8 +688,8 @@ struct ecore_dev {
u32 int_mode;
enum ecore_coalescing_mode int_coalescing_mode;
u8 rx_coalesce_usecs;
u8 tx_coalesce_usecs;
u16 rx_coalesce_usecs;
u16 tx_coalesce_usecs;
/* Start Bar offset of first hwfn */
void OSAL_IOMEM *regview;
@ -665,13 +709,20 @@ struct ecore_dev {
struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
/* SRIOV */
struct ecore_hw_sriov_info sriov_info;
struct ecore_hw_sriov_info *p_iov_info;
#define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
bool b_hw_channel;
unsigned long tunn_mode;
#define IS_ECORE_SRIOV(edev) (!!((edev)->sriov_info.total_vfs))
bool b_is_vf;
u32 drv_type;
u32 rdma_max_sge;
u32 rdma_max_inline;
u32 rdma_max_srq_sge;
struct ecore_eth_stats *reset_stats;
struct ecore_fw_data *fw_data;
@ -680,6 +731,13 @@ struct ecore_dev {
/* Recovery */
bool recov_in_prog;
/* Indicates whether should prevent attentions from being reasserted */
bool attn_clr_en;
/* Indicates if the reg_fifo is checked after any register access */
bool chk_reg_fifo;
#ifndef ASIC_ONLY
bool b_is_emul_full;
#endif
@ -689,6 +747,9 @@ struct ecore_dev {
u64 fw_len;
#endif
/* @DPDK */
struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
u8 engine_for_debug;
};
#define NUM_OF_VFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_VFS_BB \
@ -702,12 +763,14 @@ struct ecore_dev {
#define NUM_OF_ENG_PFS(dev) (ECORE_IS_BB(dev) ? MAX_NUM_PFS_BB \
: MAX_NUM_PFS_K2)
#ifndef REAL_ASIC_ONLY
#define ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn) ( \
(ECORE_IS_BB_A0(p_hwfn->p_dev)) && \
(ECORE_PATH_ID(p_hwfn) == 1) && \
((p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X40G) || \
(p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X50G) || \
(p_hwfn->hw_info.port_mode == ECORE_PORT_MODE_DE_2X25G)))
#endif
/**
* @brief ecore_concrete_to_sw_fid - get the sw function id from
@ -736,18 +799,6 @@ static OSAL_INLINE u8 ecore_concrete_to_sw_fid(struct ecore_dev *p_dev,
#define PURE_LB_TC 8
#define OOO_LB_TC 9
static OSAL_INLINE u16 ecore_sriov_get_next_vf(struct ecore_hwfn *p_hwfn,
u16 rel_vf_id)
{
u16 i;
for (i = rel_vf_id; i < p_hwfn->p_dev->sriov_info.total_vfs; i++)
if (ECORE_IS_VF_ACTIVE(p_hwfn->p_dev, i))
return i;
return p_hwfn->p_dev->sriov_info.total_vfs;
}
int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,
u32 min_pf_rate);
@ -758,11 +809,6 @@ void ecore_clean_wfq_db(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
int ecore_device_num_engines(struct ecore_dev *p_dev);
int ecore_device_num_ports(struct ecore_dev *p_dev);
#define ecore_for_each_vf(_p_hwfn, _i) \
for (_i = ecore_sriov_get_next_vf(_p_hwfn, 0); \
_i < _p_hwfn->p_dev->sriov_info.total_vfs; \
_i = ecore_sriov_get_next_vf(_p_hwfn, _i + 1))
#define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
#endif /* __ECORE_H */

17
drivers/net/qede/base/ecore_chain.h
View File

@ -118,6 +118,8 @@ struct ecore_chain {
u16 next_page_mask;
struct ecore_chain_pbl pbl;
void *dp_ctx;
};
#define ECORE_CHAIN_PBL_ENTRY_SIZE (8)
@ -542,12 +544,13 @@ static OSAL_INLINE void ecore_chain_reset(struct ecore_chain *p_chain)
* @param intended_use
* @param mode
* @param cnt_type
* @param dp_ctx
*/
static OSAL_INLINE void
ecore_chain_init_params(struct ecore_chain *p_chain, u32 page_cnt, u8 elem_size,
enum ecore_chain_use_mode intended_use,
enum ecore_chain_mode mode,
enum ecore_chain_cnt_type cnt_type)
enum ecore_chain_cnt_type cnt_type, void *dp_ctx)
{
/* chain fixed parameters */
p_chain->p_virt_addr = OSAL_NULL;
@ -571,6 +574,8 @@ ecore_chain_init_params(struct ecore_chain *p_chain, u32 page_cnt, u8 elem_size,
p_chain->pbl.p_phys_table = 0;
p_chain->pbl.p_virt_table = OSAL_NULL;
p_chain->pbl.pp_virt_addr_tbl = OSAL_NULL;
p_chain->dp_ctx = dp_ctx;
}
/**
@ -723,4 +728,14 @@ static OSAL_INLINE void ecore_chain_pbl_zero_mem(struct ecore_chain *p_chain)
ECORE_CHAIN_PAGE_SIZE);
}
int ecore_chain_print(struct ecore_chain *p_chain, char *buffer,
u32 buffer_size, u32 *element_indx, u32 stop_indx,
bool print_metadata,
int (*func_ptr_print_element)(struct ecore_chain *p_chain,
void *p_element,
char *buffer),
int (*func_ptr_print_metadata)(struct ecore_chain
*p_chain,
char *buffer));
#endif /* __ECORE_CHAIN_H__ */

319
drivers/net/qede/base/ecore_cxt.c
View File

@ -18,6 +18,7 @@
#include "ecore_cxt.h"
#include "ecore_hw.h"
#include "ecore_dev_api.h"
#include "ecore_sriov.h"
/* Max number of connection types in HW (DQ/CDU etc.) */
#define MAX_CONN_TYPES PROTOCOLID_COMMON
@ -60,6 +61,14 @@ union conn_context {
struct eth_conn_context eth_ctx;
};
/* TYPE-0 task context - iSCSI, FCOE */
union type0_task_context {
};
/* TYPE-1 task context - ROCE */
union type1_task_context {
};
struct src_ent {
u8 opaque[56];
u64 next;
@ -71,6 +80,14 @@ struct src_ent {
#define CONN_CXT_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
#define SRQ_CXT_SIZE (sizeof(struct regpair) * 8) /* @DPDK */
#define TYPE0_TASK_CXT_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
/* Alignment is inherent to the type1_task_context structure */
#define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
/* PF per protocl configuration object */
#define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
#define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
@ -96,6 +113,7 @@ struct ecore_conn_type_cfg {
#define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2)
#define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2)
#define CDUC_BLK (0)
#define SRQ_BLK (0)
#define CDUT_SEG_BLK(n) (1 + (u8)(n))
#define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_##X##_SEGMENTS)
@ -105,6 +123,7 @@ enum ilt_clients {
ILT_CLI_QM,
ILT_CLI_TM,
ILT_CLI_SRC,
ILT_CLI_TSDM,
ILT_CLI_MAX
};
@ -172,6 +191,9 @@ struct ecore_cxt_mngr {
*/
u32 vf_count;
/* total number of SRQ's for this hwfn */
u32 srq_count;
/* Acquired CIDs */
struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
@ -179,6 +201,9 @@ struct ecore_cxt_mngr {
struct ecore_dma_mem *ilt_shadow;
u32 pf_start_line;
/* Mutex for a dynamic ILT allocation */
osal_mutex_t mutex;
/* SRC T2 */
struct ecore_dma_mem *t2;
u32 t2_num_pages;
@ -197,6 +222,11 @@ static OSAL_INLINE bool tm_cid_proto(enum protocol_type type)
return type == PROTOCOLID_TOE;
}
static bool tm_tid_proto(enum protocol_type type)
{
return type == PROTOCOLID_FCOE;
}
/* counts the iids for the CDU/CDUC ILT client configuration */
struct ecore_cdu_iids {
u32 pf_cids;
@ -255,6 +285,22 @@ static OSAL_INLINE void ecore_cxt_tm_iids(struct ecore_cxt_mngr *p_mngr,
iids->pf_cids += p_cfg->cid_count;
iids->per_vf_cids += p_cfg->cids_per_vf;
}
if (tm_tid_proto(i)) {
struct ecore_tid_seg *segs = p_cfg->tid_seg;
/* for each segment there is at most one
* protocol for which count is not 0.
*/
for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
iids->pf_tids[j] += segs[j].count;
/* The last array elelment is for the VFs. As for PF
* segments there can be only one protocol for
* which this value is not 0.
*/
iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
}
}
iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
@ -317,7 +363,7 @@ static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn *p_hwfn,
}
/* set the iids (cid/tid) count per protocol */
void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
enum protocol_type type,
u32 cid_count, u32 vf_cid_cnt)
{
@ -343,7 +389,7 @@ u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
}
static u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
enum protocol_type type)
{
u32 cnt = 0;
@ -671,12 +717,27 @@ enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn)
ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_TM);
p_cli->pf_total_lines = curr_line - p_blk->start_line;
for (i = 1; i < p_mngr->vf_count; i++) {
ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_TM);
}
p_cli->vf_total_lines = curr_line - p_blk->start_line;
}
/* TSDM (SRQ CONTEXT) */
total = ecore_cxt_get_srq_count(p_hwfn);
if (total) {
p_cli = &p_mngr->clients[ILT_CLI_TSDM];
p_blk = &p_cli->pf_blks[SRQ_BLK];
ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
ILT_CLI_TSDM);
p_cli->pf_total_lines = curr_line - p_blk->start_line;
}
if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
@ -788,7 +849,7 @@ static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
val = 0;
entries[j].next = OSAL_CPU_TO_BE64(val);
conn_num -= ent_per_page;
conn_num -= ent_num;
}
return ECORE_SUCCESS;
@ -847,7 +908,7 @@ ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
u32 lines, line, sz_left, lines_to_skip = 0;
/* Special handling for RoCE that supports dynamic allocation */
if (ilt_client == ILT_CLI_CDUT)
if (ilt_client == ILT_CLI_CDUT || ilt_client == ILT_CLI_TSDM)
return ECORE_SUCCESS;
lines_to_skip = p_blk->dynamic_line_cnt;
@ -994,6 +1055,7 @@ static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
{
struct ecore_ilt_client_cfg *clients;
struct ecore_cxt_mngr *p_mngr;
u32 i;
@ -1005,35 +1067,48 @@ enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
}
/* Initialize ILT client registers */
p_mngr->clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
p_mngr->clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
p_mngr->clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
clients = p_mngr->clients;
clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT);
clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
p_mngr->clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
p_mngr->clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
p_mngr->clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT);
clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT);
clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE);
p_mngr->clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
p_mngr->clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
p_mngr->clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT);
clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT);
clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE);
p_mngr->clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
p_mngr->clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
p_mngr->clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT);
clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT);
clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
p_mngr->clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
p_mngr->clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
p_mngr->clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT);
clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT);
clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
/* default ILT page size for all clients is 32K */
for (i = 0; i < ILT_CLI_MAX; i++)
p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
/* Initialize task sizes */
/* due to removal of ISCSI/FCoE files union type0_task_context
* task_type_size will be 0. So hardcoded for now.
*/
p_mngr->task_type_size[0] = 512; /* @DPDK */
p_mngr->task_type_size[1] = 128; /* @DPDK */
p_mngr->vf_count = p_hwfn->p_dev->sriov_info.total_vfs;
if (p_hwfn->p_dev->p_iov_info)
p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
/* Initialize the dynamic ILT allocation mutex */
OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
OSAL_MUTEX_INIT(&p_mngr->mutex);
/* Set the cxt mangr pointer priori to further allocations */
p_hwfn->p_cxt_mngr = p_mngr;
@ -1080,6 +1155,7 @@ void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
ecore_cid_map_free(p_hwfn);
ecore_cxt_src_t2_free(p_hwfn);
ecore_ilt_shadow_free(p_hwfn);
OSAL_MUTEX_DEALLOC(&p_mngr->mutex);
OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
p_hwfn->p_cxt_mngr = OSAL_NULL;
@ -1383,13 +1459,16 @@ static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
u32 blk_factor;
/* For simplicty we set the 'block' to be an ILT page */
if (p_hwfn->p_dev->p_iov_info) {
struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
STORE_RT_REG(p_hwfn,
PSWRQ2_REG_VF_BASE_RT_OFFSET,
p_hwfn->hw_info.first_vf_in_pf);
p_iov->first_vf_in_pf);
STORE_RT_REG(p_hwfn,
PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
p_hwfn->hw_info.first_vf_in_pf +
p_hwfn->p_dev->sriov_info.total_vfs);
p_iov->first_vf_in_pf + p_iov->total_vfs);
}
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
@ -1543,11 +1622,11 @@ static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0);
SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
(sizeof(cfg_word) / sizeof(u32)) *
(p_hwfn->hw_info.first_vf_in_pf + i);
(p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
}
@ -1581,7 +1660,7 @@ static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
(sizeof(cfg_word) / sizeof(u32)) *
(p_hwfn->hw_info.first_vf_in_pf + i);
(p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
}
@ -1611,15 +1690,26 @@ static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
/* @@@TBD how to enable the scan for the VFs */
}
static void ecore_prs_init_common(struct ecore_hwfn *p_hwfn)
static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
{
struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
struct ecore_tid_seg *p_tid;
/* If FCoE is active set the MAX OX_ID (tid) in the Parser */
if (!p_fcoe->cid_count)
return;
p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
STORE_RT_REG_AGG(p_hwfn,
PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
p_tid->count);
}
void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
{
/* CDU configuration */
ecore_cdu_init_common(p_hwfn);
ecore_prs_init_common(p_hwfn);
}
void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
@ -1631,6 +1721,7 @@ void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
ecore_ilt_init_pf(p_hwfn);
ecore_src_init_pf(p_hwfn);
ecore_tm_init_pf(p_hwfn);
ecore_prs_init_pf(p_hwfn);
}
enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
@ -1748,6 +1839,20 @@ enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
return ECORE_SUCCESS;
}
void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
{
struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
p_mgr->srq_count = num_srqs;
}
u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
{
struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
return p_mgr->srq_count;
}
enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
{
/* Set the number of required CORE connections */
@ -1815,6 +1920,123 @@ enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
return ECORE_SUCCESS;
}
/* This function is very RoCE oriented, if another protocol in the future
* will want this feature we'll need to modify the function to be more generic
*/
enum _ecore_status_t
ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
enum ecore_cxt_elem_type elem_type,
u32 iid)
{
u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
struct ecore_ilt_client_cfg *p_cli;
struct ecore_ilt_cli_blk *p_blk;
struct ecore_ptt *p_ptt;
dma_addr_t p_phys;
u64 ilt_hw_entry;
void *p_virt;
enum _ecore_status_t rc = ECORE_SUCCESS;
switch (elem_type) {
case ECORE_ELEM_CXT:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
elem_size = CONN_CXT_SIZE(p_hwfn);
p_blk = &p_cli->pf_blks[CDUC_BLK];
break;
case ECORE_ELEM_SRQ:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
elem_size = SRQ_CXT_SIZE;
p_blk = &p_cli->pf_blks[SRQ_BLK];
break;
case ECORE_ELEM_TASK:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
break;
default:
DP_NOTICE(p_hwfn, false,
"ECORE_INVALID elem type = %d", elem_type);
return ECORE_INVAL;
}
/* Calculate line in ilt */
hw_p_size = p_cli->p_size.val;
elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
line = p_blk->start_line + (iid / elems_per_p);
shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
/* If line is already allocated, do nothing, otherwise allocate it and
* write it to the PSWRQ2 registers.
* This section can be run in parallel from different contexts and thus
* a mutex protection is needed.
*/
OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
goto out0;
p_ptt = ecore_ptt_acquire(p_hwfn);
if (!p_ptt) {
DP_NOTICE(p_hwfn, false,
"ECORE_TIME_OUT on ptt acquire - dynamic allocation");
rc = ECORE_TIMEOUT;
goto out0;
}
p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
&p_phys,
p_blk->real_size_in_page);
if (!p_virt) {
rc = ECORE_NOMEM;
goto out1;
}
OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
p_blk->real_size_in_page;
/* compute absolute offset */
reg_offset = PSWRQ2_REG_ILT_MEMORY +
(line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
ilt_hw_entry = 0;
SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
SET_FIELD(ilt_hw_entry,
ILT_ENTRY_PHY_ADDR,
(p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
/* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
0 /* no flags */);
if (elem_type == ECORE_ELEM_CXT) {
u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
elems_per_p;
/* Update the relevant register in the parser */
ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
last_cid_allocated - 1);
if (!p_hwfn->b_rdma_enabled_in_prs) {
/* Enable RoCE search */
ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
p_hwfn->b_rdma_enabled_in_prs = true;
}
}
out1:
ecore_ptt_release(p_hwfn, p_ptt);
out0:
OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
return rc;
}
/* This function is very RoCE oriented, if another protocol in the future
* will want this feature we'll need to modify the function to be more generic
*/
@ -1823,8 +2045,8 @@ ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
enum ecore_cxt_elem_type elem_type,
u32 start_iid, u32 count)
{
u32 reg_offset, elem_size, hw_p_size, elems_per_p;
u32 start_line, end_line, shadow_start_line, shadow_end_line;
u32 reg_offset, elem_size, hw_p_size, elems_per_p;
struct ecore_ilt_client_cfg *p_cli;
struct ecore_ilt_cli_blk *p_blk;
u32 end_iid = start_iid + count;
@ -1832,10 +2054,26 @@ ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
u64 ilt_hw_entry = 0;
u32 i;
if (elem_type == ECORE_ELEM_CXT) {
switch (elem_type) {
case ECORE_ELEM_CXT:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
elem_size = CONN_CXT_SIZE(p_hwfn);
p_blk = &p_cli->pf_blks[CDUC_BLK];
break;
case ECORE_ELEM_SRQ:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
elem_size = SRQ_CXT_SIZE;
p_blk = &p_cli->pf_blks[SRQ_BLK];
break;
case ECORE_ELEM_TASK:
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
break;
default:
DP_NOTICE(p_hwfn, false,
"ECORE_INVALID elem type = %d", elem_type);
return ECORE_INVAL;
}
/* Calculate line in ilt */
@ -1874,9 +2112,14 @@ ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
((start_line++) * ILT_REG_SIZE_IN_BYTES *
ILT_ENTRY_IN_REGS);
ecore_wr(p_hwfn, p_ptt, reg_offset, U64_LO(ilt_hw_entry));
ecore_wr(p_hwfn, p_ptt, reg_offset + ILT_REG_SIZE_IN_BYTES,
U64_HI(ilt_hw_entry));
/* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
* wide-bus.
*/
ecore_dmae_host2grc(p_hwfn, p_ptt,
(u64)(osal_uintptr_t)&ilt_hw_entry,
reg_offset,
sizeof(ilt_hw_entry) / sizeof(u32),
0 /* no flags */);
}
ecore_ptt_release(p_hwfn, p_ptt);
@ -1905,6 +2148,12 @@ enum _ecore_status_t ecore_cxt_free_proto_ilt(struct ecore_hwfn *p_hwfn,
rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_TASK, 0,
ecore_cxt_get_proto_tid_count(p_hwfn,
proto));
if (rc)
return rc;
/* Free TSDM CXT */
rc = ecore_cxt_free_ilt_range(p_hwfn, ECORE_ELEM_SRQ, 0,
ecore_cxt_get_srq_count(p_hwfn));
return rc;
}

49
drivers/net/qede/base/ecore_cxt.h
View File

@ -13,24 +13,38 @@
#include "ecore_proto_if.h"
#include "ecore_cxt_api.h"
/* Tasks segments definitions */
#define ECORE_CXT_ISCSI_TID_SEG PROTOCOLID_ISCSI /* 0 */
#define ECORE_CXT_FCOE_TID_SEG PROTOCOLID_FCOE /* 1 */
#define ECORE_CXT_ROCE_TID_SEG PROTOCOLID_ROCE /* 2 */
enum ecore_cxt_elem_type {
ECORE_ELEM_CXT,
ECORE_ELEM_SRQ,
ECORE_ELEM_TASK
};
u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn *p_hwfn,
enum protocol_type type, u32 *vf_cid);
enum protocol_type type,
u32 *vf_cid);
u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
enum protocol_type type);
u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn *p_hwfn,
enum protocol_type type);
u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn);
#ifndef LINUX_REMOVE
/**
* @brief ecore_cxt_qm_iids - fills the cid/tid counts for the QM configuration
*
* @param p_hwfn
* @param iids [out], a structure holding all the counters
*/
void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids);
void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
struct ecore_qm_iids *iids);
#endif
/**
* @brief ecore_cxt_set_pf_params - Set the PF params for cxt init
@ -41,18 +55,6 @@ void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn, struct ecore_qm_iids *iids);
*/
enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn);
/**
* @brief ecore_cxt_set_proto_cid_count - Set the max cids per protocol for cxt
* init
*
* @param p_hwfn
* @param type
* @param cid_cnt - number of pf cids
* @param vf_cid_cnt - number of vf cids
*/
void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
enum protocol_type type,
u32 cid_cnt, u32 vf_cid_cnt);
/**
* @brief ecore_cxt_cfg_ilt_compute - compute ILT init parameters
*
@ -134,7 +136,24 @@ enum _ecore_status_t ecore_qm_reconf(struct ecore_hwfn *p_hwfn,
* @param p_hwfn
* @param cid
*/
void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid);
void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn,
u32 cid);
/**
* @brief ecore_cxt_get_tid_mem_info - function checks if the
* page containing the iid in the ilt is already
* allocated, if it is not it allocates the page.
*
* @param p_hwfn
* @param elem_type
* @param iid
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t
ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
enum ecore_cxt_elem_type elem_type,
u32 iid);
/**
* @brief ecore_cxt_free_proto_ilt - function frees ilt pages

15
drivers/net/qede/base/ecore_cxt_api.h
View File

@ -25,21 +25,6 @@ struct ecore_tid_mem {
u8 *blocks[MAX_TID_BLOCKS]; /* 4K */
};
static OSAL_INLINE void *get_task_mem(struct ecore_tid_mem *info, u32 tid)
{
/* note: waste is superfluous */
return (void *)(info->blocks[tid / info->num_tids_per_block] +
(tid % info->num_tids_per_block) * info->tid_size);
/* more elaborate alternative with no modulo
* u32 mask = info->tid_size * info->num_tids_per_block +
* info->waste - 1;
* u32 index = tid / info->num_tids_per_block;
* u32 offset = tid * info->tid_size + index * info->waste;
* return (void *)(blocks[index] + (offset & mask));
*/
}
/**
* @brief ecore_cxt_acquire - Acquire a new cid of a specific protocol type
*

581
drivers/net/qede/base/ecore_dcbx.c
View File

@ -15,7 +15,6 @@
#include "ecore_iro.h"
#define ECORE_DCBX_MAX_MIB_READ_TRY (100)
#define ECORE_MAX_PFC_PRIORITIES 8
#define ECORE_ETH_TYPE_DEFAULT (0)
#define ECORE_DCBX_INVALID_PRIORITY 0xFF
@ -24,7 +23,7 @@
* the traffic class corresponding to the priority.
*/
#define ECORE_DCBX_PRIO2TC(prio_tc_tbl, prio) \
((u32)(pri_tc_tbl >> ((7 - prio) * 4)) & 0x7)
((u32)(prio_tc_tbl >> ((7 - prio) * 4)) & 0x7)
static bool ecore_dcbx_app_ethtype(u32 app_info_bitmap)
{
@ -38,6 +37,18 @@ static bool ecore_dcbx_app_port(u32 app_info_bitmap)
DCBX_APP_SF_PORT) ? true : false;
}
static bool ecore_dcbx_ieee_app_port(u32 app_info_bitmap, u8 type)
{
u8 mfw_val = ECORE_MFW_GET_FIELD(app_info_bitmap, DCBX_APP_SF_IEEE);
/* Old MFW */
if (mfw_val == DCBX_APP_SF_IEEE_RESERVED)
return ecore_dcbx_app_port(app_info_bitmap);
return (mfw_val == type || mfw_val == DCBX_APP_SF_IEEE_TCP_UDP_PORT) ?
true : false;
}
static bool ecore_dcbx_default_tlv(u32 app_info_bitmap, u16 proto_id)
{
return (ecore_dcbx_app_ethtype(app_info_bitmap) &&
@ -62,6 +73,12 @@ static bool ecore_dcbx_ieee(u32 dcbx_cfg_bitmap)
DCBX_CONFIG_VERSION_IEEE) ? true : false;
}
static bool ecore_dcbx_local(u32 dcbx_cfg_bitmap)
{
return (ECORE_MFW_GET_FIELD(dcbx_cfg_bitmap, DCBX_CONFIG_VERSION) ==
DCBX_CONFIG_VERSION_STATIC) ? true : false;
}
/* @@@TBD A0 Eagle workaround */
void ecore_dcbx_eagle_workaround(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, bool set_to_pfc)
@ -83,8 +100,8 @@ ecore_dcbx_dp_protocol(struct ecore_hwfn *p_hwfn,
{
struct ecore_hw_info *p_info = &p_hwfn->hw_info;
enum dcbx_protocol_type id;
bool enable, update;
u8 prio, tc, size;
u8 prio, tc, size, update;
bool enable;
const char *name; /* @DPDK */
int i;
@ -102,8 +119,10 @@ ecore_dcbx_dp_protocol(struct ecore_hwfn *p_hwfn,
prio = p_data->arr[id].priority;
DP_INFO(p_hwfn,
"%s info: update %d, enable %d, prio %d, tc %d, num_tc %d\n",
name, update, enable, prio, tc, p_info->num_tc);
"%s info: update %d, enable %d, prio %d, tc %d,"
" num_active_tc %d dscp_enable = %d dscp_val = %d\n",
name, update, enable, prio, tc, p_info->num_active_tc,
p_data->arr[id].dscp_enable, p_data->arr[id].dscp_val);
}
}
@ -112,28 +131,42 @@ ecore_dcbx_set_pf_tcs(struct ecore_hw_info *p_info,
u8 tc, enum ecore_pci_personality personality)
{
/* QM reconf data */
if (p_info->personality == personality) {
if (personality == ECORE_PCI_ETH)
p_info->non_offload_tc = tc;
else
if (p_info->personality == personality)
p_info->offload_tc = tc;
}
}
void
ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,
struct ecore_hw_info *p_info,
struct ecore_hwfn *p_hwfn,
bool enable, bool update, u8 prio, u8 tc,
enum dcbx_protocol_type type,
enum ecore_pci_personality personality)
{
struct ecore_dcbx_dscp_params *dscp = &p_hwfn->p_dcbx_info->get.dscp;
/* PF update ramrod data */
p_data->arr[type].update = update;
p_data->arr[type].enable = enable;
p_data->arr[type].priority = prio;
p_data->arr[type].tc = tc;
p_data->arr[type].dscp_enable = dscp->enabled;
if (p_data->arr[type].dscp_enable) {
u8 i;
ecore_dcbx_set_pf_tcs(p_info, tc, personality);
for (i = 0; i < ECORE_DCBX_DSCP_SIZE; i++)
if (prio == dscp->dscp_pri_map[i]) {
p_data->arr[type].dscp_val = i;
break;
}
}
if (enable && p_data->arr[type].dscp_enable)
p_data->arr[type].update = UPDATE_DCB_DSCP;
else if (enable)
p_data->arr[type].update = UPDATE_DCB;
else
p_data->arr[type].update = DONT_UPDATE_DCB_DHCP;
ecore_dcbx_set_pf_tcs(&p_hwfn->hw_info, tc, personality);
}
/* Update app protocol data and hw_info fields with the TLV info */
@ -143,7 +176,6 @@ ecore_dcbx_update_app_info(struct ecore_dcbx_results *p_data,
bool enable, bool update, u8 prio, u8 tc,
enum dcbx_protocol_type type)
{
struct ecore_hw_info *p_info = &p_hwfn->hw_info;
enum ecore_pci_personality personality;
enum dcbx_protocol_type id;
const char *name; /* @DPDK */
@ -161,7 +193,7 @@ ecore_dcbx_update_app_info(struct ecore_dcbx_results *p_data,
personality = ecore_dcbx_app_update[i].personality;
name = ecore_dcbx_app_update[i].name;
ecore_dcbx_set_params(p_data, p_info, enable, update,
ecore_dcbx_set_params(p_data, p_hwfn, enable, update,
prio, tc, type, personality);
}
}
@ -197,7 +229,8 @@ ecore_dcbx_get_app_priority(u8 pri_bitmap, u8 *priority)
static bool
ecore_dcbx_get_app_protocol_type(struct ecore_hwfn *p_hwfn,
u32 app_prio_bitmap, u16 id, int *type)
u32 app_prio_bitmap, u16 id,
enum dcbx_protocol_type *type, bool ieee)
{
bool status = false;
@ -205,7 +238,11 @@ ecore_dcbx_get_app_protocol_type(struct ecore_hwfn *p_hwfn,
*type = DCBX_PROTOCOL_ETH;
status = true;
} else {
DP_ERR(p_hwfn, "Unsupported protocol %d\n", id);
*type = DCBX_MAX_PROTOCOL_TYPE;
DP_ERR(p_hwfn,
"No action required, App TLV id = 0x%x"
" app_prio_bitmap = 0x%x\n",
id, app_prio_bitmap);
}
return status;
@ -218,16 +255,18 @@ static enum _ecore_status_t
ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn,
struct ecore_dcbx_results *p_data,
struct dcbx_app_priority_entry *p_tbl, u32 pri_tc_tbl,
int count, bool dcbx_enabled)
int count, u8 dcbx_version)
{
enum _ecore_status_t rc = ECORE_SUCCESS;
u8 tc, priority, priority_map;
int i, type = -1;
enum dcbx_protocol_type type;
bool enable, ieee;
u16 protocol_id;
bool enable;
int i;
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "Num APP entries = %d\n", count);
ieee = (dcbx_version == DCBX_CONFIG_VERSION_IEEE);
/* Parse APP TLV */
for (i = 0; i < count; i++) {
protocol_id = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
@ -242,7 +281,8 @@ ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn,
tc = ECORE_DCBX_PRIO2TC(pri_tc_tbl, priority);
if (ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry,
protocol_id, &type)) {
protocol_id, &type,
ieee)) {
/* ETH always have the enable bit reset, as it gets
* vlan information per packet. For other protocols,
* should be set according to the dcbx_enabled
@ -267,7 +307,7 @@ ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn,
if (p_data->arr[type].update)
continue;
enable = (type == DCBX_PROTOCOL_ETH) ? false : dcbx_enabled;
enable = (type == DCBX_PROTOCOL_ETH) ? false : !!dcbx_version;
ecore_dcbx_update_app_info(p_data, p_hwfn, enable, true,
priority, tc, type);
}
@ -288,14 +328,11 @@ ecore_dcbx_process_mib_info(struct ecore_hwfn *p_hwfn)
struct dcbx_ets_feature *p_ets;
struct ecore_hw_info *p_info;
u32 pri_tc_tbl, flags;
bool dcbx_enabled;
u8 dcbx_version;
int num_entries;
/* If DCBx version is non zero, then negotiation was
* successfuly performed
*/
flags = p_hwfn->p_dcbx_info->operational.flags;
dcbx_enabled = ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION) != 0;
dcbx_version = ECORE_MFW_GET_FIELD(flags, DCBX_CONFIG_VERSION);
p_app = &p_hwfn->p_dcbx_info->operational.features.app;
p_tbl = p_app->app_pri_tbl;
@ -307,13 +344,14 @@ ecore_dcbx_process_mib_info(struct ecore_hwfn *p_hwfn)
num_entries = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_NUM_ENTRIES);
rc = ecore_dcbx_process_tlv(p_hwfn, &data, p_tbl, pri_tc_tbl,
num_entries, dcbx_enabled);
num_entries, dcbx_version);
if (rc != ECORE_SUCCESS)
return rc;
p_info->num_tc = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_ETS_MAX_TCS);
p_info->num_active_tc = ECORE_MFW_GET_FIELD(p_ets->flags,
DCBX_ETS_MAX_TCS);
data.pf_id = p_hwfn->rel_pf_id;
data.dcbx_enabled = dcbx_enabled;
data.dcbx_enabled = !!dcbx_version;
ecore_dcbx_dp_protocol(p_hwfn, &data);
@ -386,36 +424,92 @@ static void
ecore_dcbx_get_app_data(struct ecore_hwfn *p_hwfn,
struct dcbx_app_priority_feature *p_app,
struct dcbx_app_priority_entry *p_tbl,
struct ecore_dcbx_params *p_params)
struct ecore_dcbx_params *p_params, bool ieee)
{
struct ecore_app_entry *entry;
u8 pri_map;
int i;
p_params->app_willing = ECORE_MFW_GET_FIELD(p_app->flags,
DCBX_APP_WILLING);
p_params->app_valid = ECORE_MFW_GET_FIELD(p_app->flags,
DCBX_APP_ENABLED);
p_params->app_error = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_ERROR);
p_params->num_app_entries = ECORE_MFW_GET_FIELD(p_app->flags,
DCBX_APP_ENABLED);
for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++)
p_params->app_bitmap[i] = p_tbl[i].entry;
DCBX_APP_NUM_ENTRIES);
for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
entry = &p_params->app_entry[i];
if (ieee) {
u8 sf_ieee;
u32 val;
sf_ieee = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
DCBX_APP_SF_IEEE);
switch (sf_ieee) {
case DCBX_APP_SF_IEEE_RESERVED:
/* Old MFW */
val = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
DCBX_APP_SF);
entry->sf_ieee = val ?
ECORE_DCBX_SF_IEEE_TCP_UDP_PORT :
ECORE_DCBX_SF_IEEE_ETHTYPE;
break;
case DCBX_APP_SF_IEEE_ETHTYPE:
entry->sf_ieee = ECORE_DCBX_SF_IEEE_ETHTYPE;
break;
case DCBX_APP_SF_IEEE_TCP_PORT:
entry->sf_ieee = ECORE_DCBX_SF_IEEE_TCP_PORT;
break;
case DCBX_APP_SF_IEEE_UDP_PORT:
entry->sf_ieee = ECORE_DCBX_SF_IEEE_UDP_PORT;
break;
case DCBX_APP_SF_IEEE_TCP_UDP_PORT:
entry->sf_ieee =
ECORE_DCBX_SF_IEEE_TCP_UDP_PORT;
break;
}
} else {
entry->ethtype = !(ECORE_MFW_GET_FIELD(p_tbl[i].entry,
DCBX_APP_SF));
}
pri_map = ECORE_MFW_GET_FIELD(p_tbl[i].entry, DCBX_APP_PRI_MAP);
ecore_dcbx_get_app_priority(pri_map, &entry->prio);
entry->proto_id = ECORE_MFW_GET_FIELD(p_tbl[i].entry,
DCBX_APP_PROTOCOL_ID);
ecore_dcbx_get_app_protocol_type(p_hwfn, p_tbl[i].entry,
entry->proto_id,
&entry->proto_type, ieee);
}
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
"APP params: willing %d, valid %d\n",
p_params->app_willing, p_params->app_valid);
"APP params: willing %d, valid %d error = %d\n",
p_params->app_willing, p_params->app_valid,
p_params->app_error);
}
static void
ecore_dcbx_get_pfc_data(struct ecore_hwfn *p_hwfn,
u32 pfc, struct ecore_dcbx_params *p_params)
{
p_params->pfc_willing = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_WILLING);
p_params->max_pfc_tc = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_CAPS);
p_params->pfc_enabled = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_ENABLED);
p_params->pfc_bitmap = pfc;
u8 pfc_map;
p_params->pfc.willing = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_WILLING);
p_params->pfc.max_tc = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_CAPS);
p_params->pfc.enabled = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_ENABLED);
pfc_map = ECORE_MFW_GET_FIELD(pfc, DCBX_PFC_PRI_EN_BITMAP);
p_params->pfc.prio[0] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_0);
p_params->pfc.prio[1] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_1);
p_params->pfc.prio[2] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_2);
p_params->pfc.prio[3] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_3);
p_params->pfc.prio[4] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_4);
p_params->pfc.prio[5] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_5);
p_params->pfc.prio[6] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_6);
p_params->pfc.prio[7] = !!(pfc_map & DCBX_PFC_PRI_EN_BITMAP_PRI_7);
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
"PFC params: willing %d, pfc_bitmap %d\n",
p_params->pfc_willing, p_params->pfc_bitmap);
p_params->pfc.willing, pfc_map);
}
static void
@ -423,28 +517,34 @@ ecore_dcbx_get_ets_data(struct ecore_hwfn *p_hwfn,
struct dcbx_ets_feature *p_ets,
struct ecore_dcbx_params *p_params)
{
u32 bw_map[2], tsa_map[2], pri_map;
int i;
p_params->ets_willing = ECORE_MFW_GET_FIELD(p_ets->flags,
DCBX_ETS_WILLING);
p_params->ets_enabled = ECORE_MFW_GET_FIELD(p_ets->flags,
DCBX_ETS_ENABLED);
p_params->ets_cbs = ECORE_MFW_GET_FIELD(p_ets->flags, DCBX_ETS_CBS);
p_params->max_ets_tc = ECORE_MFW_GET_FIELD(p_ets->flags,
DCBX_ETS_MAX_TCS);
p_params->ets_pri_tc_tbl[0] = p_ets->pri_tc_tbl[0];
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
"ETS params: willing %d, pri_tc_tbl_0 %x max_ets_tc %d\n",
p_params->ets_willing, p_params->ets_pri_tc_tbl[0],
p_params->max_ets_tc);
"ETS params: willing %d, ets_cbs %d pri_tc_tbl_0 %x"
" max_ets_tc %d\n",
p_params->ets_willing, p_params->ets_cbs,
p_ets->pri_tc_tbl[0], p_params->max_ets_tc);
/* 8 bit tsa and bw data corresponding to each of the 8 TC's are
* encoded in a type u32 array of size 2.
*/
for (i = 0; i < 2; i++) {
p_params->ets_tc_tsa_tbl[i] = p_ets->tc_tsa_tbl[i];
p_params->ets_tc_bw_tbl[i] = p_ets->tc_bw_tbl[i];
bw_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[0]);
bw_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_bw_tbl[1]);
tsa_map[0] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[0]);
tsa_map[1] = OSAL_BE32_TO_CPU(p_ets->tc_tsa_tbl[1]);
pri_map = OSAL_BE32_TO_CPU(p_ets->pri_tc_tbl[0]);
for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) {
p_params->ets_tc_bw_tbl[i] = ((u8 *)bw_map)[i];
p_params->ets_tc_tsa_tbl[i] = ((u8 *)tsa_map)[i];
p_params->ets_pri_tc_tbl[i] = ECORE_DCBX_PRIO2TC(pri_map, i);
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
"elem %d bw_tbl %x tsa_tbl %x\n",
i, p_params->ets_tc_bw_tbl[i],
@ -457,9 +557,10 @@ ecore_dcbx_get_common_params(struct ecore_hwfn *p_hwfn,
struct dcbx_app_priority_feature *p_app,
struct dcbx_app_priority_entry *p_tbl,
struct dcbx_ets_feature *p_ets,
u32 pfc, struct ecore_dcbx_params *p_params)
u32 pfc, struct ecore_dcbx_params *p_params,
bool ieee)
{
ecore_dcbx_get_app_data(p_hwfn, p_app, p_tbl, p_params);
ecore_dcbx_get_app_data(p_hwfn, p_app, p_tbl, p_params, ieee);
ecore_dcbx_get_ets_data(p_hwfn, p_ets, p_params);
ecore_dcbx_get_pfc_data(p_hwfn, pfc, p_params);
@ -485,7 +586,8 @@ ecore_dcbx_get_local_params(struct ecore_hwfn *p_hwfn,
p_ets = &p_hwfn->p_dcbx_info->local_admin.features.ets;
pfc = p_hwfn->p_dcbx_info->local_admin.features.pfc;
ecore_dcbx_get_common_params(p_hwfn, p_app, p_tbl, p_ets, pfc, p_data);
ecore_dcbx_get_common_params(p_hwfn, p_app, p_tbl, p_ets, pfc, p_data,
false);
p_local->valid = true;
return ECORE_SUCCESS;
@ -510,7 +612,8 @@ ecore_dcbx_get_remote_params(struct ecore_hwfn *p_hwfn,
p_ets = &p_hwfn->p_dcbx_info->remote.features.ets;
pfc = p_hwfn->p_dcbx_info->remote.features.pfc;
ecore_dcbx_get_common_params(p_hwfn, p_app, p_tbl, p_ets, pfc, p_data);
ecore_dcbx_get_common_params(p_hwfn, p_app, p_tbl, p_ets, pfc, p_data,
false);
p_remote->valid = true;
return ECORE_SUCCESS;
@ -553,12 +656,15 @@ ecore_dcbx_get_operational_params(struct ecore_hwfn *p_hwfn,
p_operational->ieee = ecore_dcbx_ieee(flags);
p_operational->cee = ecore_dcbx_cee(flags);
p_operational->local = ecore_dcbx_local(flags);
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB,
"Version support: ieee %d, cee %d\n",
p_operational->ieee, p_operational->cee);
"Version support: ieee %d, cee %d, static %d\n",
p_operational->ieee, p_operational->cee,
p_operational->local);
ecore_dcbx_get_common_params(p_hwfn, p_app, p_tbl, p_ets, pfc, p_data);
ecore_dcbx_get_common_params(p_hwfn, p_app, p_tbl, p_ets, pfc, p_data,
p_operational->ieee);
ecore_dcbx_get_priority_info(p_hwfn, &p_operational->app_prio,
p_results);
err = ECORE_MFW_GET_FIELD(p_app->flags, DCBX_APP_ERROR);
@ -569,6 +675,35 @@ ecore_dcbx_get_operational_params(struct ecore_hwfn *p_hwfn,
return rc;
}
static enum _ecore_status_t
ecore_dcbx_get_dscp_params(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct ecore_dcbx_get *params)
{
struct ecore_dcbx_dscp_params *p_dscp;
struct dcb_dscp_map *p_dscp_map;
int i, j, entry;
u32 pri_map;
p_dscp = &params->dscp;
p_dscp_map = &p_hwfn->p_dcbx_info->dscp_map;
p_dscp->enabled = ECORE_MFW_GET_FIELD(p_dscp_map->flags,
DCB_DSCP_ENABLE);
/* MFW encodes 64 dscp entries into 8 element array of u32 entries,
* where each entry holds the 4bit priority map for 8 dscp entries.
*/
for (i = 0, entry = 0; i < ECORE_DCBX_DSCP_SIZE / 8; i++) {
pri_map = OSAL_BE32_TO_CPU(p_dscp_map->dscp_pri_map[i]);
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "elem %d pri_map 0x%x\n",
entry, pri_map);
for (j = 0; j < ECORE_DCBX_DSCP_SIZE / 8; j++, entry++)
p_dscp->dscp_pri_map[entry] = (u32)(pri_map >>
(j * 4)) & 0xf;
}
return ECORE_SUCCESS;
}
static enum _ecore_status_t
ecore_dcbx_get_local_lldp_params(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
@ -670,6 +805,7 @@ ecore_dcbx_read_remote_lldp_mib(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t rc = ECORE_SUCCESS;
struct ecore_dcbx_mib_meta_data data;
OSAL_MEM_ZERO(&data, sizeof(data));
data.addr = p_hwfn->mcp_info->port_addr + offsetof(struct public_port,
lldp_status_params);
data.lldp_remote = p_hwfn->p_dcbx_info->lldp_remote;
@ -687,6 +823,7 @@ ecore_dcbx_read_operational_mib(struct ecore_hwfn *p_hwfn,
struct ecore_dcbx_mib_meta_data data;
enum _ecore_status_t rc = ECORE_SUCCESS;
OSAL_MEM_ZERO(&data, sizeof(data));
data.addr = p_hwfn->mcp_info->port_addr +
offsetof(struct public_port, operational_dcbx_mib);
data.mib = &p_hwfn->p_dcbx_info->operational;
@ -704,6 +841,7 @@ ecore_dcbx_read_remote_mib(struct ecore_hwfn *p_hwfn,
struct ecore_dcbx_mib_meta_data data;
enum _ecore_status_t rc = ECORE_SUCCESS;
OSAL_MEM_ZERO(&data, sizeof(data));
data.addr = p_hwfn->mcp_info->port_addr +
offsetof(struct public_port, remote_dcbx_mib);
data.mib = &p_hwfn->p_dcbx_info->remote;
@ -729,6 +867,18 @@ ecore_dcbx_read_local_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
return rc;
}
static void
ecore_dcbx_read_dscp_mib(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
{
struct ecore_dcbx_mib_meta_data data;
data.addr = p_hwfn->mcp_info->port_addr +
offsetof(struct public_port, dcb_dscp_map);
data.dscp_map = &p_hwfn->p_dcbx_info->dscp_map;
data.size = sizeof(struct dcb_dscp_map);
ecore_memcpy_from(p_hwfn, p_ptt, data.dscp_map, data.addr, data.size);
}
static enum _ecore_status_t ecore_dcbx_read_mib(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
enum ecore_mib_read_type type)
@ -737,6 +887,7 @@ static enum _ecore_status_t ecore_dcbx_read_mib(struct ecore_hwfn *p_hwfn,
switch (type) {
case ECORE_DCBX_OPERATIONAL_MIB:
ecore_dcbx_read_dscp_mib(p_hwfn, p_ptt);
rc = ecore_dcbx_read_operational_mib(p_hwfn, p_ptt, type);
break;
case ECORE_DCBX_REMOTE_MIB:
@ -775,6 +926,9 @@ ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
return rc;
if (type == ECORE_DCBX_OPERATIONAL_MIB) {
ecore_dcbx_get_dscp_params(p_hwfn, p_ptt,
&p_hwfn->p_dcbx_info->get);
rc = ecore_dcbx_process_mib_info(p_hwfn);
if (!rc) {
bool enabled;
@ -795,6 +949,14 @@ ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
}
}
ecore_dcbx_get_params(p_hwfn, p_ptt, type);
/* Update the DSCP to TC mapping bit if required */
if ((type == ECORE_DCBX_OPERATIONAL_MIB) &&
p_hwfn->p_dcbx_info->dscp_nig_update) {
ecore_wr(p_hwfn, p_ptt, NIG_REG_DSCP_TO_TC_MAP_ENABLE, 0x1);
p_hwfn->p_dcbx_info->dscp_nig_update = false;
}
OSAL_DCBX_AEN(p_hwfn, type);
return rc;
@ -828,6 +990,8 @@ static void ecore_dcbx_update_protocol_data(struct protocol_dcb_data *p_data,
p_data->dcb_enable_flag = p_src->arr[type].enable;
p_data->dcb_priority = p_src->arr[type].priority;
p_data->dcb_tc = p_src->arr[type].tc;
p_data->dscp_enable_flag = p_src->arr[type].dscp_enable;
p_data->dscp_val = p_src->arr[type].dscp_val;
}
/* Set pf update ramrod command params */
@ -835,7 +999,7 @@ void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src,
struct pf_update_ramrod_data *p_dest)
{
struct protocol_dcb_data *p_dcb_data;
bool update_flag;
bool update_flag = false;
p_dest->pf_id = p_src->pf_id;
@ -887,3 +1051,302 @@ enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *p_hwfn,
return rc;
}
static void
ecore_dcbx_set_pfc_data(struct ecore_hwfn *p_hwfn,
u32 *pfc, struct ecore_dcbx_params *p_params)
{
u8 pfc_map = 0;
int i;
if (p_params->pfc.willing)
*pfc |= DCBX_PFC_WILLING_MASK;
else
*pfc &= ~DCBX_PFC_WILLING_MASK;
if (p_params->pfc.enabled)
*pfc |= DCBX_PFC_ENABLED_MASK;
else
*pfc &= ~DCBX_PFC_ENABLED_MASK;
*pfc &= ~DCBX_PFC_CAPS_MASK;
*pfc |= (u32)p_params->pfc.max_tc << DCBX_PFC_CAPS_SHIFT;
for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++)
if (p_params->pfc.prio[i])
pfc_map |= (0x1 << i);
*pfc |= (pfc_map << DCBX_PFC_PRI_EN_BITMAP_SHIFT);
DP_VERBOSE(p_hwfn, ECORE_MSG_DCB, "pfc = 0x%x\n", *pfc);
}
static void
ecore_dcbx_set_ets_data(struct ecore_hwfn *p_hwfn,
struct dcbx_ets_feature *p_ets,
struct ecore_dcbx_params *p_params)
{
u8 *bw_map, *tsa_map;
int i;
if (p_params->ets_willing)
p_ets->flags |= DCBX_ETS_WILLING_MASK;
else
p_ets->flags &= ~DCBX_ETS_WILLING_MASK;
if (p_params->ets_cbs)
p_ets->flags |= DCBX_ETS_CBS_MASK;
else
p_ets->flags &= ~DCBX_ETS_CBS_MASK;
if (p_params->ets_enabled)
p_ets->flags |= DCBX_ETS_ENABLED_MASK;
else
p_ets->flags &= ~DCBX_ETS_ENABLED_MASK;
p_ets->flags &= ~DCBX_ETS_MAX_TCS_MASK;
p_ets->flags |= (u32)p_params->max_ets_tc << DCBX_ETS_MAX_TCS_SHIFT;
bw_map = (u8 *)&p_ets->tc_bw_tbl[0];
tsa_map = (u8 *)&p_ets->tc_tsa_tbl[0];
p_ets->pri_tc_tbl[0] = 0;
for (i = 0; i < ECORE_MAX_PFC_PRIORITIES; i++) {
bw_map[i] = p_params->ets_tc_bw_tbl[i];
tsa_map[i] = p_params->ets_tc_tsa_tbl[i];
p_ets->pri_tc_tbl[0] |= (((u32)p_params->ets_pri_tc_tbl[i]) <<
((7 - i) * 4));
}
p_ets->pri_tc_tbl[0] = OSAL_CPU_TO_BE32(p_ets->pri_tc_tbl[0]);
for (i = 0; i < 2; i++) {
p_ets->tc_bw_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_bw_tbl[i]);
p_ets->tc_tsa_tbl[i] = OSAL_CPU_TO_BE32(p_ets->tc_tsa_tbl[i]);
}
}
static void
ecore_dcbx_set_app_data(struct ecore_hwfn *p_hwfn,
struct dcbx_app_priority_feature *p_app,
struct ecore_dcbx_params *p_params, bool ieee)
{
u32 *entry;
int i;
if (p_params->app_willing)
p_app->flags |= DCBX_APP_WILLING_MASK;
else
p_app->flags &= ~DCBX_APP_WILLING_MASK;
if (p_params->app_valid)
p_app->flags |= DCBX_APP_ENABLED_MASK;
else
p_app->flags &= ~DCBX_APP_ENABLED_MASK;
p_app->flags &= ~DCBX_APP_NUM_ENTRIES_MASK;
p_app->flags |= (u32)p_params->num_app_entries <<
DCBX_APP_NUM_ENTRIES_SHIFT;
for (i = 0; i < DCBX_MAX_APP_PROTOCOL; i++) {
entry = &p_app->app_pri_tbl[i].entry;
if (ieee) {
*entry &= ~DCBX_APP_SF_IEEE_MASK;
switch (p_params->app_entry[i].sf_ieee) {
case ECORE_DCBX_SF_IEEE_ETHTYPE:
*entry |= ((u32)DCBX_APP_SF_IEEE_ETHTYPE <<
DCBX_APP_SF_IEEE_SHIFT);
break;
case ECORE_DCBX_SF_IEEE_TCP_PORT:
*entry |= ((u32)DCBX_APP_SF_IEEE_TCP_PORT <<
DCBX_APP_SF_IEEE_SHIFT);
break;
case ECORE_DCBX_SF_IEEE_UDP_PORT:
*entry |= ((u32)DCBX_APP_SF_IEEE_UDP_PORT <<
DCBX_APP_SF_IEEE_SHIFT);
break;
case ECORE_DCBX_SF_IEEE_TCP_UDP_PORT:
*entry |= (u32)DCBX_APP_SF_IEEE_TCP_UDP_PORT <<
DCBX_APP_SF_IEEE_SHIFT;
break;
}
} else {
*entry &= ~DCBX_APP_SF_MASK;
if (p_params->app_entry[i].ethtype)
*entry |= ((u32)DCBX_APP_SF_ETHTYPE <<
DCBX_APP_SF_SHIFT);
else
*entry |= ((u32)DCBX_APP_SF_PORT <<
DCBX_APP_SF_SHIFT);
}
*entry &= ~DCBX_APP_PROTOCOL_ID_MASK;
*entry |= ((u32)p_params->app_entry[i].proto_id <<
DCBX_APP_PROTOCOL_ID_SHIFT);
*entry &= ~DCBX_APP_PRI_MAP_MASK;
*entry |= ((u32)(p_params->app_entry[i].prio) <<
DCBX_APP_PRI_MAP_SHIFT);
}
}
static enum _ecore_status_t
ecore_dcbx_set_local_params(struct ecore_hwfn *p_hwfn,
struct dcbx_local_params *local_admin,
struct ecore_dcbx_set *params)
{
bool ieee = false;
local_admin->flags = 0;
OSAL_MEMCPY(&local_admin->features,
&p_hwfn->p_dcbx_info->operational.features,
sizeof(struct dcbx_features));
if (params->enabled) {
local_admin->config = params->ver_num;
ieee = !!(params->ver_num & DCBX_CONFIG_VERSION_IEEE);
} else {
local_admin->config = DCBX_CONFIG_VERSION_DISABLED;
}
if (params->override_flags & ECORE_DCBX_OVERRIDE_PFC_CFG)
ecore_dcbx_set_pfc_data(p_hwfn, &local_admin->features.pfc,
&params->config.params);
if (params->override_flags & ECORE_DCBX_OVERRIDE_ETS_CFG)
ecore_dcbx_set_ets_data(p_hwfn, &local_admin->features.ets,
&params->config.params);
if (params->override_flags & ECORE_DCBX_OVERRIDE_APP_CFG)
ecore_dcbx_set_app_data(p_hwfn, &local_admin->features.app,
&params->config.params, ieee);
return ECORE_SUCCESS;
}
static enum _ecore_status_t
ecore_dcbx_set_dscp_params(struct ecore_hwfn *p_hwfn,
struct dcb_dscp_map *p_dscp_map,
struct ecore_dcbx_set *p_params)
{
int entry, i, j;
u32 val;
OSAL_MEMCPY(p_dscp_map, &p_hwfn->p_dcbx_info->dscp_map,
sizeof(*p_dscp_map));
if (p_params->dscp.enabled)
p_dscp_map->flags |= DCB_DSCP_ENABLE_MASK;
else
p_dscp_map->flags &= ~DCB_DSCP_ENABLE_MASK;
for (i = 0, entry = 0; i < 8; i++) {
val = 0;
for (j = 0; j < 8; j++, entry++)
val |= (((u32)p_params->dscp.dscp_pri_map[entry]) <<
(j * 4));
p_dscp_map->dscp_pri_map[i] = OSAL_CPU_TO_BE32(val);
}
p_hwfn->p_dcbx_info->dscp_nig_update = true;
return ECORE_SUCCESS;
}
enum _ecore_status_t ecore_dcbx_config_params(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct ecore_dcbx_set *params,
bool hw_commit)
{
enum _ecore_status_t rc = ECORE_SUCCESS;
struct ecore_dcbx_mib_meta_data data;
struct dcbx_local_params local_admin;
struct dcb_dscp_map dscp_map;
u32 resp = 0, param = 0;
if (!hw_commit) {
OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set, params,
sizeof(struct ecore_dcbx_set));
return ECORE_SUCCESS;
}
/* clear set-parmas cache */
OSAL_MEMSET(&p_hwfn->p_dcbx_info->set, 0,
sizeof(struct ecore_dcbx_set));
OSAL_MEMSET(&local_admin, 0, sizeof(local_admin));
ecore_dcbx_set_local_params(p_hwfn, &local_admin, params);
data.addr = p_hwfn->mcp_info->port_addr +
offsetof(struct public_port, local_admin_dcbx_mib);
data.local_admin = &local_admin;
data.size = sizeof(struct dcbx_local_params);
ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.local_admin, data.size);
if (params->override_flags & ECORE_DCBX_OVERRIDE_DSCP_CFG) {
OSAL_MEMSET(&dscp_map, 0, sizeof(dscp_map));
ecore_dcbx_set_dscp_params(p_hwfn, &dscp_map, params);
data.addr = p_hwfn->mcp_info->port_addr +
offsetof(struct public_port, dcb_dscp_map);
data.dscp_map = &dscp_map;
data.size = sizeof(struct dcb_dscp_map);
ecore_memcpy_to(p_hwfn, p_ptt, data.addr, data.dscp_map,
data.size);
}
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_DCBX,
1 << DRV_MB_PARAM_LLDP_SEND_SHIFT, &resp, &param);
if (rc != ECORE_SUCCESS) {
DP_NOTICE(p_hwfn, false,
"Failed to send DCBX update request\n");
return rc;
}
return rc;
}
enum _ecore_status_t ecore_dcbx_get_config_params(struct ecore_hwfn *p_hwfn,
struct ecore_dcbx_set *params)
{
struct ecore_dcbx_get *dcbx_info;
int rc;
if (p_hwfn->p_dcbx_info->set.config.valid) {
OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set,
sizeof(struct ecore_dcbx_set));
return ECORE_SUCCESS;
}
dcbx_info = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
sizeof(struct ecore_dcbx_get));
if (!dcbx_info) {
DP_ERR(p_hwfn, "Failed to allocate struct ecore_dcbx_info\n");
return ECORE_NOMEM;
}
rc = ecore_dcbx_query_params(p_hwfn, dcbx_info,
ECORE_DCBX_OPERATIONAL_MIB);
if (rc) {
OSAL_FREE(p_hwfn->p_dev, dcbx_info);
return rc;
}
p_hwfn->p_dcbx_info->set.override_flags = 0;
p_hwfn->p_dcbx_info->set.ver_num = DCBX_CONFIG_VERSION_DISABLED;
if (dcbx_info->operational.cee)
p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_CEE;
if (dcbx_info->operational.ieee)
p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_IEEE;
if (dcbx_info->operational.local)
p_hwfn->p_dcbx_info->set.ver_num |= DCBX_CONFIG_VERSION_STATIC;
p_hwfn->p_dcbx_info->set.enabled = dcbx_info->operational.enabled;
OSAL_MEMCPY(&p_hwfn->p_dcbx_info->set.config.params,
&dcbx_info->operational.params,
sizeof(struct ecore_dcbx_admin_params));
p_hwfn->p_dcbx_info->set.config.valid = true;
OSAL_MEMCPY(params, &p_hwfn->p_dcbx_info->set,
sizeof(struct ecore_dcbx_set));
OSAL_FREE(p_hwfn->p_dev, dcbx_info);
return ECORE_SUCCESS;
}

18
drivers/net/qede/base/ecore_dcbx.h
View File

@ -25,6 +25,8 @@ struct ecore_dcbx_info {
struct lldp_config_params_s lldp_local[LLDP_MAX_LLDP_AGENTS];
struct dcbx_local_params local_admin;
struct ecore_dcbx_results results;
struct dcb_dscp_map dscp_map;
bool dscp_nig_update;
struct dcbx_mib operational;
struct dcbx_mib remote;
struct ecore_dcbx_set set;
@ -32,10 +34,15 @@ struct ecore_dcbx_info {
u8 dcbx_cap;
};
/* Upper layer driver interface routines */
enum _ecore_status_t ecore_dcbx_config_params(struct ecore_hwfn *,
struct ecore_ptt *,
struct ecore_dcbx_set *);
struct ecore_dcbx_mib_meta_data {
struct lldp_config_params_s *lldp_local;
struct lldp_status_params_s *lldp_remote;
struct dcbx_local_params *local_admin;
struct dcb_dscp_map *dscp_map;
struct dcbx_mib *mib;
osal_size_t size;
u32 addr;
};
/* ECORE local interface routines */
enum _ecore_status_t
@ -48,8 +55,11 @@ enum _ecore_status_t ecore_dcbx_info_alloc(struct ecore_hwfn *p_hwfn);
void ecore_dcbx_info_free(struct ecore_hwfn *, struct ecore_dcbx_info *);
void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src,
struct pf_update_ramrod_data *p_dest);
#ifndef REAL_ASIC_ONLY
/* @@@TBD eagle phy workaround */
void ecore_dcbx_eagle_workaround(struct ecore_hwfn *, struct ecore_ptt *,
bool set_to_pfc);
#endif
#endif /* __ECORE_DCBX_H__ */

128
drivers/net/qede/base/ecore_dcbx_api.h
View File

@ -9,7 +9,7 @@
#ifndef __ECORE_DCBX_API_H__
#define __ECORE_DCBX_API_H__
#include "ecore.h"
#include "ecore_status.h"
#define DCBX_CONFIG_MAX_APP_PROTOCOL 4
@ -23,36 +23,32 @@ enum ecore_mib_read_type {
struct ecore_dcbx_app_data {
bool enable; /* DCB enabled */
bool update; /* Update indication */
u8 update; /* Update indication */
u8 priority; /* Priority */
u8 tc; /* Traffic Class */
bool dscp_enable; /* DSCP enabled */
u8 dscp_val; /* DSCP value */
};
#ifndef __EXTRACT__LINUX__
enum dcbx_protocol_type {
DCBX_PROTOCOL_ISCSI,
DCBX_PROTOCOL_FCOE,
DCBX_PROTOCOL_ROCE,
DCBX_PROTOCOL_ROCE_V2,
DCBX_PROTOCOL_ETH,
DCBX_MAX_PROTOCOL_TYPE
};
#ifdef LINUX_REMOVE
/* We can't assume THE HSI values are available to clients, so we need
* to redefine those here.
*/
#ifndef LLDP_CHASSIS_ID_STAT_LEN
#define LLDP_CHASSIS_ID_STAT_LEN 4
#endif
#ifndef LLDP_PORT_ID_STAT_LEN
#define LLDP_PORT_ID_STAT_LEN 4
#endif
#ifndef DCBX_MAX_APP_PROTOCOL
#define DCBX_MAX_APP_PROTOCOL 32
#endif
#endif
#define ECORE_LLDP_CHASSIS_ID_STAT_LEN 4
#define ECORE_LLDP_PORT_ID_STAT_LEN 4
#define ECORE_DCBX_MAX_APP_PROTOCOL 32
#define ECORE_MAX_PFC_PRIORITIES 8
#define ECORE_DCBX_DSCP_SIZE 64
struct ecore_dcbx_lldp_remote {
u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
u32 peer_chassis_id[ECORE_LLDP_CHASSIS_ID_STAT_LEN];
u32 peer_port_id[ECORE_LLDP_PORT_ID_STAT_LEN];
bool enable_rx;
bool enable_tx;
u32 tx_interval;
@ -60,29 +56,55 @@ struct ecore_dcbx_lldp_remote {
};
struct ecore_dcbx_lldp_local {
u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
u32 local_chassis_id[ECORE_LLDP_CHASSIS_ID_STAT_LEN];
u32 local_port_id[ECORE_LLDP_PORT_ID_STAT_LEN];
};
struct ecore_dcbx_app_prio {
u8 roce;
u8 roce_v2;
u8 fcoe;
u8 iscsi;
u8 eth;
};
struct ecore_dbcx_pfc_params {
bool willing;
bool enabled;
u8 prio[ECORE_MAX_PFC_PRIORITIES];
u8 max_tc;
};
enum ecore_dcbx_sf_ieee_type {
ECORE_DCBX_SF_IEEE_ETHTYPE,
ECORE_DCBX_SF_IEEE_TCP_PORT,
ECORE_DCBX_SF_IEEE_UDP_PORT,
ECORE_DCBX_SF_IEEE_TCP_UDP_PORT
};
struct ecore_app_entry {
bool ethtype;
enum ecore_dcbx_sf_ieee_type sf_ieee;
bool enabled;
u8 prio;
u16 proto_id;
enum dcbx_protocol_type proto_type;
};
struct ecore_dcbx_params {
u32 app_bitmap[DCBX_MAX_APP_PROTOCOL];
struct ecore_app_entry app_entry[ECORE_DCBX_MAX_APP_PROTOCOL];
u16 num_app_entries;
bool app_willing;
bool app_valid;
bool app_error;
bool ets_willing;
bool ets_enabled;
bool ets_cbs;
bool valid; /* Indicate validity of params */
u32 ets_pri_tc_tbl[1];
u32 ets_tc_bw_tbl[2];
u32 ets_tc_tsa_tbl[2];
bool pfc_willing;
bool pfc_enabled;
u32 pfc_bitmap;
u8 max_pfc_tc;
u8 ets_pri_tc_tbl[ECORE_MAX_PFC_PRIORITIES];
u8 ets_tc_bw_tbl[ECORE_MAX_PFC_PRIORITIES];
u8 ets_tc_tsa_tbl[ECORE_MAX_PFC_PRIORITIES];
struct ecore_dbcx_pfc_params pfc;
u8 max_ets_tc;
};
@ -103,22 +125,40 @@ struct ecore_dcbx_operational_params {
bool enabled;
bool ieee;
bool cee;
bool local;
u32 err;
};
struct ecore_dcbx_dscp_params {
bool enabled;
u8 dscp_pri_map[ECORE_DCBX_DSCP_SIZE];
};
struct ecore_dcbx_get {
struct ecore_dcbx_operational_params operational;
struct ecore_dcbx_lldp_remote lldp_remote;
struct ecore_dcbx_lldp_local lldp_local;
struct ecore_dcbx_remote_params remote;
struct ecore_dcbx_admin_params local;
struct ecore_dcbx_dscp_params dscp;
};
#endif
#define ECORE_DCBX_VERSION_DISABLED 0
#define ECORE_DCBX_VERSION_IEEE 1
#define ECORE_DCBX_VERSION_CEE 2
struct ecore_dcbx_set {
struct ecore_dcbx_admin_params config;
#define ECORE_DCBX_OVERRIDE_STATE (1 << 0)
#define ECORE_DCBX_OVERRIDE_PFC_CFG (1 << 1)
#define ECORE_DCBX_OVERRIDE_ETS_CFG (1 << 2)
#define ECORE_DCBX_OVERRIDE_APP_CFG (1 << 3)
#define ECORE_DCBX_OVERRIDE_DSCP_CFG (1 << 4)
u32 override_flags;
bool enabled;
struct ecore_dcbx_admin_params config;
u32 ver_num;
struct ecore_dcbx_dscp_params dscp;
};
struct ecore_dcbx_results {
@ -133,27 +173,23 @@ struct ecore_dcbx_app_metadata {
enum ecore_pci_personality personality;
};
struct ecore_dcbx_mib_meta_data {
struct lldp_config_params_s *lldp_local;
struct lldp_status_params_s *lldp_remote;
struct dcbx_local_params *local_admin;
struct dcbx_mib *mib;
osal_size_t size;
u32 addr;
};
void
ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,
struct ecore_hw_info *p_info,
bool enable, bool update, u8 prio, u8 tc,
enum dcbx_protocol_type type,
enum ecore_pci_personality personality);
enum _ecore_status_t ecore_dcbx_query_params(struct ecore_hwfn *,
struct ecore_dcbx_get *,
enum ecore_mib_read_type);
enum _ecore_status_t ecore_dcbx_get_config_params(struct ecore_hwfn *,
struct ecore_dcbx_set *);
enum _ecore_status_t ecore_dcbx_config_params(struct ecore_hwfn *,
struct ecore_ptt *,
struct ecore_dcbx_set *,
bool);
static const struct ecore_dcbx_app_metadata ecore_dcbx_app_update[] = {
{DCBX_PROTOCOL_ISCSI, "ISCSI", ECORE_PCI_ISCSI},
{DCBX_PROTOCOL_FCOE, "FCOE", ECORE_PCI_FCOE},
{DCBX_PROTOCOL_ROCE, "ROCE", ECORE_PCI_ETH_ROCE},
{DCBX_PROTOCOL_ROCE_V2, "ROCE_V2", ECORE_PCI_ETH_ROCE},
{DCBX_PROTOCOL_ETH, "ETH", ECORE_PCI_ETH}
};

1557
drivers/net/qede/base/ecore_dev.c
View File

File diff suppressed because it is too large Load Diff

100
drivers/net/qede/base/ecore_dev_api.h
View File

@ -13,8 +13,6 @@
#include "ecore_chain.h"
#include "ecore_int_api.h"
struct ecore_tunn_start_params;
/**
* @brief ecore_init_dp - initialize the debug level
*
@ -108,6 +106,7 @@ enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev);
*/
void ecore_hw_stop_fastpath(struct ecore_dev *p_dev);
#ifndef LINUX_REMOVE
/**
* @brief ecore_prepare_hibernate -should be called when
* the system is going into the hibernate state
@ -116,6 +115,7 @@ void ecore_hw_stop_fastpath(struct ecore_dev *p_dev);
*
*/
void ecore_prepare_hibernate(struct ecore_dev *p_dev);
#endif
/**
* @brief ecore_hw_start_fastpath -restart fastpath traffic,
@ -135,15 +135,25 @@ void ecore_hw_start_fastpath(struct ecore_hwfn *p_hwfn);
*/
enum _ecore_status_t ecore_hw_reset(struct ecore_dev *p_dev);
struct ecore_hw_prepare_params {
/* personality to initialize */
int personality;
/* force the driver's default resource allocation */
bool drv_resc_alloc;
/* check the reg_fifo after any register access */
bool chk_reg_fifo;
};
/**
* @brief ecore_hw_prepare -
*
* @param p_dev
* @param personality - personality to initialize
* @param p_params
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev, int personality);
enum _ecore_status_t ecore_hw_prepare(struct ecore_dev *p_dev,
struct ecore_hw_prepare_params *p_params);
/**
* @brief ecore_hw_remove -
@ -422,28 +432,50 @@ enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
* @param p_filter - MAC to remove
*/
void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u8 *p_filter);
struct ecore_ptt *p_ptt,
u8 *p_filter);
enum ecore_llh_port_filter_type_t {
ECORE_LLH_FILTER_ETHERTYPE,
ECORE_LLH_FILTER_TCP_SRC_PORT,
ECORE_LLH_FILTER_TCP_DEST_PORT,
ECORE_LLH_FILTER_TCP_SRC_AND_DEST_PORT,
ECORE_LLH_FILTER_UDP_SRC_PORT,
ECORE_LLH_FILTER_UDP_DEST_PORT,
ECORE_LLH_FILTER_UDP_SRC_AND_DEST_PORT
};
/**
* @brief ecore_llh_add_ethertype_filter - configures a ethertype filter in llh
* @brief ecore_llh_add_protocol_filter - configures a protocol filter in llh
*
* @param p_hwfn
* @param p_ptt
* @param filter - ethertype to add
* @param source_port_or_eth_type - source port or ethertype to add
* @param dest_port - destination port to add
* @param type - type of filters and comparing
*/
enum _ecore_status_t ecore_llh_add_ethertype_filter(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t
ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 filter);
u16 source_port_or_eth_type,
u16 dest_port,
enum ecore_llh_port_filter_type_t type);
/**
* @brief ecore_llh_remove_ethertype_filter - removes a ethertype llh filter
* @brief ecore_llh_remove_protocol_filter - remove a protocol filter in llh
*
* @param p_hwfn
* @param p_ptt
* @param filter - ethertype to remove
* @param source_port_or_eth_type - source port or ethertype to add
* @param dest_port - destination port to add
* @param type - type of filters and comparing
*/
void ecore_llh_remove_ethertype_filter(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u16 filter);
void
ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 source_port_or_eth_type,
u16 dest_port,
enum ecore_llh_port_filter_type_t type);
/**
* @brief ecore_llh_clear_all_filters - removes all MAC filters from llh
@ -455,7 +487,17 @@ void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
/**
*@brief Cleanup of previous driver remains prior to load
* @brief ecore_llh_set_function_as_default - set function as default per port
*
* @param p_hwfn
* @param p_ptt
*/
enum _ecore_status_t
ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
/**
*@brief Cleanup of previous driver remains prior to load
*
* @param p_hwfn
* @param p_ptt
@ -464,47 +506,45 @@ void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 id, bool is_vf);
/**
* @brief ecore_test_registers - Perform register tests
*
* @param p_hwfn
* @param p_ptt
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_test_registers(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
enum _ecore_status_t ecore_final_cleanup(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 id,
bool is_vf);
/**
* @brief ecore_set_rxq_coalesce - Configure coalesce parameters for an Rx queue
* The fact that we can configure coalescing to up to 511, but on varying
* accuracy [the bigger the value the less accurate] up to a mistake of 3usec
* for the highest values.
*
* @param p_hwfn
* @param p_ptt
* @param coalesce - Coalesce value in micro seconds.
* @param qid - Queue index.
* @param qid - SB Id
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_set_rxq_coalesce(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u8 coalesce, u8 qid);
u16 coalesce, u8 qid, u16 sb_id);
/**
* @brief ecore_set_txq_coalesce - Configure coalesce parameters for a Tx queue
* While the API allows setting coalescing per-qid, all tx queues sharing a
* SB should be in same range [i.e., either 0-0x7f, 0x80-0xff or 0x100-0x1ff]
* otherwise configuration would break.
*
* @param p_hwfn
* @param p_ptt
* @param coalesce - Coalesce value in micro seconds.
* @param qid - Queue index.
* @param qid - SB Id
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_set_txq_coalesce(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u8 coalesce, u8 qid);
u16 coalesce, u8 qid, u16 sb_id);
#endif

120
drivers/net/qede/base/ecore_hsi_eth.h
View File

@ -246,11 +246,11 @@ struct xstorm_eth_conn_ag_ctx {
#define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
u8 edpm_event_id /* byte2 */;
__le16 physical_q0 /* physical_q0 */;
__le16 word1 /* physical_q1 */;
__le16 quota /* physical_q1 */;
__le16 edpm_num_bds /* physical_q2 */;
__le16 tx_bd_cons /* word3 */;
__le16 tx_bd_prod /* word4 */;
__le16 go_to_bd_cons /* word5 */;
__le16 tx_class /* word5 */;
__le16 conn_dpi /* conn_dpi */;
u8 byte3 /* byte3 */;
u8 byte4 /* byte4 */;
@ -306,7 +306,7 @@ struct ystorm_eth_conn_st_ctx {
struct ystorm_eth_conn_ag_ctx {
u8 byte0 /* cdu_validation */;
u8 byte1 /* state */;
u8 state /* state */;
u8 flags0;
#define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1
#define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0
@ -335,7 +335,7 @@ struct ystorm_eth_conn_ag_ctx {
#define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6
#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1
#define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7
u8 byte2 /* byte2 */;
u8 tx_q0_int_coallecing_timeset /* byte2 */;
u8 byte3 /* byte3 */;
__le16 word0 /* word0 */;
__le32 terminate_spqe /* reg0 */;
@ -635,9 +635,8 @@ enum eth_event_opcode {
ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
ETH_EVENT_RX_ADD_UDP_FILTER,
ETH_EVENT_RX_DELETE_UDP_FILTER,
ETH_EVENT_RX_ADD_GFT_FILTER,
ETH_EVENT_RX_DELETE_GFT_FILTER,
ETH_EVENT_RX_CREATE_GFT_ACTION,
ETH_EVENT_RX_GFT_UPDATE_FILTER,
MAX_ETH_EVENT_OPCODE
};
@ -732,21 +731,19 @@ enum eth_ramrod_cmd_id {
ETH_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
ETH_RAMROD_FILTERS_UPDATE /* Add or Remove Mac/Vlan/Pair filters */,
ETH_RAMROD_RX_QUEUE_UPDATE /* RX Queue Update Ramrod */,
ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION
/* RX - Create an Openflow Action */,
ETH_RAMROD_RX_ADD_OPENFLOW_FILTER
/* RX - Add an Openflow Filter to the Searcher */,
ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER
/* RX - Delete an Openflow Filter to the Searcher */,
ETH_RAMROD_RX_ADD_UDP_FILTER /* RX - Add a UDP Filter to the Searcher */
,
ETH_RAMROD_RX_DELETE_UDP_FILTER
/* RX - Delete a UDP Filter to the Searcher */,
ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create an Gft Action */,
ETH_RAMROD_RX_DELETE_GFT_FILTER
/* RX - Delete an GFT Filter to the Searcher */,
ETH_RAMROD_RX_ADD_GFT_FILTER
/* RX - Add an GFT Filter to the Searcher */,
/* RX - Create an Openflow Action */
ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
/* RX - Add an Openflow Filter to the Searcher */
ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
/* RX - Delete an Openflow Filter to the Searcher */
ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
/* RX - Add a UDP Filter to the Searcher */
ETH_RAMROD_RX_ADD_UDP_FILTER,
/* RX - Delete a UDP Filter to the Searcher */
ETH_RAMROD_RX_DELETE_UDP_FILTER,
ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */,
/* RX - Add/Delete a GFT Filter to the Searcher */
ETH_RAMROD_GFT_UPDATE_FILTER,
MAX_ETH_RAMROD_CMD_ID
};
@ -911,14 +908,21 @@ struct eth_vport_tx_mode {
};
/*
* Ramrod data for rx add gft filter data
* Ramrod data for rx create gft action
*/
struct rx_add_gft_filter_data {
struct regpair pkt_hdr_addr /* Packet Header That Defines GFT Filter */
;
__le16 action_icid /* ICID of Action to run for this filter */;
__le16 pkt_hdr_length /* Packet Header Length */;
u8 reserved[4];
enum gft_filter_update_action {
GFT_ADD_FILTER,
GFT_DELETE_FILTER,
MAX_GFT_FILTER_UPDATE_ACTION
};
/*
* Ramrod data for rx create gft action
*/
enum gft_logic_filter_type {
GFT_FILTER_TYPE /* flow FW is GFT-logic as well */,
RFS_FILTER_TYPE /* flow FW is A-RFS-logic */,
MAX_GFT_LOGIC_FILTER_TYPE
};
/*
@ -990,7 +994,13 @@ struct rx_queue_start_ramrod_data {
u8 notify_en;
u8 toggle_val
/* Initial value for the toggle valid bit - used in PMD mode */;
u8 reserved[7];
/* Index of RX producers in VF zone. Used for VF only. */
u8 vf_rx_prod_index;
/* Backward compatibility mode. If set, unprotected mStorm queue zone will used
* for VF RX producers instead of VF zone.
*/
u8 vf_rx_prod_use_zone_a;
u8 reserved[5];
__le16 reserved1 /* FW reserved. */;
struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */;
struct regpair bd_base /* bd address of the first bd page */;
@ -1046,13 +1056,33 @@ struct rx_udp_filter_data {
};
/*
* Ramrod data for rx queue start ramrod
* Ramrod to add filter - filter is packet headr of type of packet wished to
* pass certin FW flow
*/
struct rx_update_gft_filter_data {
/* Pointer to Packet Header That Defines GFT Filter */
struct regpair pkt_hdr_addr;
__le16 pkt_hdr_length /* Packet Header Length */;
/* If is_rfs flag is set: Queue Id to associate filter with else: action icid */
__le16 rx_qid_or_action_icid;
/* Field is used if is_rfs flag is set: vport Id of which to associate filter
* with
*/
u8 vport_id;
/* Use enum to set type of flow using gft HW logic blocks */
u8 filter_type;
u8 filter_action /* Use to set type of action on filter */;
u8 reserved;
};
/*
* Ramrod data for tx queue start ramrod
*/
struct tx_queue_start_ramrod_data {
__le16 sb_id /* Status block ID */;
u8 sb_index /* Status block protocol index */;
u8 vport_id /* VPort ID */;
u8 reserved0 /* FW reserved. */;
u8 reserved0 /* FW reserved. (qcn_rl_en) */;
u8 stats_counter_id /* Statistics counter ID to use */;
__le16 qm_pq_id /* QM PQ ID */;
u8 flags;
@ -1076,10 +1106,16 @@ struct tx_queue_start_ramrod_data {
__le16 pxp_st_index /* PXP command Steering tag index */;
__le16 comp_agg_size /* TX completion min agg size - for PMD queues */;
__le16 queue_zone_id /* queue zone ID to use */;
__le16 test_dup_count /* In Test Mode, number of duplications */;
__le16 reserved2 /* FW reserved. (test_dup_count) */;
__le16 pbl_size /* Number of BD pages pointed by PBL */;
__le16 tx_queue_id
/* unique Queue ID - currently used only by PMD flow */;
/* Unique Same-As-Last Resource ID - improves performance for same-as-last
* packets per connection (range 0..ETH_TX_NUM_SAME_AS_LAST_ENTRIES-1 IDs
* available)
*/
__le16 same_as_last_id;
__le16 reserved[3];
struct regpair pbl_base_addr /* address of the pbl page */;
struct regpair bd_cons_address
/* BD consumer address in host - for PMD queues */;
@ -1124,12 +1160,16 @@ struct vport_start_ramrod_data {
u8 handle_ptp_pkts /* If set, the vport handles PTP Timesync Packets */
;
u8 silent_vlan_removal_en;
/* If enable then innerVlan will be striped and not written to cqe */
/* If enable then innerVlan will be striped and not written to cqe */
u8 untagged;
struct eth_tx_err_vals tx_err_behav
/* Desired behavior per TX error type */;
u8 zero_placement_offset;
u8 reserved[7];
/* If set, Contorl frames will be filtered according to MAC check. */
u8 ctl_frame_mac_check_en;
/* If set, Contorl frames will be filtered according to ethtype check. */
u8 ctl_frame_ethtype_check_en;
u8 reserved[5];
};
/*
@ -1459,8 +1499,8 @@ struct mstorm_eth_conn_ag_ctx {
__le32 reg1 /* reg1 */;
};
/* @DPDK: xstormEthConnAgCtxDqExtLdPart */
struct xstorm_eth_conn_ag_ctx_dq_ext_ld_part {
struct xstormEthConnAgCtxDqExtLdPart {
u8 reserved0 /* cdu_validation */;
u8 eth_state /* state */;
u8 flags0;
@ -1672,11 +1712,11 @@ struct xstorm_eth_conn_ag_ctx_dq_ext_ld_part {
#define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6
u8 edpm_event_id /* byte2 */;
__le16 physical_q0 /* physical_q0 */;
__le16 word1 /* physical_q1 */;
__le16 quota /* physical_q1 */;
__le16 edpm_num_bds /* physical_q2 */;
__le16 tx_bd_cons /* word3 */;
__le16 tx_bd_prod /* word4 */;
__le16 go_to_bd_cons /* word5 */;
__le16 tx_class /* word5 */;
__le16 conn_dpi /* conn_dpi */;
u8 byte3 /* byte3 */;
u8 byte4 /* byte4 */;
@ -1901,11 +1941,11 @@ struct xstorm_eth_hw_conn_ag_ctx {
#define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6
u8 edpm_event_id /* byte2 */;
__le16 physical_q0 /* physical_q0 */;
__le16 word1 /* physical_q1 */;
__le16 quota /* physical_q1 */;
__le16 edpm_num_bds /* physical_q2 */;
__le16 tx_bd_cons /* word3 */;
__le16 tx_bd_prod /* word4 */;
__le16 go_to_bd_cons /* word5 */;
__le16 tx_class /* word5 */;
__le16 conn_dpi /* conn_dpi */;
};

212
drivers/net/qede/base/ecore_hw.c
View File

@ -23,27 +23,28 @@
#define ECORE_BAR_ACQUIRE_TIMEOUT 1000
/* Invalid values */
#define ECORE_BAR_INVALID_OFFSET -1
#define ECORE_BAR_INVALID_OFFSET (OSAL_CPU_TO_LE32(-1))
struct ecore_ptt {
osal_list_entry_t list_entry;
unsigned int idx;
struct pxp_ptt_entry pxp;
u8 hwfn_id;
};
struct ecore_ptt_pool {
osal_list_t free_list;
osal_spinlock_t lock;
osal_spinlock_t lock; /* ptt synchronized access */
struct ecore_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM];
};
enum _ecore_status_t ecore_ptt_pool_alloc(struct ecore_hwfn *p_hwfn)
{
struct ecore_ptt_pool *p_pool;
struct ecore_ptt_pool *p_pool = OSAL_ALLOC(p_hwfn->p_dev,
GFP_KERNEL,
sizeof(*p_pool));
int i;
p_pool = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
sizeof(struct ecore_ptt_pool));
if (!p_pool)
return ECORE_NOMEM;
@ -52,6 +53,7 @@ enum _ecore_status_t ecore_ptt_pool_alloc(struct ecore_hwfn *p_hwfn)
p_pool->ptts[i].idx = i;
p_pool->ptts[i].pxp.offset = ECORE_BAR_INVALID_OFFSET;
p_pool->ptts[i].pxp.pretend.control = 0;
p_pool->ptts[i].hwfn_id = p_hwfn->my_id;
/* There are special PTT entries that are taken only by design.
* The rest are added ot the list for general usage.
@ -95,32 +97,36 @@ struct ecore_ptt *ecore_ptt_acquire(struct ecore_hwfn *p_hwfn)
/* Take the free PTT from the list */
for (i = 0; i < ECORE_BAR_ACQUIRE_TIMEOUT; i++) {
OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
if (!OSAL_LIST_IS_EMPTY(&p_hwfn->p_ptt_pool->free_list))
break;
OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
OSAL_MSLEEP(1);
}
/* We should not time-out, but it can happen... --> Lock isn't held */
if (i == ECORE_BAR_ACQUIRE_TIMEOUT) {
DP_NOTICE(p_hwfn, true, "Failed to allocate PTT\n");
return OSAL_NULL;
}
p_ptt = OSAL_LIST_FIRST_ENTRY(&p_hwfn->p_ptt_pool->free_list,
if (!OSAL_LIST_IS_EMPTY(&p_hwfn->p_ptt_pool->free_list)) {
p_ptt = OSAL_LIST_FIRST_ENTRY(
&p_hwfn->p_ptt_pool->free_list,
struct ecore_ptt, list_entry);
OSAL_LIST_REMOVE_ENTRY(&p_ptt->list_entry,
&p_hwfn->p_ptt_pool->free_list);
OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
DP_VERBOSE(p_hwfn, ECORE_MSG_HW, "allocated ptt %d\n", p_ptt->idx);
DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
"allocated ptt %d\n", p_ptt->idx);
return p_ptt;
}
OSAL_SPIN_UNLOCK(&p_hwfn->p_ptt_pool->lock);
OSAL_MSLEEP(1);
}
DP_NOTICE(p_hwfn, true,
"PTT acquire timeout - failed to allocate PTT\n");
return OSAL_NULL;
}
void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
{
/* This PTT should not be set to pretend if it is being released */
/* TODO - add some pretend sanity checks, to make sure pretend
* isn't set on this ptt
*/
OSAL_SPIN_LOCK(&p_hwfn->p_ptt_pool->lock);
OSAL_LIST_PUSH_HEAD(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list);
@ -130,7 +136,7 @@ void ecore_ptt_release(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
u32 ecore_ptt_get_hw_addr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
{
/* The HW is using DWORDS and we need to translate it to Bytes */
return p_ptt->pxp.offset << 2;
return OSAL_LE32_TO_CPU(p_ptt->pxp.offset) << 2;
}
static u32 ecore_ptt_config_addr(struct ecore_ptt *p_ptt)
@ -161,11 +167,12 @@ void ecore_ptt_set_win(struct ecore_hwfn *p_hwfn,
p_ptt->idx, new_hw_addr);
/* The HW is using DWORDS and the address is in Bytes */
p_ptt->pxp.offset = new_hw_addr >> 2;
p_ptt->pxp.offset = OSAL_CPU_TO_LE32(new_hw_addr >> 2);
REG_WR(p_hwfn,
ecore_ptt_config_addr(p_ptt) +
OFFSETOF(struct pxp_ptt_entry, offset), p_ptt->pxp.offset);
OFFSETOF(struct pxp_ptt_entry, offset),
OSAL_LE32_TO_CPU(p_ptt->pxp.offset));
}
static u32 ecore_set_ptt(struct ecore_hwfn *p_hwfn,
@ -176,6 +183,11 @@ static u32 ecore_set_ptt(struct ecore_hwfn *p_hwfn,
offset = hw_addr - win_hw_addr;
if (p_ptt->hwfn_id != p_hwfn->my_id)
DP_NOTICE(p_hwfn, true,
"ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n",
p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id);
/* Verify the address is within the window */
if (hw_addr < win_hw_addr ||
offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) {
@ -198,11 +210,37 @@ struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,
return &p_hwfn->p_ptt_pool->ptts[ptt_idx];
}
static bool ecore_is_reg_fifo_empty(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
bool is_empty = true;
u32 bar_addr;
if (!p_hwfn->p_dev->chk_reg_fifo)
goto out;
/* ecore_rd() cannot be used here since it calls this function */
bar_addr = ecore_set_ptt(p_hwfn, p_ptt, GRC_REG_TRACE_FIFO_VALID_DATA);
is_empty = REG_RD(p_hwfn, bar_addr) == 0;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
OSAL_UDELAY(100);
#endif
out:
return is_empty;
}
void ecore_wr(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u32 hw_addr, u32 val)
{
u32 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
bool prev_fifo_err;
u32 bar_addr;
prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
REG_WR(p_hwfn, bar_addr, val);
DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
"bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
@ -212,12 +250,21 @@ void ecore_wr(struct ecore_hwfn *p_hwfn,
if (CHIP_REV_IS_SLOW(p_hwfn->p_dev))
OSAL_UDELAY(100);
#endif
OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
"reg_fifo err was caused by a call to ecore_wr(0x%x, 0x%x)\n",
hw_addr, val);
}
u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr)
{
u32 bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
u32 val = REG_RD(p_hwfn, bar_addr);
bool prev_fifo_err;
u32 bar_addr, val;
prev_fifo_err = !ecore_is_reg_fifo_empty(p_hwfn, p_ptt);
bar_addr = ecore_set_ptt(p_hwfn, p_ptt, hw_addr);
val = REG_RD(p_hwfn, bar_addr);
DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
"bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n",
@ -228,6 +275,10 @@ u32 ecore_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u32 hw_addr)
OSAL_UDELAY(100);
#endif
OSAL_WARN(!prev_fifo_err && !ecore_is_reg_fifo_empty(p_hwfn, p_ptt),
"reg_fifo error was caused by a call to ecore_rd(0x%x)\n",
hw_addr);
return val;
}
@ -292,60 +343,59 @@ void ecore_memcpy_to(struct ecore_hwfn *p_hwfn,
void ecore_fid_pretend(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u16 fid)
{
void *p_pretend;
u16 control = 0;
SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1);
SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1);
/* Every pretend undos prev pretends, including previous port pretend */
SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID))
fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID);
p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
p_ptt->pxp.pretend.fid.concrete_fid.fid = OSAL_CPU_TO_LE16(fid);
p_pretend = &p_ptt->pxp.pretend;
REG_WR(p_hwfn,
ecore_ptt_config_addr(p_ptt) +
OFFSETOF(struct pxp_ptt_entry, pretend), *(u32 *)p_pretend);
OFFSETOF(struct pxp_ptt_entry, pretend),
*(u32 *)&p_ptt->pxp.pretend);
}
void ecore_port_pretend(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u8 port_id)
{
void *p_pretend;
u16 control = 0;
SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id);
SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1);
SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
p_ptt->pxp.pretend.control = control;
p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
p_pretend = &p_ptt->pxp.pretend;
REG_WR(p_hwfn,
ecore_ptt_config_addr(p_ptt) +
OFFSETOF(struct pxp_ptt_entry, pretend), *(u32 *)p_pretend);
OFFSETOF(struct pxp_ptt_entry, pretend),
*(u32 *)&p_ptt->pxp.pretend);
}
void ecore_port_unpretend(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
{
void *p_pretend;
u16 control = 0;
SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0);
SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0);
SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1);
p_ptt->pxp.pretend.control = control;
p_pretend = &p_ptt->pxp.pretend;
p_ptt->pxp.pretend.control = OSAL_CPU_TO_LE16(control);
REG_WR(p_hwfn,
ecore_ptt_config_addr(p_ptt) +
OFFSETOF(struct pxp_ptt_entry, pretend), *(u32 *)p_pretend);
OFFSETOF(struct pxp_ptt_entry, pretend),
*(u32 *)&p_ptt->pxp.pretend);
}
u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)
@ -442,15 +492,16 @@ static u32 ecore_dmae_idx_to_go_cmd(u8 idx)
{
OSAL_BUILD_BUG_ON((DMAE_REG_GO_C31 - DMAE_REG_GO_C0) != 31 * 4);
return DMAE_REG_GO_C0 + idx * 4;
/* All the DMAE 'go' registers form an array in internal memory */
return DMAE_REG_GO_C0 + (idx << 2);
}
static enum _ecore_status_t
ecore_dmae_post_command(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
{
struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd;
enum _ecore_status_t ecore_status = ECORE_SUCCESS;
u8 idx_cmd = p_hwfn->dmae_info.channel, i;
enum _ecore_status_t ecore_status = ECORE_SUCCESS;
/* verify address is not OSAL_NULL */
if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) ||
@ -459,13 +510,14 @@ ecore_dmae_post_command(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
"source or destination address 0 idx_cmd=%d\n"
"opcode = [0x%08x,0x%04x] len=0x%x"
" src=0x%x:%x dst=0x%x:%x\n",
idx_cmd, (u32)p_command->opcode,
(u16)p_command->opcode_b,
(int)p_command->length_dw,
(int)p_command->src_addr_hi,
(int)p_command->src_addr_lo,
(int)p_command->dst_addr_hi,
(int)p_command->dst_addr_lo);
idx_cmd,
OSAL_LE32_TO_CPU(p_command->opcode),
OSAL_LE16_TO_CPU(p_command->opcode_b),
OSAL_LE16_TO_CPU(p_command->length_dw),
OSAL_LE32_TO_CPU(p_command->src_addr_hi),
OSAL_LE32_TO_CPU(p_command->src_addr_lo),
OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
return ECORE_INVAL;
}
@ -473,12 +525,14 @@ ecore_dmae_post_command(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
"Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x]"
"len=0x%x src=0x%x:%x dst=0x%x:%x\n",
idx_cmd, (u32)p_command->opcode,
(u16)p_command->opcode_b,
(int)p_command->length_dw,
(int)p_command->src_addr_hi,
(int)p_command->src_addr_lo,
(int)p_command->dst_addr_hi, (int)p_command->dst_addr_lo);
idx_cmd,
OSAL_LE32_TO_CPU(p_command->opcode),
OSAL_LE16_TO_CPU(p_command->opcode_b),
OSAL_LE16_TO_CPU(p_command->length_dw),
OSAL_LE32_TO_CPU(p_command->src_addr_hi),
OSAL_LE32_TO_CPU(p_command->src_addr_lo),
OSAL_LE32_TO_CPU(p_command->dst_addr_hi),
OSAL_LE32_TO_CPU(p_command->dst_addr_lo));
/* Copy the command to DMAE - need to do it before every call
* for source/dest address no reset.
@ -514,8 +568,7 @@ enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn)
if (*p_comp == OSAL_NULL) {
DP_NOTICE(p_hwfn, true,
"Failed to allocate `p_completion_word'\n");
ecore_dmae_info_free(p_hwfn);
return ECORE_NOMEM;
goto err;
}
p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr;
@ -524,8 +577,7 @@ enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn)
if (*p_cmd == OSAL_NULL) {
DP_NOTICE(p_hwfn, true,
"Failed to allocate `struct dmae_cmd'\n");
ecore_dmae_info_free(p_hwfn);
return ECORE_NOMEM;
goto err;
}
p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr;
@ -534,14 +586,15 @@ enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn)
if (*p_buff == OSAL_NULL) {
DP_NOTICE(p_hwfn, true,
"Failed to allocate `intermediate_buffer'\n");
ecore_dmae_info_free(p_hwfn);
return ECORE_NOMEM;
goto err;
}
/* DMAE_E4_TODO : Need to change this to reflect proper channel */
p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id;
return ECORE_SUCCESS;
err:
ecore_dmae_info_free(p_hwfn);
return ECORE_NOMEM;
}
void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn)
@ -598,9 +651,6 @@ static enum _ecore_status_t ecore_dmae_operation_wait(struct ecore_hwfn *p_hwfn)
*/
OSAL_BARRIER(p_hwfn->p_dev);
while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) {
/* DMAE_E4_TODO : using OSAL_MSLEEP instead of mm_wait since mm
* functions are getting depriciated. Need to review for future.
*/
OSAL_UDELAY(DMAE_MIN_WAIT_TIME);
if (++wait_cnt > wait_cnt_limit) {
DP_NOTICE(p_hwfn->p_dev, ECORE_MSG_HW,
@ -629,7 +679,7 @@ ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u64 src_addr,
u64 dst_addr,
u8 src_type, u8 dst_type, u32 length)
u8 src_type, u8 dst_type, u32 length_dw)
{
dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr;
struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
@ -638,16 +688,16 @@ ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
switch (src_type) {
case ECORE_DMAE_ADDRESS_GRC:
case ECORE_DMAE_ADDRESS_HOST_PHYS:
cmd->src_addr_hi = DMA_HI(src_addr);
cmd->src_addr_lo = DMA_LO(src_addr);
cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(src_addr));
cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(src_addr));
break;
/* for virt source addresses we use the intermediate buffer. */
case ECORE_DMAE_ADDRESS_HOST_VIRT:
cmd->src_addr_hi = DMA_HI(phys);
cmd->src_addr_lo = DMA_LO(phys);
cmd->src_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
cmd->src_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
OSAL_MEMCPY(&p_hwfn->dmae_info.p_intermediate_buffer[0],
(void *)(osal_uintptr_t)src_addr,
length * sizeof(u32));
length_dw * sizeof(u32));
break;
default:
return ECORE_INVAL;
@ -656,26 +706,26 @@ ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
switch (dst_type) {
case ECORE_DMAE_ADDRESS_GRC:
case ECORE_DMAE_ADDRESS_HOST_PHYS:
cmd->dst_addr_hi = DMA_HI(dst_addr);
cmd->dst_addr_lo = DMA_LO(dst_addr);
cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(dst_addr));
cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(dst_addr));
break;
/* for virt destination address we use the intermediate buff. */
case ECORE_DMAE_ADDRESS_HOST_VIRT:
cmd->dst_addr_hi = DMA_HI(phys);
cmd->dst_addr_lo = DMA_LO(phys);
cmd->dst_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
cmd->dst_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
break;
default:
return ECORE_INVAL;
}
cmd->length_dw = (u16)length;
cmd->length_dw = OSAL_CPU_TO_LE16((u16)length_dw);
if (src_type == ECORE_DMAE_ADDRESS_HOST_VIRT ||
src_type == ECORE_DMAE_ADDRESS_HOST_PHYS)
OSAL_DMA_SYNC(p_hwfn->p_dev,
(void *)HILO_U64(cmd->src_addr_hi,
cmd->src_addr_lo),
length * sizeof(u32), false);
length_dw * sizeof(u32), false);
ecore_dmae_post_command(p_hwfn, p_ptt);
@ -687,21 +737,21 @@ ecore_dmae_execute_sub_operation(struct ecore_hwfn *p_hwfn,
OSAL_DMA_SYNC(p_hwfn->p_dev,
(void *)HILO_U64(cmd->src_addr_hi,
cmd->src_addr_lo),
length * sizeof(u32), true);
length_dw * sizeof(u32), true);
if (ecore_status != ECORE_SUCCESS) {
DP_NOTICE(p_hwfn, ECORE_MSG_HW,
"ecore_dmae_host2grc: Wait Failed. source_addr"
" 0x%lx, grc_addr 0x%lx, size_in_dwords 0x%x\n",
(unsigned long)src_addr, (unsigned long)dst_addr,
length);
length_dw);
return ecore_status;
}
if (dst_type == ECORE_DMAE_ADDRESS_HOST_VIRT)
OSAL_MEMCPY((void *)(osal_uintptr_t)(dst_addr),
&p_hwfn->dmae_info.p_intermediate_buffer[0],
length * sizeof(u32));
length_dw * sizeof(u32));
return ECORE_SUCCESS;
}
@ -719,18 +769,18 @@ ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr;
u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0;
struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd;
enum _ecore_status_t ecore_status = ECORE_SUCCESS;
u64 src_addr_split = 0, dst_addr_split = 0;
u16 length_limit = DMAE_MAX_RW_SIZE;
enum _ecore_status_t ecore_status = ECORE_SUCCESS;
u32 offset = 0;
ecore_dmae_opcode(p_hwfn,
(src_type == ECORE_DMAE_ADDRESS_GRC),
(dst_type == ECORE_DMAE_ADDRESS_GRC), p_params);
cmd->comp_addr_lo = DMA_LO(phys);
cmd->comp_addr_hi = DMA_HI(phys);
cmd->comp_val = DMAE_COMPLETION_VAL;
cmd->comp_addr_lo = OSAL_CPU_TO_LE32(DMA_LO(phys));
cmd->comp_addr_hi = OSAL_CPU_TO_LE32(DMA_HI(phys));
cmd->comp_val = OSAL_CPU_TO_LE32(DMAE_COMPLETION_VAL);
/* Check if the grc_addr is valid like < MAX_GRC_OFFSET */
cnt_split = size_in_dwords / length_limit;

16
drivers/net/qede/base/ecore_hw.h
View File

@ -259,6 +259,10 @@ enum _ecore_status_t ecore_dmae_info_alloc(struct ecore_hwfn *p_hwfn);
void ecore_dmae_info_free(struct ecore_hwfn *p_hwfn);
union ecore_qm_pq_params {
struct {
u8 q_idx;
} iscsi;
struct {
u8 tc;
} core;
@ -268,10 +272,20 @@ union ecore_qm_pq_params {
u8 vf_id;
u8 tc;
} eth;
struct {
u8 dcqcn;
u8 qpid; /* roce relative */
} roce;
struct {
u8 qidx;
} iwarp;
};
u16 ecore_get_qm_pq(struct ecore_hwfn *p_hwfn,
enum protocol_type proto, union ecore_qm_pq_params *params);
enum protocol_type proto,
union ecore_qm_pq_params *params);
enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
const u8 *fw_data);

324
drivers/net/qede/base/ecore_init_fw_funcs.c
View File

@ -13,11 +13,11 @@
#include "ecore_rt_defs.h"
#include "ecore_hsi_common.h"
#include "ecore_hsi_init_func.h"
#include "ecore_hsi_eth.h"
#include "ecore_hsi_init_tool.h"
#include "ecore_iro.h"
#include "ecore_init_fw_funcs.h"
/* @DPDK CmInterfaceEnum */
enum cm_interface_enum {
enum CmInterfaceEnum {
MCM_SEC,
MCM_PRI,
UCM_SEC,
@ -51,17 +51,23 @@ enum cm_interface_enum {
#define QM_RL_UPPER_BOUND 62500000
#define QM_RL_PERIOD 5
#define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
#define QM_RL_INC_VAL(rate) \
OSAL_MAX_T(u32, (((rate ? rate : 1000000) * QM_RL_PERIOD * 1.01) / 8), 1)
#define QM_RL_MAX_INC_VAL 43750000
/* RL increment value - the factor of 1.01 was added after seeing only
* 99% factor reached in a 25Gbps port with DPDK RFC 2544 test.
* In this scenario the PF RL was reducing the line rate to 99% although
* the credit increment value was the correct one and FW calculated
* correct packet sizes. The reason for the inaccuracy of the RL is
* unknown at this point.
*/
/* rate in mbps */
#define QM_RL_INC_VAL(rate) OSAL_MAX_T(u32, (u32)(((rate ? rate : 1000000) * \
QM_RL_PERIOD * 101) / (8 * 100)), 1)
/* AFullOprtnstcCrdMask constants */
#define QM_OPPOR_LINE_VOQ_DEF 1
#define QM_OPPOR_FW_STOP_DEF 0
#define QM_OPPOR_PQ_EMPTY_DEF 1
#define EAGLE_WORKAROUND_TC 7
/* Command Queue constants */
#define PBF_CMDQ_PURE_LB_LINES 150
#define PBF_CMDQ_EAGLE_WORKAROUND_LINES 8 /* eagle workaround CmdQ */
#define PBF_CMDQ_LINES_RT_OFFSET(voq) \
(PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \
voq * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET \
@ -73,8 +79,8 @@ voq * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET \
((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
/* BTB: blocks constants (block size = 256B) */
#define BTB_JUMBO_PKT_BLOCKS 38 /* 256B blocks in 9700B packet */
#define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS /* headroom per-port */
#define BTB_EAGLE_WORKAROUND_BLOCKS 4 /* eagle workaround blocks */
/* headroom per-port */
#define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
#define BTB_PURE_LB_FACTOR 10
#define BTB_PURE_LB_RATIO 7 /* factored (hence really 0.7) */
/* QM stop command constants */
@ -170,6 +176,9 @@ static void ecore_cmdq_lines_voq_rt_init(struct ecore_hwfn *p_hwfn,
u8 voq, u16 cmdq_lines)
{
u32 qm_line_crd;
/* In A0 - Limit the size of pbf queue so that only 511 commands
* with the minimum size of 4 (FCoE minimum size)
*/
bool is_bb_a0 = ECORE_IS_BB_A0(p_hwfn->p_dev);
if (is_bb_a0)
cmdq_lines = OSAL_MIN_T(u32, cmdq_lines, 1022);
@ -189,18 +198,16 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
port_params[MAX_NUM_PORTS])
{
u8 tc, voq, port_id, num_tcs_in_port;
bool eagle_workaround = ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn);
/* clear PBF lines for all VOQs */
for (voq = 0; voq < MAX_NUM_VOQS; voq++)
STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0);
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
if (port_params[port_id].active) {
u16 phys_lines, phys_lines_per_tc;
/* find #lines to divide between active physical TCs */
phys_lines =
port_params[port_id].num_pbf_cmd_lines -
PBF_CMDQ_PURE_LB_LINES;
if (eagle_workaround)
phys_lines -= PBF_CMDQ_EAGLE_WORKAROUND_LINES;
/* find #lines per active physical TC */
num_tcs_in_port = 0;
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
@ -222,14 +229,6 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
/* init registers for pure LB TC */
ecore_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id),
PBF_CMDQ_PURE_LB_LINES);
/* init registers for eagle workaround */
if (eagle_workaround) {
voq =
PHYS_VOQ(port_id, EAGLE_WORKAROUND_TC,
max_phys_tcs_per_port);
ecore_cmdq_lines_voq_rt_init(p_hwfn, voq,
PBF_CMDQ_EAGLE_WORKAROUND_LINES);
}
}
}
}
@ -262,15 +261,13 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
{
u8 tc, voq, port_id, num_tcs_in_port;
u32 usable_blocks, pure_lb_blocks, phys_blocks;
bool eagle_workaround = ENABLE_EAGLE_ENG1_WORKAROUND(p_hwfn);
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
if (port_params[port_id].active) {
/* subtract headroom blocks */
usable_blocks =
port_params[port_id].num_btb_blocks -
BTB_HEADROOM_BLOCKS;
if (eagle_workaround)
usable_blocks -= BTB_EAGLE_WORKAROUND_BLOCKS;
/* find blocks per physical TC. use factor to avoid floating arithmethic */
num_tcs_in_port = 0;
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
@ -303,18 +300,8 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
}
/* init pure LB TC */
STORE_RT_REG(p_hwfn,
PBF_BTB_GUARANTEED_RT_OFFSET(LB_VOQ
(port_id)),
pure_lb_blocks);
/* init eagle workaround */
if (eagle_workaround) {
voq =
PHYS_VOQ(port_id, EAGLE_WORKAROUND_TC,
max_phys_tcs_per_port);
STORE_RT_REG(p_hwfn,
PBF_BTB_GUARANTEED_RT_OFFSET(voq),
BTB_EAGLE_WORKAROUND_BLOCKS);
}
PBF_BTB_GUARANTEED_RT_OFFSET(
LB_VOQ(port_id)), pure_lb_blocks);
}
}
}
@ -363,6 +350,10 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
u8 voq =
VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
bool is_vf_pq = (i >= num_pf_pqs);
/* added to avoid compilation warning */
u32 max_qm_global_rls = MAX_QM_GLOBAL_RLS;
bool rl_valid = pq_params[i].rl_valid &&
pq_params[i].vport_id < max_qm_global_rls;
/* update first Tx PQ of VPORT/TC */
u8 vport_id_in_pf = pq_params[i].vport_id - start_vport;
u16 first_tx_pq_id =
@ -379,14 +370,19 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
(voq << QM_WFQ_VP_PQ_VOQ_SHIFT) | (pf_id <<
QM_WFQ_VP_PQ_PF_SHIFT));
}
/* check RL ID */
if (pq_params[i].rl_valid && pq_params[i].vport_id >=
max_qm_global_rls)
DP_NOTICE(p_hwfn, true,
"Invalid VPORT ID for rate limiter config");
/* fill PQ map entry */
OSAL_MEMSET(&tx_pq_map, 0, sizeof(tx_pq_map));
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_VALID,
is_vf_pq ? 1 : 0);
rl_valid ? 1 : 0);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID,
is_vf_pq ? pq_params[i].vport_id : 0);
rl_valid ? pq_params[i].vport_id : 0);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP,
pq_params[i].wrr_group);
@ -398,6 +394,9 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
mem_addr_4kb);
/* check if VF PQ */
if (is_vf_pq) {
/* if PQ is associated with a VF, add indication to PQ
* VF mask
*/
tx_pq_vf_mask[pq_id / tx_pq_vf_mask_width] |=
(1 << (pq_id % tx_pq_vf_mask_width));
mem_addr_4kb += vport_pq_mem_4kb;
@ -409,6 +408,9 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
for (i = 0; i < num_tx_pq_vf_masks; i++) {
if (tx_pq_vf_mask[i]) {
if (is_bb_a0) {
/* A0-only: perform read-modify-write
*(fixed in B0)
*/
u32 curr_mask =
is_first_pf ? 0 : ecore_rd(p_hwfn, p_ptt,
QM_REG_MAXPQSIZETXSEL_0
@ -432,6 +434,8 @@ static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
u32 num_tids, u32 base_mem_addr_4kb)
{
u16 i, pq_id;
/* a single other PQ grp is used in each PF, where PQ group i is used in PF i */
u16 pq_group = pf_id;
u32 pq_size = num_pf_cids + num_tids;
u32 pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
@ -450,7 +454,7 @@ static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
mem_addr_4kb += pq_mem_4kb;
}
}
/* Prepare PF WFQ runtime init values for specified PF. Return -1 on error. */
static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn,
u8 port_id,
u8 pf_id,
@ -474,15 +478,14 @@ static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn,
u8 voq =
VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
OVERWRITE_RT_REG(p_hwfn, crd_reg_offset + voq * MAX_NUM_PFS_BB,
QM_WFQ_CRD_REG_SIGN_BIT);
(u32)QM_WFQ_CRD_REG_SIGN_BIT);
}
STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id,
QM_WFQ_UPPER_BOUND | QM_WFQ_CRD_REG_SIGN_BIT);
QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val);
return 0;
}
/* Prepare PF RL runtime init values for the specified PF. Return -1 on err */
/* Prepare PF RL runtime init values for specified PF. Return -1 on error. */
static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
{
u32 inc_val = QM_RL_INC_VAL(pf_rl);
@ -491,13 +494,15 @@ static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
return -1;
}
STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id,
QM_RL_CRD_REG_SIGN_BIT);
(u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id,
QM_RL_UPPER_BOUND | QM_RL_CRD_REG_SIGN_BIT);
QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
return 0;
}
/* Prepare VPORT WFQ runtime init values for the specified VPORTs. Return -1 on
* error.
*/
static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,
u8 num_vports,
struct init_qm_vport_params *vport_params)
@ -513,6 +518,9 @@ static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,
"Invalid VPORT WFQ weight config");
return -1;
}
/* each VPORT can have several VPORT PQ IDs for
* different TCs
*/
for (tc = 0; tc < NUM_OF_TCS; tc++) {
u16 vport_pq_id =
vport_params[i].first_tx_pq_id[tc];
@ -520,7 +528,7 @@ static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,
STORE_RT_REG(p_hwfn,
QM_REG_WFQVPCRD_RT_OFFSET +
vport_pq_id,
QM_WFQ_CRD_REG_SIGN_BIT);
(u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn,
QM_REG_WFQVPWEIGHT_RT_OFFSET
+ vport_pq_id, inc_val);
@ -531,13 +539,20 @@ static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,
return 0;
}
/* Prepare VPORT RL runtime init values for specified VPORT. Ret -1 on error. */
/* Prepare VPORT RL runtime init values for the specified VPORTs.
* Return -1 on error.
*/
static int ecore_vport_rl_rt_init(struct ecore_hwfn *p_hwfn,
u8 start_vport,
u8 num_vports,
struct init_qm_vport_params *vport_params)
{
u8 i, vport_id;
if (start_vport + num_vports >= MAX_QM_GLOBAL_RLS) {
DP_NOTICE(p_hwfn, true,
"Invalid VPORT ID for rate limiter configuration");
return -1;
}
/* go over all PF VPORTs */
for (i = 0, vport_id = start_vport; i < num_vports; i++, vport_id++) {
u32 inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl);
@ -547,10 +562,10 @@ static int ecore_vport_rl_rt_init(struct ecore_hwfn *p_hwfn,
return -1;
}
STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + vport_id,
QM_RL_CRD_REG_SIGN_BIT);
(u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn,
QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + vport_id,
QM_RL_UPPER_BOUND | QM_RL_CRD_REG_SIGN_BIT);
QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id,
inc_val);
}
@ -568,7 +583,7 @@ static bool ecore_poll_on_qm_cmd_ready(struct ecore_hwfn *p_hwfn,
}
/* check if timeout while waiting for SDM command ready */
if (i == QM_STOP_CMD_MAX_POLL_COUNT) {
DP_VERBOSE(p_hwfn, ECORE_MSG_HW,
DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG,
"Timeout waiting for QM SDM cmd ready signal\n");
return false;
}
@ -610,7 +625,6 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
struct init_qm_port_params
port_params[MAX_NUM_PORTS])
{
u8 port_id;
/* init AFullOprtnstcCrdMask */
u32 mask =
(QM_OPPOR_LINE_VOQ_DEF << QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT) |
@ -717,7 +731,7 @@ int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,
return -1;
}
ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFCRD + pf_id * 4,
QM_RL_CRD_REG_SIGN_BIT);
(u32)QM_RL_CRD_REG_SIGN_BIT);
ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val);
return 0;
}
@ -746,14 +760,20 @@ int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u8 vport_id, u32 vport_rl)
{
u32 inc_val = QM_RL_INC_VAL(vport_rl);
u32 inc_val, max_qm_global_rls = MAX_QM_GLOBAL_RLS;
if (vport_id >= max_qm_global_rls) {
DP_NOTICE(p_hwfn, true,
"Invalid VPORT ID for rate limiter configuration");
return -1;
}
inc_val = QM_RL_INC_VAL(vport_rl);
if (inc_val > QM_RL_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, true,
"Invalid VPORT rate-limit configuration");
return -1;
}
ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLCRD + vport_id * 4,
QM_RL_CRD_REG_SIGN_BIT);
(u32)QM_RL_CRD_REG_SIGN_BIT);
ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + vport_id * 4, inc_val);
return 0;
}
@ -1132,22 +1152,22 @@ void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn,
/*In MF should be called once per engine to set EtherType of OuterTag*/
void ecore_set_engine_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u32 eth_type)
struct ecore_ptt *p_ptt, u32 ethType)
{
/* update PRS register */
STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, eth_type);
STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType);
/* update NIG register */
STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, eth_type);
STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType);
/* update PBF register */
STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, eth_type);
STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType);
}
/*In MF should be called once per port to set EtherType of OuterTag*/
void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u32 eth_type)
struct ecore_ptt *p_ptt, u32 ethType)
{
/* update DORQ register */
STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, eth_type);
STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, ethType);
}
#define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \
@ -1159,7 +1179,7 @@ void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn,
/* update PRS register */
ecore_wr(p_hwfn, p_ptt, PRS_REG_VXLAN_PORT, dest_port);
/* update NIG register */
ecore_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_PORT, dest_port);
ecore_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_CTRL, dest_port);
/* update PBF register */
ecore_wr(p_hwfn, p_ptt, PBF_REG_VXLAN_PORT, dest_port);
}
@ -1176,7 +1196,7 @@ void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn,
ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val) {
ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
PRS_ETH_TUNN_FIC_FORMAT);
(u32)PRS_ETH_TUNN_FIC_FORMAT);
}
/* update NIG register */
reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
@ -1205,7 +1225,7 @@ void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn,
ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val) {
ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
PRS_ETH_TUNN_FIC_FORMAT);
(u32)PRS_ETH_TUNN_FIC_FORMAT);
}
/* update NIG register */
reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
@ -1256,7 +1276,7 @@ void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
if (reg_val) {
ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0,
PRS_ETH_TUNN_FIC_FORMAT);
(u32)PRS_ETH_TUNN_FIC_FORMAT);
}
/* update NIG register */
ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE,
@ -1277,3 +1297,179 @@ void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN,
ip_geneve_enable ? 1 : 0);
}
#define T_ETH_PACKET_ACTION_GFT_EVENTID 23
#define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272
#define T_ETH_PACKET_MATCH_RFS_EVENTID 25
#define PARSER_ETH_CONN_CM_HDR (0x0)
#define CAM_LINE_SIZE sizeof(u32)
#define RAM_LINE_SIZE sizeof(u64)
#define REG_SIZE sizeof(u32)
void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
/* set RFS event ID to be awakened i Tstorm By Prs */
u32 rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
rfs_cm_hdr_event_id |= T_ETH_PACKET_ACTION_GFT_EVENTID <<
PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
rfs_cm_hdr_event_id |= PARSER_ETH_CONN_GFT_ACTION_CM_HDR <<
PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
}
void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 pf_id,
bool tcp,
bool udp,
bool ipv4,
bool ipv6)
{
u32 rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
union gft_cam_line_union camLine;
struct gft_ram_line ramLine;
u32 *ramLinePointer = (u32 *)&ramLine;
int i;
if (!ipv6 && !ipv4)
DP_NOTICE(p_hwfn, true,
"set_rfs_mode_enable: must accept at "
"least on of - ipv4 or ipv6");
if (!tcp && !udp)
DP_NOTICE(p_hwfn, true,
"set_rfs_mode_enable: must accept at "
"least on of - udp or tcp");
/* set RFS event ID to be awakened i Tstorm By Prs */
rfs_cm_hdr_event_id |= T_ETH_PACKET_MATCH_RFS_EVENTID <<
PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
rfs_cm_hdr_event_id |= PARSER_ETH_CONN_CM_HDR <<
PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
/* Configure Registers for RFS mode */
/* enable gft search */
ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
ecore_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0); /* do not load
* context only cid
* in PRS on match
*/
camLine.cam_line_mapped.camline = 0;
/* cam line is now valid!! */
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_VALID, 1);
/* filters are per PF!! */
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_PF_ID_MASK, 1);
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
if (!(tcp && udp)) {
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK, 1);
if (tcp)
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
GFT_PROFILE_TCP_PROTOCOL);
else
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
GFT_PROFILE_UDP_PROTOCOL);
}
if (!(ipv4 && ipv6)) {
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
if (ipv4)
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_IP_VERSION,
GFT_PROFILE_IPV4);
else
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_IP_VERSION,
GFT_PROFILE_IPV6);
}
/* write characteristics to cam */
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
camLine.cam_line_mapped.camline);
camLine.cam_line_mapped.camline =
ecore_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
/* write line to RAM - compare to filter 4 tuple */
ramLine.low32bits = 0;
ramLine.high32bits = 0;
SET_FIELD(ramLine.high32bits, GFT_RAM_LINE_DST_IP, 1);
SET_FIELD(ramLine.high32bits, GFT_RAM_LINE_SRC_IP, 1);
SET_FIELD(ramLine.low32bits, GFT_RAM_LINE_SRC_PORT, 1);
SET_FIELD(ramLine.low32bits, GFT_RAM_LINE_DST_PORT, 1);
/* each iteration write to reg */
for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM +
RAM_LINE_SIZE * pf_id +
i * REG_SIZE, *(ramLinePointer + i));
/* set default profile so that no filter match will happen */
ramLine.low32bits = 0xffff;
ramLine.high32bits = 0xffff;
for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM +
RAM_LINE_SIZE * PRS_GFT_CAM_LINES_NO_MATCH +
i * REG_SIZE, *(ramLinePointer + i));
}
/* Configure VF zone size mode*/
void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u16 mode,
bool runtime_init)
{
u32 msdm_vf_size_log = MSTORM_VF_ZONE_DEFAULT_SIZE_LOG;
u32 msdm_vf_offset_mask;
if (mode == VF_ZONE_SIZE_MODE_DOUBLE)
msdm_vf_size_log += 1;
else if (mode == VF_ZONE_SIZE_MODE_QUAD)
msdm_vf_size_log += 2;
msdm_vf_offset_mask = (1 << msdm_vf_size_log) - 1;
if (runtime_init) {
STORE_RT_REG(p_hwfn,
PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET,
msdm_vf_size_log);
STORE_RT_REG(p_hwfn,
PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET,
msdm_vf_offset_mask);
} else {
ecore_wr(p_hwfn, p_ptt,
PGLUE_B_REG_MSDM_VF_SHIFT_B, msdm_vf_size_log);
ecore_wr(p_hwfn, p_ptt,
PGLUE_B_REG_MSDM_OFFSET_MASK_B, msdm_vf_offset_mask);
}
}
/* get mstorm statistics for offset by VF zone size mode*/
u32 ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn *p_hwfn,
u16 stat_cnt_id,
u16 vf_zone_size_mode)
{
u32 offset = MSTORM_QUEUE_STAT_OFFSET(stat_cnt_id);
if ((vf_zone_size_mode != VF_ZONE_SIZE_MODE_DEFAULT) &&
(stat_cnt_id > MAX_NUM_PFS)) {
if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_DOUBLE)
offset += (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
(stat_cnt_id - MAX_NUM_PFS);
else if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_QUAD)
offset += 3 * (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
(stat_cnt_id - MAX_NUM_PFS);
}
return offset;
}
/* get mstorm VF producer offset by VF zone size mode*/
u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn,
u8 vf_id,
u8 vf_queue_id,
u16 vf_zone_size_mode)
{
u32 offset = MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id);
if (vf_zone_size_mode != VF_ZONE_SIZE_MODE_DEFAULT) {
if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_DOUBLE)
offset += (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
vf_id;
else if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_QUAD)
offset += 3 * (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) *
vf_id;
}
return offset;
}

102
drivers/net/qede/base/ecore_init_fw_funcs.h
View File

@ -28,10 +28,12 @@ struct init_qm_pq_params;
u32 ecore_qm_pf_mem_size(u8 pf_id,
u32 num_pf_cids,
u32 num_vf_cids,
u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
u32 num_tids,
u16 num_pf_pqs,
u16 num_vf_pqs);
/**
* @brief ecore_qm_common_rt_init -
* Prepare QM runtime init values for the engine phase
* @brief ecore_qm_common_rt_init - Prepare QM runtime init values for engine
* phase
*
* @param p_hwfn
* @param max_ports_per_engine - max number of ports per engine in HW
@ -51,9 +53,35 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
bool pf_wfq_en,
bool vport_rl_en,
bool vport_wfq_en,
struct init_qm_port_params
port_params[MAX_NUM_PORTS]);
struct init_qm_port_params port_params[MAX_NUM_PORTS]);
/**
* @brief ecore_qm_pf_rt_init Prepare QM runtime init values for the PF phase
*
* @param p_hwfn
* @param p_ptt - ptt window used for writing the registers
* @param port_id - port ID
* @param pf_id - PF ID
* @param max_phys_tcs_per_port - max number of physical TCs per port in HW
* @param is_first_pf - 1 = first PF in engine, 0 = othwerwise
* @param num_pf_cids - number of connections used by this PF
* @param num_vf_cids - number of connections used by VFs of this PF
* @param num_tids - number of tasks used by this PF
* @param start_pq - first Tx PQ ID associated with this PF
* @param num_pf_pqs - number of Tx PQs associated with this PF (non-VF)
* @param num_vf_pqs - number of Tx PQs associated with a VF
* @param start_vport - first VPORT ID associated with this PF
* @param num_vports - number of VPORTs associated with this PF
* @param pf_wfq - WFQ weight. if PF WFQ is globally disabled, the weight must
* be 0. otherwise, the weight must be non-zero.
* @param pf_rl - rate limit in Mb/sec units. a value of 0 means don't
* configure. ignored if PF RL is globally disabled.
* @param pq_params - array of size (num_pf_pqs+num_vf_pqs) with parameters for
* each Tx PQ associated with the specified PF.
* @param vport_params - array of size num_vports with parameters for each
* associated VPORT.
*
* @return 0 on success, -1 on error.
*/
int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u8 port_id,
@ -287,5 +315,65 @@ void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn,
*/
void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
bool eth_geneve_enable, bool ip_geneve_enable);
bool eth_geneve_enable,
bool ip_geneve_enable);
#ifndef UNUSED_HSI_FUNC
/**
* @brief ecore_set_gft_event_id_cm_hdr - configure GFT event id and cm header
*
* @param p_ptt - ptt window used for writing the registers.
*/
void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
/**
* @brief ecore_set_rfs_mode_enable - enable and configure HW for RFS
*
*
* @param p_ptt - ptt window used for writing the registers.
* @param pf_id - pf on which to enable RFS.
* @param tcp - set profile tcp packets.
* @param udp - set profile udp packet.
* @param ipv4 - set profile ipv4 packet.
* @param ipv6 - set profile ipv6 packet.
*/
void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 pf_id,
bool tcp,
bool udp,
bool ipv4,
bool ipv6);
#endif /* UNUSED_HSI_FUNC */
/**
* @brief ecore_config_vf_zone_size_mode - Configure VF zone size mode. Must be
* used before first ETH queue started.
*
*
* @param p_ptt - ptt window used for writing the registers. Don't care
* if runtime_init used
* @param mode - VF zone size mode. Use enum vf_zone_size_mode.
* @param runtime_init - Set 1 to init runtime registers in engine phase. Set 0
* if VF zone size mode configured after engine phase.
*/
void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn, struct ecore_ptt
*p_ptt, u16 mode, bool runtime_init);
/**
* @brief ecore_get_mstorm_queue_stat_offset - get mstorm statistics offset by VF
* zone size mode.
*
* @param stat_cnt_id - statistic counter id
* @param vf_zone_size_mode - VF zone size mode. Use enum vf_zone_size_mode.
*/
u32 ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn *p_hwfn,
u16 stat_cnt_id, u16 vf_zone_size_mode);
/**
* @brief ecore_get_mstorm_eth_vf_prods_offset - VF producer offset by VF zone
* size mode.
*
* @param vf_id - vf id.
* @param vf_queue_id - per VF rx queue id.
* @param vf_zone_size_mode - vf zone size mode. Use enum vf_zone_size_mode.
*/
u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn, u8 vf_id, u8
vf_queue_id, u16 vf_zone_size_mode);
#endif

5
drivers/net/qede/base/ecore_init_ops.c
View File

@ -525,7 +525,7 @@ void ecore_gtt_init(struct ecore_hwfn *p_hwfn)
* not too bright, but it should work on the simple FPGA/EMUL
* scenarios.
*/
bool initialized = false; /* @DPDK */
static bool initialized;
int poll_cnt = 500;
u32 val;
@ -573,7 +573,8 @@ enum _ecore_status_t ecore_init_fw_data(struct ecore_dev *p_dev,
return ECORE_INVAL;
}
buf_hdr = (struct bin_buffer_hdr *)(uintptr_t)data;
/* First Dword contains metadata and should be skipped */
buf_hdr = (struct bin_buffer_hdr *)((uintptr_t)(data + sizeof(u32)));
offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset;
fw->fw_ver_info = (struct fw_ver_info *)((uintptr_t)(data + offset));

271
drivers/net/qede/base/ecore_int.c
View File

@ -21,7 +21,6 @@
#include "ecore_hw_defs.h"
#include "ecore_hsi_common.h"
#include "ecore_mcp.h"
#include "ecore_attn_values.h"
struct ecore_pi_info {
ecore_int_comp_cb_t comp_cb;
@ -61,8 +60,6 @@ struct aeu_invert_reg_bit {
#define ATTENTION_OFFSET_SHIFT (12)
#define ATTENTION_CLEAR_ENABLE (1 << 28)
#define ATTENTION_FW_DUMP (1 << 29)
#define ATTENTION_PANIC_DUMP (1 << 30)
unsigned int flags;
/* Callback to call if attention will be triggered */
@ -726,46 +723,12 @@ static enum _ecore_status_t ecore_int_assertion(struct ecore_hwfn *p_hwfn,
return ECORE_SUCCESS;
}
static void ecore_int_deassertion_print_bit(struct ecore_hwfn *p_hwfn,
struct attn_hw_reg *p_reg_desc,
struct attn_hw_block *p_block,
enum ecore_attention_type type,
u32 val, u32 mask)
static void ecore_int_attn_print(struct ecore_hwfn *p_hwfn,
enum block_id id, enum dbg_attn_type type,
bool b_clear)
{
int j;
#ifdef ATTN_DESC
const char **description;
if (type == ECORE_ATTN_TYPE_ATTN)
description = p_block->int_desc;
else
description = p_block->prty_desc;
#endif
for (j = 0; j < p_reg_desc->num_of_bits; j++) {
if (val & (1 << j)) {
#ifdef ATTN_DESC
DP_NOTICE(p_hwfn, false,
"%s (%s): %s [reg %d [0x%08x], bit %d]%s\n",
p_block->name,
type == ECORE_ATTN_TYPE_ATTN ? "Interrupt" :
"Parity",
description[p_reg_desc->bit_attn_idx[j]],
p_reg_desc->reg_idx,
p_reg_desc->sts_addr, j,
(mask & (1 << j)) ? " [MASKED]" : "");
#else
DP_NOTICE(p_hwfn->p_dev, false,
"%s (%s): [reg %d [0x%08x], bit %d]%s\n",
p_block->name,
type == ECORE_ATTN_TYPE_ATTN ? "Interrupt" :
"Parity",
p_reg_desc->reg_idx,
p_reg_desc->sts_addr, j,
(mask & (1 << j)) ? " [MASKED]" : "");
#endif
}
}
/* @DPDK */
DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n", id, type);
}
/**
@ -788,13 +751,7 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
u32 bitmask)
{
enum _ecore_status_t rc = ECORE_INVAL;
u32 val, mask;
#ifndef REMOVE_DBG
u32 interrupts[20]; /* TODO- change into HSI define once supplied */
OSAL_MEMSET(interrupts, 0, sizeof(u32) * 20); /* FIXME real size) */
#endif
bool b_fatal = false;
DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
p_bit_name, bitmask);
@ -806,13 +763,17 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
rc = p_aeu->cb(p_hwfn);
}
if (rc != ECORE_SUCCESS)
b_fatal = true;
/* Print HW block interrupt registers */
if (p_aeu->block_index != MAX_BLOCK_ID)
DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
p_aeu->block_index, ATTN_TYPE_INTERRUPT);
if (p_aeu->block_index != MAX_BLOCK_ID) {
ecore_int_attn_print(p_hwfn, p_aeu->block_index,
ATTN_TYPE_INTERRUPT, !b_fatal);
}
/* Reach assertion if attention is fatal */
if (rc != ECORE_SUCCESS) {
if (b_fatal) {
DP_NOTICE(p_hwfn, true, "`%s': Fatal attention\n",
p_bit_name);
@ -820,7 +781,8 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
}
/* Prevent this Attention from being asserted in the future */
if (p_aeu->flags & ATTENTION_CLEAR_ENABLE) {
if (p_aeu->flags & ATTENTION_CLEAR_ENABLE ||
p_hwfn->p_dev->attn_clr_en) {
u32 val;
u32 mask = ~bitmask;
val = ecore_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
@ -829,13 +791,6 @@ ecore_int_deassertion_aeu_bit(struct ecore_hwfn *p_hwfn,
p_bit_name);
}
if (p_aeu->flags & (ATTENTION_FW_DUMP | ATTENTION_PANIC_DUMP)) {
/* @@@TODO - what to dump? <yuvalmin 04/02/13> */
DP_ERR(p_hwfn->p_dev, "`%s' - Dumps aren't implemented yet\n",
p_aeu->bit_name);
return ECORE_NOTIMPL;
}
return rc;
}
@ -856,15 +811,18 @@ static void ecore_int_deassertion_parity(struct ecore_hwfn *p_hwfn,
DP_INFO(p_hwfn->p_dev, "%s[%d] parity attention is set\n",
p_aeu->bit_name, bit_index);
if (block_id != MAX_BLOCK_ID)
if (block_id == MAX_BLOCK_ID)
return;
ecore_int_attn_print(p_hwfn, block_id,
ATTN_TYPE_PARITY, false);
/* In A0, there's a single parity bit for several blocks */
if (block_id == BLOCK_BTB) {
DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
BLOCK_OPTE, ATTN_TYPE_PARITY);
DP_NOTICE(p_hwfn->p_dev, false, "[block_id %d type %d]\n",
BLOCK_MCP, ATTN_TYPE_PARITY);
ecore_int_attn_print(p_hwfn, BLOCK_OPTE,
ATTN_TYPE_PARITY, false);
ecore_int_attn_print(p_hwfn, BLOCK_MCP,
ATTN_TYPE_PARITY, false);
}
}
@ -1094,13 +1052,11 @@ void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie)
struct ecore_pi_info *pi_info = OSAL_NULL;
struct ecore_sb_attn_info *sb_attn;
struct ecore_sb_info *sb_info;
static int arr_size;
int arr_size;
u16 rc = 0;
if (!p_hwfn) {
DP_ERR(p_hwfn->p_dev, "DPC called - no hwfn!\n");
if (!p_hwfn)
return;
}
if (!p_hwfn->p_sp_sb) {
DP_ERR(p_hwfn->p_dev, "DPC called - no p_sp_sb\n");
@ -1275,7 +1231,7 @@ static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
void *p_virt;
/* SB struct */
p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(struct ecore_sb_attn_info));
p_sb = OSAL_ALLOC(p_dev, GFP_KERNEL, sizeof(*p_sb));
if (!p_sb) {
DP_NOTICE(p_dev, true,
"Failed to allocate `struct ecore_sb_attn_info'");
@ -1300,17 +1256,8 @@ static enum _ecore_status_t ecore_int_sb_attn_alloc(struct ecore_hwfn *p_hwfn,
}
/* coalescing timeout = timeset << (timer_res + 1) */
#ifdef RTE_LIBRTE_QEDE_RX_COAL_US
#define ECORE_CAU_DEF_RX_USECS RTE_LIBRTE_QEDE_RX_COAL_US
#else
#define ECORE_CAU_DEF_RX_USECS 24
#endif
#ifdef RTE_LIBRTE_QEDE_TX_COAL_US
#define ECORE_CAU_DEF_TX_USECS RTE_LIBRTE_QEDE_TX_COAL_US
#else
#define ECORE_CAU_DEF_TX_USECS 48
#endif
void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
struct cau_sb_entry *p_sb_entry,
@ -1318,6 +1265,7 @@ void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
{
struct ecore_dev *p_dev = p_hwfn->p_dev;
u32 cau_state;
u8 timer_res;
OSAL_MEMSET(p_sb_entry, 0, sizeof(*p_sb_entry));
@ -1327,28 +1275,33 @@ void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
/* setting the time resultion to a fixed value ( = 1) */
SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0,
ECORE_CAU_DEF_RX_TIMER_RES);
SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1,
ECORE_CAU_DEF_TX_TIMER_RES);
cau_state = CAU_HC_DISABLE_STATE;
if (p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
cau_state = CAU_HC_ENABLE_STATE;
if (!p_dev->rx_coalesce_usecs) {
if (!p_dev->rx_coalesce_usecs)
p_dev->rx_coalesce_usecs = ECORE_CAU_DEF_RX_USECS;
DP_INFO(p_dev, "Coalesce params rx-usecs=%u\n",
p_dev->rx_coalesce_usecs);
}
if (!p_dev->tx_coalesce_usecs) {
if (!p_dev->tx_coalesce_usecs)
p_dev->tx_coalesce_usecs = ECORE_CAU_DEF_TX_USECS;
DP_INFO(p_dev, "Coalesce params tx-usecs=%u\n",
p_dev->tx_coalesce_usecs);
}
}
/* Coalesce = (timeset << timer-res), timeset is 7bit wide */
if (p_dev->rx_coalesce_usecs <= 0x7F)
timer_res = 0;
else if (p_dev->rx_coalesce_usecs <= 0xFF)
timer_res = 1;
else
timer_res = 2;
SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
if (p_dev->tx_coalesce_usecs <= 0x7F)
timer_res = 0;
else if (p_dev->tx_coalesce_usecs <= 0xFF)
timer_res = 1;
else
timer_res = 2;
SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state);
SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state);
}
@ -1388,17 +1341,32 @@ void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
/* Configure pi coalescing if set */
if (p_hwfn->p_dev->int_coalescing_mode == ECORE_COAL_MODE_ENABLE) {
u8 num_tc = 1; /* @@@TBD aelior ECORE_MULTI_COS */
u8 timeset = p_hwfn->p_dev->rx_coalesce_usecs >>
(ECORE_CAU_DEF_RX_TIMER_RES + 1);
/* eth will open queues for all tcs, so configure all of them
* properly, rather than just the active ones
*/
u8 num_tc = p_hwfn->hw_info.num_hw_tc;
u8 timeset, timer_res;
u8 i;
/* timeset = (coalesce >> timer-res), timeset is 7bit wide */
if (p_hwfn->p_dev->rx_coalesce_usecs <= 0x7F)
timer_res = 0;
else if (p_hwfn->p_dev->rx_coalesce_usecs <= 0xFF)
timer_res = 1;
else
timer_res = 2;
timeset = (u8)(p_hwfn->p_dev->rx_coalesce_usecs >> timer_res);
ecore_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
ECORE_COAL_RX_STATE_MACHINE, timeset);
timeset = p_hwfn->p_dev->tx_coalesce_usecs >>
(ECORE_CAU_DEF_TX_TIMER_RES + 1);
if (p_hwfn->p_dev->tx_coalesce_usecs <= 0x7F)
timer_res = 0;
else if (p_hwfn->p_dev->tx_coalesce_usecs <= 0xFF)
timer_res = 1;
else
timer_res = 2;
timeset = (u8)(p_hwfn->p_dev->tx_coalesce_usecs >> timer_res);
for (i = 0; i < num_tc; i++) {
ecore_int_cau_conf_pi(p_hwfn, p_ptt,
igu_sb_id, TX_PI(i),
@ -1572,10 +1540,10 @@ static enum _ecore_status_t ecore_int_sp_sb_alloc(struct ecore_hwfn *p_hwfn,
/* SB struct */
p_sb =
OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
sizeof(struct ecore_sb_sp_info));
sizeof(*p_sb));
if (!p_sb) {
DP_NOTICE(p_hwfn, true,
"Failed to allocate `struct ecore_sb_info'");
"Failed to allocate `struct ecore_sb_info'\n");
return ECORE_NOMEM;
}
@ -1644,14 +1612,14 @@ void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
enum ecore_int_mode int_mode)
{
u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
DP_INFO(p_hwfn, "FPGA - don't enable ATTN generation in IGU\n");
else
igu_pf_conf &= ~IGU_PF_CONF_ATTN_BIT_EN;
}
#endif
igu_pf_conf |= IGU_PF_CONF_ATTN_BIT_EN;
p_hwfn->p_dev->int_mode = int_mode;
switch (p_hwfn->p_dev->int_mode) {
@ -1706,12 +1674,6 @@ ecore_int_igu_enable(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
enum _ecore_status_t rc = ECORE_SUCCESS;
u32 tmp;
/* @@@tmp - Mask General HW attentions 0-31, Enable 32-36 */
tmp = ecore_rd(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0);
tmp |= 0xf;
ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE3_IGU_OUT_0, 0);
ecore_wr(p_hwfn, p_ptt, MISC_REG_AEU_ENABLE4_IGU_OUT_0, tmp);
/* @@@tmp - Starting with MFW 8.2.1.0 we've started hitting AVS stop
* attentions. Since we're waiting for BRCM answer regarding this
* attention, in the meanwhile we simply mask it.
@ -1752,7 +1714,7 @@ void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
}
#define IGU_CLEANUP_SLEEP_LENGTH (1000)
void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
static void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 sb_id, bool cleanup_set, u16 opaque_fid)
{
@ -1811,7 +1773,7 @@ void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 sb_id, u16 opaque, bool b_set)
{
int pi;
int pi, i;
/* Set */
if (b_set)
@ -1820,6 +1782,23 @@ void ecore_int_igu_init_pure_rt_single(struct ecore_hwfn *p_hwfn,
/* Clear */
ecore_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque);
/* Wait for the IGU SB to cleanup */
for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
u32 val;
val = ecore_rd(p_hwfn, p_ptt,
IGU_REG_WRITE_DONE_PENDING +
((sb_id / 32) * 4));
if (val & (1 << (sb_id % 32)))
OSAL_UDELAY(10);
else
break;
}
if (i == IGU_CLEANUP_SLEEP_LENGTH)
DP_NOTICE(p_hwfn, true,
"Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
sb_id);
/* Clear the CAU for the SB */
for (pi = 0; pi < 12; pi++)
ecore_wr(p_hwfn, p_ptt,
@ -1895,8 +1874,8 @@ enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
{
struct ecore_igu_info *p_igu_info;
struct ecore_igu_block *p_block;
u32 min_vf = 0, max_vf = 0, val;
u16 sb_id, last_iov_sb_id = 0;
u32 min_vf, max_vf, val;
u16 prev_sb_id = 0xFF;
p_hwfn->hw_info.p_igu_info = OSAL_ALLOC(p_hwfn->p_dev,
@ -1915,16 +1894,14 @@ enum _ecore_status_t ecore_int_igu_read_cam(struct ecore_hwfn *p_hwfn,
p_igu_info->igu_dsb_id = 0xffff;
p_igu_info->igu_base_sb_iov = 0xffff;
#ifdef CONFIG_ECORE_SRIOV
min_vf = p_hwfn->hw_info.first_vf_in_pf;
max_vf = p_hwfn->hw_info.first_vf_in_pf +
p_hwfn->p_dev->sriov_info.total_vfs;
#else
min_vf = 0;
max_vf = 0;
#endif
if (p_hwfn->p_dev->p_iov_info) {
struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
for (sb_id = 0; sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
min_vf = p_iov->first_vf_in_pf;
max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
}
for (sb_id = 0;
sb_id < ECORE_MAPPING_MEMORY_SIZE(p_hwfn->p_dev);
sb_id++) {
p_block = &p_igu_info->igu_map.igu_blocks[sb_id];
val = ecore_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id);
@ -2126,12 +2103,12 @@ u16 ecore_int_queue_id_from_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id)
} else if ((sb_id >= p_info->igu_base_sb_iov) &&
(sb_id < p_info->igu_base_sb_iov + p_info->igu_sb_cnt_iov)) {
return sb_id - p_info->igu_base_sb_iov + p_info->igu_sb_cnt;
}
} else {
DP_NOTICE(p_hwfn, true, "SB %d not in range for function\n",
sb_id);
return 0;
}
}
void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
{
@ -2140,3 +2117,45 @@ void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev)
for_each_hwfn(p_dev, i)
p_dev->hwfns[i].b_int_requested = false;
}
void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable)
{
p_dev->attn_clr_en = clr_enable;
}
enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u8 timer_res, u16 sb_id, bool tx)
{
enum _ecore_status_t rc;
struct cau_sb_entry sb_entry;
if (!p_hwfn->hw_init_done) {
DP_ERR(p_hwfn, "hardware not initialized yet\n");
return ECORE_INVAL;
}
rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
sb_id * sizeof(u64),
(u64)(osal_uintptr_t)&sb_entry, 2, 0);
if (rc != ECORE_SUCCESS) {
DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
return rc;
}
if (tx)
SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
else
SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
(u64)(osal_uintptr_t)&sb_entry,
CAU_REG_SB_VAR_MEMORY +
sb_id * sizeof(u64), 2, 0);
if (rc != ECORE_SUCCESS) {
DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
return rc;
}
return rc;
}

19
drivers/net/qede/base/ecore_int.h
View File

@ -115,22 +115,6 @@ enum _ecore_status_t ecore_int_unregister_cb(struct ecore_hwfn *p_hwfn, u8 pi);
*/
u16 ecore_int_get_sp_sb_id(struct ecore_hwfn *p_hwfn);
/**
* @brief Status block cleanup. Should be called for each status
* block that will be used -> both PF / VF
*
* @param p_hwfn
* @param p_ptt
* @param sb_id - igu status block id
* @param cleanup_set - set(1) / clear(0)
* @param opaque_fid - the function for which to perform
* cleanup, for example a PF on behalf of
* its VFs.
*/
void ecore_int_igu_cleanup_sb(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 sb_id, bool cleanup_set, u16 opaque_fid);
/**
* @brief Status block cleanup. Should be called for each status
* block that will be used -> both PF / VF
@ -223,6 +207,9 @@ void ecore_init_cau_sb_entry(struct ecore_hwfn *p_hwfn,
struct cau_sb_entry *p_sb_entry, u8 pf_id,
u16 vf_number, u8 vf_valid);
enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u8 timer_res, u16 sb_id, bool tx);
#ifndef ASIC_ONLY
#define ECORE_MAPPING_MEMORY_SIZE(dev) \
((CHIP_REV_IS_SLOW(dev) && (!(dev)->b_is_emul_full)) ? \

11
drivers/net/qede/base/ecore_int_api.h
View File

@ -274,4 +274,15 @@ void ecore_int_get_num_sbs(struct ecore_hwfn *p_hwfn,
*/
void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev);
/**
* @brief ecore_int_attn_clr_enable - sets whether the general behavior is
* preventing attentions from being reasserted, or following the
* attributes of the specific attention.
*
* @param p_dev
* @param clr_enable
*
*/
void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable);
#endif

104
drivers/net/qede/base/ecore_iov_api.h
View File

@ -9,14 +9,17 @@
#ifndef __ECORE_SRIOV_API_H__
#define __ECORE_SRIOV_API_H__
#include "common_hsi.h"
#include "ecore_status.h"
#define ECORE_ETH_VF_NUM_MAC_FILTERS 1
#define ECORE_ETH_VF_NUM_VLAN_FILTERS 2
#define ECORE_VF_ARRAY_LENGTH (3)
#define IS_VF(p_dev) ((p_dev)->b_is_vf)
#define IS_PF(p_dev) (!((p_dev)->b_is_vf))
#ifdef CONFIG_ECORE_SRIOV
#define IS_PF_SRIOV(p_hwfn) (!!((p_hwfn)->p_dev->sriov_info.total_vfs))
#define IS_PF_SRIOV(p_hwfn) (!!((p_hwfn)->p_dev->p_iov_info))
#else
#define IS_PF_SRIOV(p_hwfn) (0)
#endif
@ -39,6 +42,18 @@ enum ecore_iov_vport_update_flag {
ECORE_IOV_VP_UPDATE_MAX = 8,
};
/* PF to VF STATUS is part of vfpf-channel API
* and must be forward compatible
*/
enum ecore_iov_pf_to_vf_status {
PFVF_STATUS_WAITING = 0,
PFVF_STATUS_SUCCESS,
PFVF_STATUS_FAILURE,
PFVF_STATUS_NOT_SUPPORTED,
PFVF_STATUS_NO_RESOURCE,
PFVF_STATUS_FORCED,
};
struct ecore_mcp_link_params;
struct ecore_mcp_link_state;
struct ecore_mcp_link_capabilities;
@ -100,32 +115,58 @@ struct ecore_iov_sw_mbx {
*
* @return struct ecore_iov_sw_mbx*
*/
struct ecore_iov_sw_mbx *ecore_iov_get_vf_sw_mbx(struct ecore_hwfn *p_hwfn,
struct ecore_iov_sw_mbx*
ecore_iov_get_vf_sw_mbx(struct ecore_hwfn *p_hwfn,
u16 rel_vf_id);
#endif
/* This struct is part of ecore_dev and contains data relevant to all hwfns;
* Initialized only if SR-IOV cpabability is exposed in PCIe config space.
*/
struct ecore_hw_sriov_info {
/* standard SRIOV capability fields, mostly for debugging */
int pos; /* capability position */
int nres; /* number of resources */
u32 cap; /* SR-IOV Capabilities */
u16 ctrl; /* SR-IOV Control */
u16 total_vfs; /* total VFs associated with the PF */
u16 num_vfs; /* number of vfs that have been started */
u16 initial_vfs; /* initial VFs associated with the PF */
u16 nr_virtfn; /* number of VFs available */
u16 offset; /* first VF Routing ID offset */
u16 stride; /* following VF stride */
u16 vf_device_id; /* VF device id */
u32 pgsz; /* page size for BAR alignment */
u8 link; /* Function Dependency Link */
u32 first_vf_in_pf;
};
#ifdef CONFIG_ECORE_SRIOV
#ifndef LINUX_REMOVE
/**
* @brief mark/clear all VFs before/after an incoming PCIe sriov
* disable.
*
* @param p_hwfn
* @param p_dev
* @param to_disable
*/
void ecore_iov_set_vfs_to_disable(struct ecore_hwfn *p_hwfn, u8 to_disable);
void ecore_iov_set_vfs_to_disable(struct ecore_dev *p_dev,
u8 to_disable);
/**
* @brief mark/clear chosen VFs before/after an incoming PCIe
* @brief mark/clear chosen VF before/after an incoming PCIe
* sriov disable.
*
* @param p_hwfn
* @param p_dev
* @param rel_vf_id
* @param to_disable
*/
void ecore_iov_set_vf_to_disable(struct ecore_hwfn *p_hwfn,
u16 rel_vf_id, u8 to_disable);
void ecore_iov_set_vf_to_disable(struct ecore_dev *p_dev,
u16 rel_vf_id,
u8 to_disable);
/**
*
* @brief ecore_iov_init_hw_for_vf - initialize the HW for
* enabling access of a VF. Also includes preparing the
* IGU for VF access. This needs to be called AFTER hw is
@ -171,7 +212,6 @@ enum _ecore_status_t ecore_iov_release_hw_for_vf(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 rel_vf_id);
#ifndef LINUX_REMOVE
/**
* @brief ecore_iov_set_vf_ctx - set a context for a given VF
*
@ -182,8 +222,8 @@ enum _ecore_status_t ecore_iov_release_hw_for_vf(struct ecore_hwfn *p_hwfn,
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_iov_set_vf_ctx(struct ecore_hwfn *p_hwfn,
u16 vf_id, void *ctx);
#endif
u16 vf_id,
void *ctx);
/**
* @brief FLR cleanup for all VFs
@ -332,17 +372,6 @@ void ecore_iov_bulletin_set_forced_mac(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t ecore_iov_bulletin_set_mac(struct ecore_hwfn *p_hwfn,
u8 *mac, int vfid);
/**
* @brief Set forced VLAN [pvid] in PFs copy of bulletin board
* and configures FW/HW to support the configuration.
* Setting of pvid 0 would clear the feature.
* @param p_hwfn
* @param pvid
* @param vfid
*/
void ecore_iov_bulletin_set_forced_vlan(struct ecore_hwfn *p_hwfn,
u16 pvid, int vfid);
/**
* @brief Set default behaviour of VF in case no vlans are configured for it
* whether to accept only untagged traffic or all.
@ -379,6 +408,17 @@ void ecore_iov_get_vfs_opaque_fid(struct ecore_hwfn *p_hwfn, int vfid,
void ecore_iov_get_vfs_vport_id(struct ecore_hwfn *p_hwfn, int vfid,
u8 *p_vport_id);
/**
* @brief Set forced VLAN [pvid] in PFs copy of bulletin board
* and configures FW/HW to support the configuration.
* Setting of pvid 0 would clear the feature.
* @param p_hwfn
* @param pvid
* @param vfid
*/
void ecore_iov_bulletin_set_forced_vlan(struct ecore_hwfn *p_hwfn,
u16 pvid, int vfid);
/**
* @brief Check if VF has VPORT instance. This can be used
* to check if VPORT is active.
@ -953,4 +993,22 @@ static OSAL_INLINE enum _ecore_status_t ecore_iov_configure_min_tx_rate(
return ECORE_INVAL;
}
#endif
/**
* @brief - Given a VF index, return index of next [including that] active VF.
*
* @param p_hwfn
* @param rel_vf_id
*
* @return MAX_NUM_VFS in case no further active VFs, otherwise index.
*/
u16 ecore_iov_get_next_active_vf(struct ecore_hwfn *p_hwfn, u16 rel_vf_id);
#endif /* CONFIG_ECORE_SRIOV */
#define ecore_for_each_vf(_p_hwfn, _i) \
for (_i = ecore_iov_get_next_active_vf(_p_hwfn, 0); \
_i < MAX_NUM_VFS; \
_i = ecore_iov_get_next_active_vf(_p_hwfn, _i + 1))
#endif

222
drivers/net/qede/base/ecore_iro.h
View File

@ -13,103 +13,177 @@
#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
/* Tstorm port statistics */
#define TSTORM_PORT_STAT_OFFSET(port_id) \
(IRO[1].base + ((port_id) * IRO[1].m1))
#define TSTORM_PORT_STAT_OFFSET(port_id) (IRO[1].base + ((port_id) * IRO[1].m1))
#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
/* Tstorm ll2 port statistics */
#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) (IRO[2].base + \
((port_id) * IRO[2].m1))
#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
/* Ustorm VF-PF Channel ready flag */
#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
(IRO[3].base + ((vf_id) * IRO[3].m1))
#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) (IRO[3].base + \
((vf_id) * IRO[3].m1))
#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
/* Ustorm Final flr cleanup ack */
#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
(IRO[4].base + ((pf_id) * IRO[4].m1))
#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) (IRO[4].base + ((pf_id) * IRO[4].m1))
#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
/* Ustorm Event ring consumer */
#define USTORM_EQE_CONS_OFFSET(pf_id) \
(IRO[5].base + ((pf_id) * IRO[5].m1))
#define USTORM_EQE_CONS_OFFSET(pf_id) (IRO[5].base + ((pf_id) * IRO[5].m1))
#define USTORM_EQE_CONS_SIZE (IRO[5].size)
/* Ustorm eth queue zone */
#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) (IRO[6].base + \
((queue_zone_id) * IRO[6].m1))
#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
/* Ustorm Common Queue ring consumer */
#define USTORM_COMMON_QUEUE_CONS_OFFSET(global_queue_id) \
(IRO[6].base + ((global_queue_id) * IRO[6].m1))
#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[6].size)
#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) (IRO[7].base + \
((queue_zone_id) * IRO[7].m1))
#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
/* Xstorm Integration Test Data */
#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[7].base)
#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[7].size)
#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base)
#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size)
/* Ystorm Integration Test Data */
#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[8].base)
#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[8].size)
#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
/* Pstorm Integration Test Data */
#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
/* Tstorm Integration Test Data */
#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
/* Mstorm Integration Test Data */
#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
/* Ustorm Integration Test Data */
#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
#define USTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
#define USTORM_INTEG_TEST_DATA_SIZE (IRO[13].size)
/* Tstorm producers */
#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) (IRO[14].base + \
((core_rx_queue_id) * IRO[14].m1))
#define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size)
/* Tstorm LightL2 queue statistics */
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
(IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size)
/* Ustorm LiteL2 queue statistics */
#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
(IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size)
/* Pstorm LiteL2 queue statistics */
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
(IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17].size)
/* Mstorm queue statistics */
#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[17].base + ((stat_counter_id) * IRO[17].m1))
#define MSTORM_QUEUE_STAT_SIZE (IRO[17].size)
/* Mstorm producers */
#define MSTORM_PRODS_OFFSET(queue_id) \
(IRO[18].base + ((queue_id) * IRO[18].m1))
#define MSTORM_PRODS_SIZE (IRO[18].size)
#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[18].base + \
((stat_counter_id) * IRO[18].m1))
#define MSTORM_QUEUE_STAT_SIZE (IRO[18].size)
/* Mstorm ETH PF queues producers */
#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) (IRO[19].base + \
((queue_id) * IRO[19].m1))
#define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size)
/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
* mode.
*/
#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) (IRO[20].base + \
((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
#define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size)
/* TPA agregation timeout in us resolution (on ASIC) */
#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[19].base)
#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[19].size)
#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base)
#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size)
/* Mstorm pf statistics */
#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[22].base + ((pf_id) * IRO[22].m1))
#define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size)
/* Ustorm queue statistics */
#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[20].base + ((stat_counter_id) * IRO[20].m1))
#define USTORM_QUEUE_STAT_SIZE (IRO[20].size)
/* Ustorm queue zone */
#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
(IRO[21].base + ((queue_id) * IRO[21].m1))
#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[21].size)
#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[23].base + \
((stat_counter_id) * IRO[23].m1))
#define USTORM_QUEUE_STAT_SIZE (IRO[23].size)
/* Ustorm pf statistics */
#define USTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[24].base + ((pf_id) * IRO[24].m1))
#define USTORM_ETH_PF_STAT_SIZE (IRO[24].size)
/* Pstorm queue statistics */
#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
(IRO[22].base + ((stat_counter_id) * IRO[22].m1))
#define PSTORM_QUEUE_STAT_SIZE (IRO[22].size)
#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) (IRO[25].base + \
((stat_counter_id) * IRO[25].m1))
#define PSTORM_QUEUE_STAT_SIZE (IRO[25].size)
/* Pstorm pf statistics */
#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) (IRO[26].base + ((pf_id) * IRO[26].m1))
#define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size)
/* Control frame's EthType configuration for TX control frame security */
#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) (IRO[27].base + \
((ethType_id) * IRO[27].m1))
#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size)
/* Tstorm last parser message */
#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[23].base)
#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[23].size)
#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base)
#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size)
/* Tstorm Eth limit Rx rate */
#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
(IRO[24].base + ((pf_id) * IRO[24].m1))
#define ETH_RX_RATE_LIMIT_SIZE (IRO[24].size)
/* Ystorm queue zone */
#define YSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
(IRO[25].base + ((queue_id) * IRO[25].m1))
#define YSTORM_ETH_QUEUE_ZONE_SIZE (IRO[25].size)
#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) (IRO[29].base + ((pf_id) * IRO[29].m1))
#define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size)
/* Xstorm queue zone */
#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) (IRO[30].base + \
((queue_id) * IRO[30].m1))
#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size)
/* Ystorm cqe producer */
#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
(IRO[26].base + ((rss_id) * IRO[26].m1))
#define YSTORM_TOE_CQ_PROD_SIZE (IRO[26].size)
#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[31].base + \
((rss_id) * IRO[31].m1))
#define YSTORM_TOE_CQ_PROD_SIZE (IRO[31].size)
/* Ustorm cqe producer */
#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
(IRO[27].base + ((rss_id) * IRO[27].m1))
#define USTORM_TOE_CQ_PROD_SIZE (IRO[27].size)
#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) (IRO[32].base + \
((rss_id) * IRO[32].m1))
#define USTORM_TOE_CQ_PROD_SIZE (IRO[32].size)
/* Ustorm grq producer */
#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
(IRO[28].base + ((pf_id) * IRO[28].m1))
#define USTORM_TOE_GRQ_PROD_SIZE (IRO[28].size)
#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) (IRO[33].base + \
((pf_id) * IRO[33].m1))
#define USTORM_TOE_GRQ_PROD_SIZE (IRO[33].size)
/* Tstorm cmdq-cons of given command queue-id */
#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
(IRO[29].base + ((cmdq_queue_id) * IRO[29].m1))
#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[29].size)
#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
(IRO[30].base + ((func_id) * IRO[30].m1) + ((bdq_id) * IRO[30].m2))
#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[30].size)
/* Mstorm rq-cons of given queue-id */
#define MSTORM_SCSI_RQ_CONS_OFFSET(rq_queue_id) \
(IRO[31].base + ((rq_queue_id) * IRO[31].m1))
#define MSTORM_SCSI_RQ_CONS_SIZE (IRO[31].size)
/* Mstorm bdq-external-producer of given BDQ function ID, BDqueue-id */
#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
(IRO[32].base + ((func_id) * IRO[32].m1) + ((bdq_id) * IRO[32].m2))
#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[32].size)
#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) (IRO[34].base + \
((cmdq_queue_id) * IRO[34].m1))
#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size)
/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
* BDqueue-id
*/
#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[35].base + \
((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2))
#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size)
/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) (IRO[36].base + \
((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size)
/* Tstorm iSCSI RX stats */
#define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[37].base + \
((pf_id) * IRO[37].m1))
#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size)
/* Mstorm iSCSI RX stats */
#define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[38].base + \
((pf_id) * IRO[38].m1))
#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size)
/* Ustorm iSCSI RX stats */
#define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) (IRO[39].base + \
((pf_id) * IRO[39].m1))
#define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size)
/* Xstorm iSCSI TX stats */
#define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[40].base + \
((pf_id) * IRO[40].m1))
#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size)
/* Ystorm iSCSI TX stats */
#define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[41].base + \
((pf_id) * IRO[41].m1))
#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size)
/* Pstorm iSCSI TX stats */
#define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) (IRO[42].base + \
((pf_id) * IRO[42].m1))
#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size)
/* Tstorm FCoE RX stats */
#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) (IRO[43].base + \
((pf_id) * IRO[43].m1))
#define TSTORM_FCOE_RX_STATS_SIZE (IRO[43].size)
/* Pstorm FCoE TX stats */
#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) (IRO[44].base + \
((pf_id) * IRO[44].m1))
#define PSTORM_FCOE_TX_STATS_SIZE (IRO[44].size)
/* Pstorm RDMA queue statistics */
#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
(IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1))
#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size)
/* Tstorm RDMA queue statistics */
#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) (IRO[46].base + \
((rdma_stat_counter_id) * IRO[46].m1))
#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size)
#endif /* __IRO_H__ */

108
drivers/net/qede/base/ecore_iro_values.h
View File

@ -9,51 +9,101 @@
#ifndef __IRO_VALUES_H__
#define __IRO_VALUES_H__
static const struct iro iro_arr[44] = {
static const struct iro iro_arr[47] = {
/* YSTORM_FLOW_CONTROL_MODE_OFFSET */
{ 0x0, 0x0, 0x0, 0x0, 0x8},
{0x4db0, 0x60, 0x0, 0x0, 0x60},
{0x6418, 0x20, 0x0, 0x0, 0x20},
{0x500, 0x8, 0x0, 0x0, 0x4},
{0x480, 0x8, 0x0, 0x0, 0x4},
/* TSTORM_PORT_STAT_OFFSET(port_id) */
{ 0x4cb0, 0x78, 0x0, 0x0, 0x78},
/* TSTORM_LL2_PORT_STAT_OFFSET(port_id) */
{ 0x6318, 0x20, 0x0, 0x0, 0x20},
/* USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) */
{ 0xb00, 0x8, 0x0, 0x0, 0x4},
/* USTORM_FLR_FINAL_ACK_OFFSET(pf_id) */
{ 0xa80, 0x8, 0x0, 0x0, 0x4},
/* USTORM_EQE_CONS_OFFSET(pf_id) */
{ 0x0, 0x8, 0x0, 0x0, 0x2},
{0x80, 0x8, 0x0, 0x0, 0x2},
{0x4938, 0x0, 0x0, 0x0, 0x78},
/* USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) */
{ 0x80, 0x8, 0x0, 0x0, 0x4},
/* USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) */
{ 0x84, 0x8, 0x0, 0x0, 0x2},
/* XSTORM_INTEG_TEST_DATA_OFFSET */
{ 0x4bc0, 0x0, 0x0, 0x0, 0x78},
/* YSTORM_INTEG_TEST_DATA_OFFSET */
{ 0x3df0, 0x0, 0x0, 0x0, 0x78},
/* PSTORM_INTEG_TEST_DATA_OFFSET */
{ 0x29b0, 0x0, 0x0, 0x0, 0x78},
{0x4d38, 0x0, 0x0, 0x0, 0x78},
{0x56c8, 0x0, 0x0, 0x0, 0x78},
/* TSTORM_INTEG_TEST_DATA_OFFSET */
{ 0x4c38, 0x0, 0x0, 0x0, 0x78},
/* MSTORM_INTEG_TEST_DATA_OFFSET */
{ 0x4990, 0x0, 0x0, 0x0, 0x78},
/* USTORM_INTEG_TEST_DATA_OFFSET */
{ 0x7e48, 0x0, 0x0, 0x0, 0x78},
/* TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) */
{ 0xa28, 0x8, 0x0, 0x0, 0x8},
{0x61f8, 0x10, 0x0, 0x0, 0x10},
{0xb500, 0x30, 0x0, 0x0, 0x30},
/* CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */
{ 0x60f8, 0x10, 0x0, 0x0, 0x10},
/* CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */
{ 0xb820, 0x30, 0x0, 0x0, 0x30},
/* CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) */
{ 0x95b8, 0x30, 0x0, 0x0, 0x30},
{0x5898, 0x40, 0x0, 0x0, 0x40},
{0x1f8, 0x10, 0x0, 0x0, 0x8},
{0xa228, 0x0, 0x0, 0x0, 0x4},
/* MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
{ 0x4b60, 0x80, 0x0, 0x0, 0x40},
/* MSTORM_ETH_PF_PRODS_OFFSET(queue_id) */
{ 0x1f8, 0x4, 0x0, 0x0, 0x4},
/* MSTORM_ETH_VF_PRODS_OFFSET(vf_id,vf_queue_id) */
{ 0x53a0, 0x80, 0x4, 0x0, 0x4},
/* MSTORM_TPA_TIMEOUT_US_OFFSET */
{ 0xc8f0, 0x0, 0x0, 0x0, 0x4},
/* MSTORM_ETH_PF_STAT_OFFSET(pf_id) */
{ 0x4ba0, 0x80, 0x0, 0x0, 0x20},
/* USTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
{ 0x8050, 0x40, 0x0, 0x0, 0x30},
{0xcf8, 0x8, 0x0, 0x0, 0x8},
/* USTORM_ETH_PF_STAT_OFFSET(pf_id) */
{ 0xe770, 0x60, 0x0, 0x0, 0x60},
/* PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
{ 0x2b48, 0x80, 0x0, 0x0, 0x38},
{0xadf0, 0x0, 0x0, 0x0, 0xf0},
{0xaee0, 0x8, 0x0, 0x0, 0x8},
{0x80, 0x8, 0x0, 0x0, 0x8},
/* PSTORM_ETH_PF_STAT_OFFSET(pf_id) */
{ 0xf188, 0x78, 0x0, 0x0, 0x78},
/* PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) */
{ 0x1f8, 0x4, 0x0, 0x0, 0x4},
/* TSTORM_ETH_PRS_INPUT_OFFSET */
{ 0xacf0, 0x0, 0x0, 0x0, 0xf0},
/* ETH_RX_RATE_LIMIT_OFFSET(pf_id) */
{ 0xade0, 0x8, 0x0, 0x0, 0x8},
/* XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) */
{ 0x1f8, 0x8, 0x0, 0x0, 0x8},
/* YSTORM_TOE_CQ_PROD_OFFSET(rss_id) */
{ 0xac0, 0x8, 0x0, 0x0, 0x8},
/* USTORM_TOE_CQ_PROD_OFFSET(rss_id) */
{ 0x2578, 0x8, 0x0, 0x0, 0x8},
/* USTORM_TOE_GRQ_PROD_OFFSET(pf_id) */
{ 0x24f8, 0x8, 0x0, 0x0, 0x8},
/* TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) */
{ 0x0, 0x8, 0x0, 0x0, 0x8},
/* TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */
{ 0x200, 0x10, 0x8, 0x0, 0x8},
{0x17f8, 0x8, 0x0, 0x0, 0x2},
{0x19f8, 0x10, 0x8, 0x0, 0x2},
{0xd988, 0x38, 0x0, 0x0, 0x24},
{0x11040, 0x10, 0x0, 0x0, 0x8},
{0x11670, 0x38, 0x0, 0x0, 0x18},
{0xaeb8, 0x30, 0x0, 0x0, 0x10},
/* MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */
{ 0xb78, 0x10, 0x8, 0x0, 0x2},
/* TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
{ 0xd888, 0x38, 0x0, 0x0, 0x24},
/* MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
{ 0x12c38, 0x10, 0x0, 0x0, 0x8},
/* USTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
{ 0x11aa0, 0x38, 0x0, 0x0, 0x18},
/* XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
{ 0xa8c0, 0x30, 0x0, 0x0, 0x10},
/* YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
{ 0x86f8, 0x28, 0x0, 0x0, 0x18},
{0xebf8, 0x10, 0x0, 0x0, 0x10},
{0xde08, 0x40, 0x0, 0x0, 0x30},
{0x121a0, 0x38, 0x0, 0x0, 0x8},
{0xf060, 0x20, 0x0, 0x0, 0x20},
/* PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
{ 0x101f8, 0x10, 0x0, 0x0, 0x10},
/* TSTORM_FCOE_RX_STATS_OFFSET(pf_id) */
{ 0xdd08, 0x48, 0x0, 0x0, 0x38},
/* PSTORM_FCOE_TX_STATS_OFFSET(pf_id) */
{ 0x10660, 0x20, 0x0, 0x0, 0x20},
/* PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */
{ 0x2b80, 0x80, 0x0, 0x0, 0x10},
{0x50a0, 0x10, 0x0, 0x0, 0x10},
/* TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */
{ 0x5000, 0x10, 0x0, 0x0, 0x10},
};
#endif /* __IRO_VALUES_H__ */

292
drivers/net/qede/base/ecore_l2.c
View File

@ -84,6 +84,8 @@ ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
p_ramrod->tpa_param.tpa_min_size_to_start = p_params->mtu / 2;
p_ramrod->tpa_param.tpa_ipv4_en_flg = 1;
p_ramrod->tpa_param.tpa_ipv6_en_flg = 1;
p_ramrod->tpa_param.tpa_ipv4_tunn_en_flg = 1;
p_ramrod->tpa_param.tpa_ipv6_tunn_en_flg = 1;
p_ramrod->tpa_param.tpa_pkt_split_flg = 1;
p_ramrod->tpa_param.tpa_gro_consistent_flg = 1;
break;
@ -97,6 +99,9 @@ ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
p_ramrod->tx_switching_en = 0;
#endif
p_ramrod->ctl_frame_mac_check_en = !!p_params->check_mac;
p_ramrod->ctl_frame_ethtype_check_en = !!p_params->check_ethtype;
/* Software Function ID in hwfn (PFs are 0 - 15, VFs are 16 - 135) */
p_ramrod->sw_fid = ecore_concrete_to_sw_fid(p_hwfn->p_dev,
p_params->concrete_fid);
@ -202,10 +207,12 @@ ecore_sp_vport_update_rss(struct ecore_hwfn *p_hwfn,
static void
ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
struct vport_update_ramrod_data *p_ramrod,
struct ecore_filter_accept_flags flags)
struct ecore_filter_accept_flags accept_flags)
{
p_ramrod->common.update_rx_mode_flg = flags.update_rx_mode_config;
p_ramrod->common.update_tx_mode_flg = flags.update_tx_mode_config;
p_ramrod->common.update_rx_mode_flg =
accept_flags.update_rx_mode_config;
p_ramrod->common.update_tx_mode_flg =
accept_flags.update_tx_mode_config;
#ifndef ASIC_ONLY
/* On B0 emulation we cannot enable Tx, since this would cause writes
@ -220,74 +227,55 @@ ecore_sp_update_accept_mode(struct ecore_hwfn *p_hwfn,
/* Set Rx mode accept flags */
if (p_ramrod->common.update_rx_mode_flg) {
__le16 *state = &p_ramrod->rx_mode.state;
u8 accept_filter = flags.rx_accept_filter;
u8 accept_filter = accept_flags.rx_accept_filter;
u16 state = 0;
/*
* SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
* !!(accept_filter & ECORE_ACCEPT_NONE));
*/
SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL,
(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) &&
!!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_DROP_ALL,
!(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) ||
!!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
SET_FIELD(*state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
SET_FIELD(state, ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED,
!!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED));
/*
* SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
* !!(accept_filter & ECORE_ACCEPT_NONE));
*/
SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_DROP_ALL,
!(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) ||
!!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
SET_FIELD(*state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
SET_FIELD(state, ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL,
(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
!!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
SET_FIELD(*state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
SET_FIELD(state, ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL,
!!(accept_filter & ECORE_ACCEPT_BCAST));
p_ramrod->rx_mode.state = OSAL_CPU_TO_LE16(state);
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"p_ramrod->rx_mode.state = 0x%x\n",
p_ramrod->rx_mode.state);
state);
}
/* Set Tx mode accept flags */
if (p_ramrod->common.update_tx_mode_flg) {
__le16 *state = &p_ramrod->tx_mode.state;
u8 accept_filter = flags.tx_accept_filter;
u8 accept_filter = accept_flags.tx_accept_filter;
u16 state = 0;
SET_FIELD(*state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
SET_FIELD(state, ETH_VPORT_TX_MODE_UCAST_DROP_ALL,
!!(accept_filter & ECORE_ACCEPT_NONE));
SET_FIELD(*state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_DROP_ALL,
!!(accept_filter & ECORE_ACCEPT_NONE));
SET_FIELD(*state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
SET_FIELD(state, ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL,
(!!(accept_filter & ECORE_ACCEPT_MCAST_MATCHED) &&
!!(accept_filter & ECORE_ACCEPT_MCAST_UNMATCHED)));
SET_FIELD(*state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
SET_FIELD(state, ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL,
!!(accept_filter & ECORE_ACCEPT_BCAST));
/* @DPDK */
/* ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL and
* ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL
* needs to be set for VF-VF communication to work
* when dest macaddr is unknown.
*/
SET_FIELD(*state, ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL,
(!!(accept_filter & ECORE_ACCEPT_UCAST_MATCHED) &&
!!(accept_filter & ECORE_ACCEPT_UCAST_UNMATCHED)));
p_ramrod->tx_mode.state = OSAL_CPU_TO_LE16(state);
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"p_ramrod->tx_mode.state = 0x%x\n",
p_ramrod->tx_mode.state);
state);
}
}
@ -351,12 +339,12 @@ ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
struct ecore_spq_comp_cb *p_comp_data)
{
struct ecore_rss_params *p_rss_params = p_params->rss_params;
struct vport_update_ramrod_data_cmn *p_cmn;
struct ecore_sp_init_data init_data;
struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
struct ecore_spq_entry *p_ent = OSAL_NULL;
enum _ecore_status_t rc = ECORE_NOTIMPL;
struct ecore_sp_init_data init_data;
u8 abs_vport_id = 0, val;
u16 wordval;
enum _ecore_status_t rc = ECORE_NOTIMPL;
if (IS_VF(p_hwfn->p_dev)) {
rc = ecore_vf_pf_vport_update(p_hwfn, p_params);
@ -382,30 +370,31 @@ ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
/* Copy input params to ramrod according to FW struct */
p_ramrod = &p_ent->ramrod.vport_update;
p_cmn = &p_ramrod->common;
p_ramrod->common.vport_id = abs_vport_id;
p_cmn->vport_id = abs_vport_id;
p_ramrod->common.rx_active_flg = p_params->vport_active_rx_flg;
p_ramrod->common.tx_active_flg = p_params->vport_active_tx_flg;
val = p_params->update_vport_active_rx_flg;
p_ramrod->common.update_rx_active_flg = val;
val = p_params->update_vport_active_tx_flg;
p_ramrod->common.update_tx_active_flg = val;
p_cmn->rx_active_flg = p_params->vport_active_rx_flg;
p_cmn->update_rx_active_flg = p_params->update_vport_active_rx_flg;
p_cmn->tx_active_flg = p_params->vport_active_tx_flg;
p_cmn->update_tx_active_flg = p_params->update_vport_active_tx_flg;
p_cmn->accept_any_vlan = p_params->accept_any_vlan;
val = p_params->update_accept_any_vlan_flg;
p_cmn->update_accept_any_vlan_flg = val;
p_cmn->inner_vlan_removal_en = p_params->inner_vlan_removal_flg;
val = p_params->update_inner_vlan_removal_flg;
p_ramrod->common.update_inner_vlan_removal_en_flg = val;
val = p_params->inner_vlan_removal_flg;
p_ramrod->common.inner_vlan_removal_en = val;
val = p_params->silent_vlan_removal_flg;
p_ramrod->common.silent_vlan_removal_en = val;
val = p_params->update_tx_switching_flg;
p_ramrod->common.update_tx_switching_en_flg = val;
p_cmn->update_inner_vlan_removal_en_flg = val;
p_cmn->default_vlan_en = p_params->default_vlan_enable_flg;
val = p_params->update_default_vlan_enable_flg;
p_ramrod->common.update_default_vlan_en_flg = val;
p_ramrod->common.default_vlan_en = p_params->default_vlan_enable_flg;
val = p_params->update_default_vlan_flg;
p_ramrod->common.update_default_vlan_flg = val;
wordval = p_params->default_vlan;
p_ramrod->common.default_vlan = OSAL_CPU_TO_LE16(wordval);
p_cmn->update_default_vlan_en_flg = val;
p_cmn->default_vlan = OSAL_CPU_TO_LE16(p_params->default_vlan);
p_cmn->update_default_vlan_flg = p_params->update_default_vlan_flg;
p_cmn->silent_vlan_removal_en = p_params->silent_vlan_removal_flg;
p_ramrod->common.tx_switching_en = p_params->tx_switching_flg;
@ -419,13 +408,11 @@ ecore_sp_vport_update(struct ecore_hwfn *p_hwfn,
p_ramrod->common.update_tx_switching_en_flg = 1;
}
#endif
p_cmn->update_tx_switching_en_flg = p_params->update_tx_switching_flg;
p_cmn->anti_spoofing_en = p_params->anti_spoofing_en;
val = p_params->update_anti_spoofing_en_flg;
p_ramrod->common.update_anti_spoofing_en_flg = val;
p_ramrod->common.anti_spoofing_en = p_params->anti_spoofing_en;
p_ramrod->common.accept_any_vlan = p_params->accept_any_vlan;
val = p_params->update_accept_any_vlan_flg;
p_ramrod->common.update_accept_any_vlan_flg = val;
rc = ecore_sp_vport_update_rss(p_hwfn, p_ramrod, p_rss_params);
if (rc != ECORE_SUCCESS) {
@ -499,20 +486,20 @@ ecore_filter_accept_cmd(struct ecore_dev *p_dev,
enum spq_mode comp_mode,
struct ecore_spq_comp_cb *p_comp_data)
{
struct ecore_sp_vport_update_params update_params;
struct ecore_sp_vport_update_params vport_update_params;
int i, rc;
/* Prepare and send the vport rx_mode change */
OSAL_MEMSET(&update_params, 0, sizeof(update_params));
update_params.vport_id = vport;
update_params.accept_flags = accept_flags;
update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
update_params.accept_any_vlan = accept_any_vlan;
OSAL_MEMSET(&vport_update_params, 0, sizeof(vport_update_params));
vport_update_params.vport_id = vport;
vport_update_params.accept_flags = accept_flags;
vport_update_params.update_accept_any_vlan_flg = update_accept_any_vlan;
vport_update_params.accept_any_vlan = accept_any_vlan;
for_each_hwfn(p_dev, i) {
struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
vport_update_params.opaque_fid = p_hwfn->hw_info.opaque_fid;
if (IS_VF(p_dev)) {
rc = ecore_vf_pf_accept_flags(p_hwfn, &accept_flags);
@ -521,7 +508,7 @@ ecore_filter_accept_cmd(struct ecore_dev *p_dev,
continue;
}
rc = ecore_sp_vport_update(p_hwfn, &update_params,
rc = ecore_sp_vport_update(p_hwfn, &vport_update_params,
comp_mode, p_comp_data);
if (rc != ECORE_SUCCESS) {
DP_ERR(p_dev, "Update rx_mode failed %d\n", rc);
@ -557,23 +544,26 @@ ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
u16 opaque_fid,
u32 cid,
u16 rx_queue_id,
u8 vf_rx_queue_id,
u8 vport_id,
u8 stats_id,
u16 sb,
u8 sb_index,
u16 bd_max_bytes,
dma_addr_t bd_chain_phys_addr,
dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size)
dma_addr_t cqe_pbl_addr,
u16 cqe_pbl_size, bool b_use_zone_a_prod)
{
struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
struct rx_queue_start_ramrod_data *p_ramrod = OSAL_NULL;
struct ecore_spq_entry *p_ent = OSAL_NULL;
enum _ecore_status_t rc = ECORE_NOTIMPL;
struct ecore_sp_init_data init_data;
struct ecore_hw_cid_data *p_rx_cid;
u16 abs_rx_q_id = 0;
u8 abs_vport_id = 0;
enum _ecore_status_t rc = ECORE_NOTIMPL;
/* Store information for the stop */
p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
p_rx_cid->cid = cid;
p_rx_cid->opaque_fid = opaque_fid;
p_rx_cid->vport_id = vport_id;
@ -618,6 +608,15 @@ ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
p_ramrod->num_of_pbl_pages = OSAL_CPU_TO_LE16(cqe_pbl_size);
DMA_REGPAIR_LE(p_ramrod->cqe_pbl_addr, cqe_pbl_addr);
if (vf_rx_queue_id || b_use_zone_a_prod) {
p_ramrod->vf_rx_prod_index = vf_rx_queue_id;
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"Queue%s is meant for VF rxq[%02x]\n",
b_use_zone_a_prod ? " [legacy]" : "",
vf_rx_queue_id);
p_ramrod->vf_rx_prod_use_zone_a = b_use_zone_a_prod;
}
return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
}
@ -634,11 +633,11 @@ enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
u16 cqe_pbl_size,
void OSAL_IOMEM **pp_prod)
{
struct ecore_hw_cid_data *p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
u8 abs_stats_id = 0;
struct ecore_hw_cid_data *p_rx_cid;
u32 init_prod_val = 0;
u16 abs_l2_queue = 0;
u8 abs_stats_id = 0;
enum _ecore_status_t rc;
u64 init_prod_val = 0;
if (IS_VF(p_hwfn->p_dev)) {
return ecore_vf_pf_rxq_start(p_hwfn,
@ -660,14 +659,17 @@ enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
return rc;
*pp_prod = (u8 OSAL_IOMEM *)p_hwfn->regview +
GTT_BAR0_MAP_REG_MSDM_RAM + MSTORM_PRODS_OFFSET(abs_l2_queue);
GTT_BAR0_MAP_REG_MSDM_RAM +
MSTORM_ETH_PF_PRODS_OFFSET(abs_l2_queue);
/* Init the rcq, rx bd and rx sge (if valid) producers to 0 */
__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u64),
__internal_ram_wr(p_hwfn, *pp_prod, sizeof(u32),
(u32 *)(&init_prod_val));
/* Allocate a CID for the queue */
rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_rx_cid->cid);
p_rx_cid = &p_hwfn->p_rx_cids[rx_queue_id];
rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH,
&p_rx_cid->cid);
if (rc != ECORE_SUCCESS) {
DP_NOTICE(p_hwfn, true, "Failed to acquire cid\n");
return rc;
@ -678,13 +680,16 @@ enum _ecore_status_t ecore_sp_eth_rx_queue_start(struct ecore_hwfn *p_hwfn,
opaque_fid,
p_rx_cid->cid,
rx_queue_id,
0,
vport_id,
abs_stats_id,
sb,
sb_index,
bd_max_bytes,
bd_chain_phys_addr,
cqe_pbl_addr, cqe_pbl_size);
cqe_pbl_addr,
cqe_pbl_size,
false);
if (rc != ECORE_SUCCESS)
ecore_sp_release_queue_cid(p_hwfn, p_rx_cid);
@ -859,8 +864,7 @@ ecore_sp_eth_txq_start_ramrod(struct ecore_hwfn *p_hwfn,
p_ramrod->queue_zone_id = OSAL_CPU_TO_LE16(abs_tx_q_id);
p_ramrod->pbl_size = OSAL_CPU_TO_LE16(pbl_size);
p_ramrod->pbl_base_addr.hi = DMA_HI_LE(pbl_addr);
p_ramrod->pbl_base_addr.lo = DMA_LO_LE(pbl_addr);
DMA_REGPAIR_LE(p_ramrod->pbl_base_addr, pbl_addr);
pq_id = ecore_get_qm_pq(p_hwfn, PROTOCOLID_ETH, p_pq_params);
p_ramrod->qm_pq_id = OSAL_CPU_TO_LE16(pq_id);
@ -875,30 +879,36 @@ enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
u8 stats_id,
u16 sb,
u8 sb_index,
u8 tc,
dma_addr_t pbl_addr,
u16 pbl_size,
void OSAL_IOMEM **pp_doorbell)
{
struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
struct ecore_hw_cid_data *p_tx_cid;
union ecore_qm_pq_params pq_params;
enum _ecore_status_t rc;
u8 abs_stats_id = 0;
enum _ecore_status_t rc;
if (IS_VF(p_hwfn->p_dev)) {
return ecore_vf_pf_txq_start(p_hwfn,
tx_queue_id,
sb,
sb_index,
pbl_addr, pbl_size, pp_doorbell);
pbl_addr,
pbl_size,
pp_doorbell);
}
rc = ecore_fw_vport(p_hwfn, stats_id, &abs_stats_id);
if (rc != ECORE_SUCCESS)
return rc;
p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
OSAL_MEMSET(p_tx_cid, 0, sizeof(*p_tx_cid));
OSAL_MEMSET(&pq_params, 0, sizeof(pq_params));
pq_params.eth.tc = tc;
/* Allocate a CID for the queue */
rc = ecore_cxt_acquire_cid(p_hwfn, PROTOCOLID_ETH, &p_tx_cid->cid);
if (rc != ECORE_SUCCESS) {
@ -943,10 +953,9 @@ enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
u16 tx_queue_id)
{
struct ecore_hw_cid_data *p_tx_cid = &p_hwfn->p_tx_cids[tx_queue_id];
struct tx_queue_stop_ramrod_data *p_ramrod = OSAL_NULL;
struct ecore_spq_entry *p_ent = OSAL_NULL;
enum _ecore_status_t rc = ECORE_NOTIMPL;
struct ecore_sp_init_data init_data;
enum _ecore_status_t rc = ECORE_NOTIMPL;
if (IS_VF(p_hwfn->p_dev))
return ecore_vf_pf_txq_stop(p_hwfn, tx_queue_id);
@ -963,8 +972,6 @@ enum _ecore_status_t ecore_sp_eth_tx_queue_stop(struct ecore_hwfn *p_hwfn,
if (rc != ECORE_SUCCESS)
return rc;
p_ramrod = &p_ent->ramrod.tx_queue_stop;
rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
if (rc != ECORE_SUCCESS)
return rc;
@ -1247,7 +1254,7 @@ static u32 ecore_calc_crc32c(u8 *crc32_packet,
return crc32_result;
}
static OSAL_INLINE u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
static u32 ecore_crc32c_le(u32 seed, u8 *mac, u32 len)
{
u32 packet_buf[2] = { 0 };
@ -1270,18 +1277,22 @@ ecore_sp_eth_filter_mcast(struct ecore_hwfn *p_hwfn,
enum spq_mode comp_mode,
struct ecore_spq_comp_cb *p_comp_data)
{
struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
unsigned long bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
struct vport_update_ramrod_data *p_ramrod = OSAL_NULL;
struct ecore_spq_entry *p_ent = OSAL_NULL;
struct ecore_sp_init_data init_data;
enum _ecore_status_t rc;
u8 abs_vport_id = 0;
enum _ecore_status_t rc;
int i;
if (p_filter_cmd->opcode == ECORE_FILTER_ADD)
rc = ecore_fw_vport(p_hwfn,
(p_filter_cmd->opcode == ECORE_FILTER_ADD) ?
p_filter_cmd->vport_to_add_to :
p_filter_cmd->vport_to_remove_from, &abs_vport_id);
p_filter_cmd->vport_to_add_to,
&abs_vport_id);
else
rc = ecore_fw_vport(p_hwfn,
p_filter_cmd->vport_to_remove_from,
&abs_vport_id);
if (rc != ECORE_SUCCESS)
return rc;
@ -1356,14 +1367,16 @@ ecore_filter_mcast_cmd(struct ecore_dev *p_dev,
for_each_hwfn(p_dev, i) {
struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
u16 opaque_fid;
if (IS_VF(p_dev)) {
ecore_vf_pf_filter_mcast(p_hwfn, p_filter_cmd);
continue;
}
opaque_fid = p_hwfn->hw_info.opaque_fid;
rc = ecore_sp_eth_filter_mcast(p_hwfn,
p_hwfn->hw_info.opaque_fid,
opaque_fid,
p_filter_cmd,
comp_mode, p_comp_data);
if (rc != ECORE_SUCCESS)
@ -1384,14 +1397,16 @@ ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
for_each_hwfn(p_dev, i) {
struct ecore_hwfn *p_hwfn = &p_dev->hwfns[i];
u16 opaque_fid;
if (IS_VF(p_dev)) {
rc = ecore_vf_pf_filter_ucast(p_hwfn, p_filter_cmd);
continue;
}
opaque_fid = p_hwfn->hw_info.opaque_fid;
rc = ecore_sp_eth_filter_ucast(p_hwfn,
p_hwfn->hw_info.opaque_fid,
opaque_fid,
p_filter_cmd,
comp_mode, p_comp_data);
if (rc != ECORE_SUCCESS)
@ -1401,77 +1416,6 @@ ecore_filter_ucast_cmd(struct ecore_dev *p_dev,
return rc;
}
/* IOV related */
enum _ecore_status_t ecore_sp_vf_start(struct ecore_hwfn *p_hwfn,
u32 concrete_vfid, u16 opaque_vfid)
{
struct vf_start_ramrod_data *p_ramrod = OSAL_NULL;
struct ecore_spq_entry *p_ent = OSAL_NULL;
enum _ecore_status_t rc = ECORE_NOTIMPL;
struct ecore_sp_init_data init_data;
/* Get SPQ entry */
OSAL_MEMSET(&init_data, 0, sizeof(init_data));
init_data.cid = ecore_spq_get_cid(p_hwfn);
init_data.opaque_fid = opaque_vfid;
init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
rc = ecore_sp_init_request(p_hwfn, &p_ent,
COMMON_RAMROD_VF_START,
PROTOCOLID_COMMON, &init_data);
if (rc != ECORE_SUCCESS)
return rc;
p_ramrod = &p_ent->ramrod.vf_start;
p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
p_ramrod->opaque_fid = OSAL_CPU_TO_LE16(opaque_vfid);
switch (p_hwfn->hw_info.personality) {
case ECORE_PCI_ETH:
p_ramrod->personality = PERSONALITY_ETH;
break;
default:
DP_NOTICE(p_hwfn, true, "Unknown VF personality %d\n",
p_hwfn->hw_info.personality);
return ECORE_INVAL;
}
return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
}
enum _ecore_status_t ecore_sp_vf_update(struct ecore_hwfn *p_hwfn)
{
return ECORE_NOTIMPL;
}
enum _ecore_status_t ecore_sp_vf_stop(struct ecore_hwfn *p_hwfn,
u32 concrete_vfid, u16 opaque_vfid)
{
enum _ecore_status_t rc = ECORE_NOTIMPL;
struct vf_stop_ramrod_data *p_ramrod = OSAL_NULL;
struct ecore_spq_entry *p_ent = OSAL_NULL;
struct ecore_sp_init_data init_data;
/* Get SPQ entry */
OSAL_MEMSET(&init_data, 0, sizeof(init_data));
init_data.cid = ecore_spq_get_cid(p_hwfn);
init_data.opaque_fid = opaque_vfid;
init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
rc = ecore_sp_init_request(p_hwfn, &p_ent,
COMMON_RAMROD_VF_STOP,
PROTOCOLID_COMMON, &init_data);
if (rc != ECORE_SUCCESS)
return rc;
p_ramrod = &p_ent->ramrod.vf_stop;
p_ramrod->vf_id = GET_FIELD(concrete_vfid, PXP_CONCRETE_FID_VFID);
return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
}
/* Statistics related code */
static void __ecore_get_vport_pstats_addrlen(struct ecore_hwfn *p_hwfn,
u32 *p_addr, u32 *p_len,
@ -1740,7 +1684,7 @@ static void _ecore_get_vport_stats(struct ecore_dev *p_dev,
IS_PF(p_dev) ? true : false);
out:
if (IS_PF(p_dev))
if (IS_PF(p_dev) && p_ptt)
ecore_ptt_release(p_hwfn, p_ptt);
}
}

57
drivers/net/qede/base/ecore_l2.h
View File

@ -9,61 +9,12 @@
#ifndef __ECORE_L2_H__
#define __ECORE_L2_H__
#include "ecore.h"
#include "ecore_hw.h"
#include "ecore_spq.h"
#include "ecore_l2_api.h"
/**
* @brief ecore_sp_vf_start - VF Function Start
*
* This ramrod is sent to initialize a virtual function (VF) is loaded.
* It will configure the function related parameters.
*
* @note Final phase API.
*
* @param p_hwfn
* @param concrete_vfid VF ID
* @param opaque_vfid
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_sp_vf_start(struct ecore_hwfn *p_hwfn,
u32 concrete_vfid, u16 opaque_vfid);
/**
* @brief ecore_sp_vf_update - VF Function Update Ramrod
*
* This ramrod performs updates of a virtual function (VF).
* It currently contains no functionality.
*
* @note Final phase API.
*
* @param p_hwfn
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_sp_vf_update(struct ecore_hwfn *p_hwfn);
/**
* @brief ecore_sp_vf_stop - VF Function Stop Ramrod
*
* This ramrod is sent to unload a virtual function (VF).
*
* @note Final phase API.
*
* @param p_hwfn
* @param concrete_vfid
* @param opaque_vfid
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_sp_vf_stop(struct ecore_hwfn *p_hwfn,
u32 concrete_vfid, u16 opaque_vfid);
/**
* @brief ecore_sp_eth_tx_queue_update -
*
@ -98,7 +49,7 @@ ecore_sp_eth_vport_start(struct ecore_hwfn *p_hwfn,
* @param bd_chain_phys_addr
* @param cqe_pbl_addr
* @param cqe_pbl_size
* @param leading
* @param b_use_zone_a_prod - support legacy VF producers
*
* @return enum _ecore_status_t
*/
@ -107,13 +58,15 @@ ecore_sp_eth_rxq_start_ramrod(struct ecore_hwfn *p_hwfn,
u16 opaque_fid,
u32 cid,
u16 rx_queue_id,
u8 vf_rx_queue_id,
u8 vport_id,
u8 stats_id,
u16 sb,
u8 sb_index,
u16 bd_max_bytes,
dma_addr_t bd_chain_phys_addr,
dma_addr_t cqe_pbl_addr, u16 cqe_pbl_size);
dma_addr_t cqe_pbl_addr,
u16 cqe_pbl_size, bool b_use_zone_a_prod);
/**
* @brief - Starts a Tx queue; Should be used where contexts are handled

9
drivers/net/qede/base/ecore_l2_api.h
View File

@ -218,11 +218,12 @@ ecore_sp_eth_rx_queue_stop(struct ecore_hwfn *p_hwfn,
* @param opaque_fid
* @param tx_queue_id TX Queue ID
* @param vport_id VPort ID
* @param stats_id VPort ID which the queue stats
* @param u8 stats_id VPort ID which the queue stats
* will be added to
* @param sb Status Block of the Function Event Ring
* @param sb_index Index into the status block of the Function
* Event Ring
* @param tc traffic class to use with this L2 txq
* @param pbl_addr address of the pbl array
* @param pbl_size number of entries in pbl
* @param pp_doorbell Pointer to place doorbell pointer (May be NULL).
@ -238,10 +239,10 @@ enum _ecore_status_t ecore_sp_eth_tx_queue_start(struct ecore_hwfn *p_hwfn,
u8 stats_id,
u16 sb,
u8 sb_index,
u8 tc,
dma_addr_t pbl_addr,
u16 pbl_size,
void OSAL_IOMEM * *
pp_doorbell);
void OSAL_IOMEM **pp_doorbell);
/**
* @brief ecore_sp_eth_tx_queue_stop -
@ -277,6 +278,8 @@ struct ecore_sp_vport_start_params {
u8 vport_id; /* VPORT ID */
u16 mtu; /* VPORT MTU */
bool zero_placement_offset;
bool check_mac;
bool check_ethtype;
};
/**

350
drivers/net/qede/base/ecore_mcp.c
View File

@ -15,6 +15,7 @@
#include "ecore_hw.h"
#include "ecore_init_fw_funcs.h"
#include "ecore_sriov.h"
#include "ecore_vf.h"
#include "ecore_iov_api.h"
#include "ecore_gtt_reg_addr.h"
#include "ecore_iro.h"
@ -227,7 +228,8 @@ static enum _ecore_status_t ecore_mcp_mb_lock(struct ecore_hwfn *p_hwfn,
if (p_hwfn->mcp_info->block_mb_sending) {
DP_NOTICE(p_hwfn, false,
"Trying to send a MFW mailbox command [0x%x] in parallel to [UN]LOAD_REQ. Aborting.\n",
"Trying to send a MFW mailbox command [0x%x]"
" in parallel to [UN]LOAD_REQ. Aborting.\n",
cmd);
OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
return ECORE_BUSY;
@ -259,6 +261,7 @@ enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
delay = EMUL_MCP_RESP_ITER_US;
#endif
/* Ensure that only a single thread is accessing the mailbox at a
* certain time.
*/
@ -292,7 +295,6 @@ enum _ecore_status_t ecore_mcp_reset(struct ecore_hwfn *p_hwfn,
return rc;
}
/* Should be called while the dedicated spinlock is acquired */
static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 cmd, u32 param,
@ -300,12 +302,16 @@ static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
u32 *o_mcp_param)
{
u32 delay = CHIP_MCP_RESP_ITER_US;
u32 max_retries = ECORE_DRV_MB_MAX_RETRIES;
u32 seq, cnt = 1, actual_mb_seq;
enum _ecore_status_t rc = ECORE_SUCCESS;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
delay = EMUL_MCP_RESP_ITER_US;
/* There is a built-in delay of 100usec in each MFW response read */
if (CHIP_REV_IS_FPGA(p_hwfn->p_dev))
max_retries /= 10;
#endif
/* Get actual driver mailbox sequence */
@ -329,10 +335,6 @@ static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
/* Set drv command along with the updated sequence */
DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (cmd | seq));
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"wrote command (%x) to MFW MB param 0x%08x\n",
(cmd | seq), param);
do {
/* Wait for MFW response */
OSAL_UDELAY(delay);
@ -340,11 +342,7 @@ static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
/* Give the FW up to 5 second (500*10ms) */
} while ((seq != (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) &&
(cnt++ < ECORE_DRV_MB_MAX_RETRIES));
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"[after %d ms] read (%x) seq is (%x) from FW MB\n",
cnt * delay, *o_mcp_resp, seq);
(cnt++ < max_retries));
/* Is this a reply to our command? */
if (seq == (*o_mcp_resp & FW_MSG_SEQ_NUMBER_MASK)) {
@ -362,9 +360,9 @@ static enum _ecore_status_t ecore_do_mcp_cmd(struct ecore_hwfn *p_hwfn,
return rc;
}
static enum _ecore_status_t
ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
ecore_mcp_cmd_and_union(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct ecore_mcp_mb_params *p_mb_params)
{
u32 union_data_addr;
@ -423,6 +421,7 @@ enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
return ECORE_SUCCESS;
}
#endif
OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
mb_params.cmd = cmd;
mb_params.param = param;
@ -451,7 +450,7 @@ enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
mb_params.cmd = cmd;
mb_params.param = param;
OSAL_MEMCPY(&union_data.raw_data, i_buf, i_txn_size);
OSAL_MEMCPY((u32 *)&union_data.raw_data, i_buf, i_txn_size);
mb_params.p_data_src = &union_data;
rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
if (rc != ECORE_SUCCESS)
@ -471,30 +470,25 @@ enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
u32 *o_mcp_param,
u32 *o_txn_size, u32 *o_buf)
{
struct ecore_mcp_mb_params mb_params;
union drv_union_data union_data;
enum _ecore_status_t rc;
u32 i;
/* MCP not initialized */
if (!ecore_mcp_is_init(p_hwfn)) {
DP_NOTICE(p_hwfn, true, "MFW is not initialized !\n");
return ECORE_BUSY;
}
OSAL_SPIN_LOCK(&p_hwfn->mcp_info->lock);
rc = ecore_do_mcp_cmd(p_hwfn, p_ptt, cmd, param, o_mcp_resp,
o_mcp_param);
OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
mb_params.cmd = cmd;
mb_params.param = param;
mb_params.p_data_dst = &union_data;
rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
if (rc != ECORE_SUCCESS)
goto out;
return rc;
*o_mcp_resp = mb_params.mcp_resp;
*o_mcp_param = mb_params.mcp_param;
/* Get payload after operation completes successfully */
*o_txn_size = *o_mcp_param;
for (i = 0; i < *o_txn_size; i += 4)
o_buf[i / sizeof(u32)] = DRV_MB_RD(p_hwfn, p_ptt,
union_data.raw_data[i]);
OSAL_MEMCPY(o_buf, (u32 *)&union_data.raw_data, *o_txn_size);
out:
OSAL_SPIN_UNLOCK(&p_hwfn->mcp_info->lock);
return rc;
return ECORE_SUCCESS;
}
#ifndef ASIC_ONLY
@ -532,7 +526,6 @@ enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
struct ecore_dev *p_dev = p_hwfn->p_dev;
struct ecore_mcp_mb_params mb_params;
union drv_union_data union_data;
u32 param;
enum _ecore_status_t rc;
#ifndef ASIC_ONLY
@ -556,6 +549,8 @@ enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
return rc;
}
*p_load_code = mb_params.mcp_resp;
/* If MFW refused (e.g. other port is in diagnostic mode) we
* must abort. This can happen in the following cases:
* - Other port is in diagnostic mode
@ -617,7 +612,6 @@ enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
MCP_PF_ID(p_hwfn));
struct ecore_mcp_mb_params mb_params;
union drv_union_data union_data;
u32 resp, param;
enum _ecore_status_t rc;
int i;
@ -630,9 +624,10 @@ enum _ecore_status_t ecore_mcp_ack_vf_flr(struct ecore_hwfn *p_hwfn,
mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
OSAL_MEMCPY(&union_data.ack_vf_disabled, vfs_to_ack, VF_MAX_STATIC / 8);
mb_params.p_data_src = &union_data;
rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt,
&mb_params);
if (rc != ECORE_SUCCESS) {
DP_NOTICE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IOV),
DP_NOTICE(p_hwfn, false,
"Failed to pass ACK for VF flr to MFW\n");
return ECORE_TIMEOUT;
}
@ -673,9 +668,11 @@ static void ecore_mcp_handle_transceiver_change(struct ecore_hwfn *p_hwfn,
}
static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, bool b_reset)
struct ecore_ptt *p_ptt,
bool b_reset)
{
struct ecore_mcp_link_state *p_link;
u8 max_bw, min_bw;
u32 status = 0;
p_link = &p_hwfn->mcp_info->link_output;
@ -739,23 +736,18 @@ static void ecore_mcp_handle_link_change(struct ecore_hwfn *p_hwfn,
else
p_link->line_speed = 0;
/* Correct speed according to bandwidth allocation */
if (p_hwfn->mcp_info->func_info.bandwidth_max && p_link->speed) {
u8 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
/* Max bandwidth configuration */
__ecore_configure_pf_max_bandwidth(p_hwfn, p_ptt,
p_link, max_bw);
}
if (p_hwfn->mcp_info->func_info.bandwidth_min && p_link->speed) {
u8 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
/* Mintz bandwidth configuration */
__ecore_configure_pf_min_bandwidth(p_hwfn, p_ptt,
p_link, min_bw);
ecore_configure_vp_wfq_on_link_change(p_hwfn->p_dev,
p_link->min_pf_rate);
}
p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
p_link->an_complete = !!(status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
@ -822,8 +814,8 @@ enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
struct ecore_mcp_mb_params mb_params;
union drv_union_data union_data;
struct pmm_phy_cfg *p_phy_cfg;
u32 param = 0, reply = 0, cmd;
enum _ecore_status_t rc = ECORE_SUCCESS;
u32 cmd;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_EMUL(p_hwfn->p_dev))
@ -841,16 +833,6 @@ enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
p_phy_cfg->pause |= (params->pause.forced_tx) ? PMM_PAUSE_TX : 0;
p_phy_cfg->adv_speed = params->speed.advertised_speeds;
p_phy_cfg->loopback_mode = params->loopback_mode;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_FPGA(p_hwfn->p_dev)) {
DP_INFO(p_hwfn,
"Link on FPGA - Ask for loopback mode '5' at 10G\n");
p_phy_cfg->loopback_mode = 5;
p_phy_cfg->speed = 10000;
}
#endif
p_hwfn->b_drv_link_init = b_up;
if (b_up)
@ -945,8 +927,8 @@ static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
enum ecore_mcp_protocol_type stats_type;
union ecore_mcp_protocol_stats stats;
struct ecore_mcp_mb_params mb_params;
u32 hsi_param, param = 0, reply = 0;
union drv_union_data union_data;
u32 hsi_param;
switch (type) {
case MFW_DRV_MSG_GET_LAN_STATS:
@ -968,26 +950,6 @@ static void ecore_mcp_send_protocol_stats(struct ecore_hwfn *p_hwfn,
ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
}
static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct public_func *p_data, int pfid)
{
u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
PUBLIC_FUNC);
u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
u32 i, size;
OSAL_MEM_ZERO(p_data, sizeof(*p_data));
size = OSAL_MIN_T(u32, sizeof(*p_data), SECTION_SIZE(mfw_path_offsize));
for (i = 0; i < size / sizeof(u32); i++)
((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
func_addr + (i << 2));
return size;
}
static void
ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
struct public_func *p_shmem_info)
@ -1023,6 +985,28 @@ ecore_read_pf_bandwidth(struct ecore_hwfn *p_hwfn,
}
}
static u32 ecore_mcp_get_shmem_func(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct public_func *p_data,
int pfid)
{
u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
PUBLIC_FUNC);
u32 mfw_path_offsize = ecore_rd(p_hwfn, p_ptt, addr);
u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
u32 i, size;
OSAL_MEM_ZERO(p_data, sizeof(*p_data));
size = OSAL_MIN_T(u32, sizeof(*p_data),
SECTION_SIZE(mfw_path_offsize));
for (i = 0; i < size / sizeof(u32); i++)
((u32 *)p_data)[i] = ecore_rd(p_hwfn, p_ptt,
func_addr + (i << 2));
return size;
}
static void
ecore_mcp_update_bw(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
{
@ -1102,6 +1086,9 @@ enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
ecore_dcbx_mib_update_event(p_hwfn, p_ptt,
ECORE_DCBX_OPERATIONAL_MIB);
break;
case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
break;
case MFW_DRV_MSG_ERROR_RECOVERY:
ecore_mcp_handle_process_kill(p_hwfn, p_ptt);
break;
@ -1114,9 +1101,6 @@ enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
case MFW_DRV_MSG_BW_UPDATE:
ecore_mcp_update_bw(p_hwfn, p_ptt);
break;
case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
ecore_mcp_handle_transceiver_change(p_hwfn, p_ptt);
break;
case MFW_DRV_MSG_FAILURE_DETECTED:
ecore_mcp_handle_fan_failure(p_hwfn, p_ptt);
break;
@ -1152,34 +1136,33 @@ enum _ecore_status_t ecore_mcp_handle_events(struct ecore_hwfn *p_hwfn,
return rc;
}
enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_dev *p_dev,
enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *p_mfw_ver,
u32 *p_running_bundle_id)
{
struct ecore_hwfn *p_hwfn = ECORE_LEADING_HWFN(p_dev);
u32 global_offsize;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_EMUL(p_dev)) {
DP_NOTICE(p_dev, false, "Emulation - can't get MFW version\n");
if (CHIP_REV_IS_EMUL(p_hwfn->p_dev)) {
DP_NOTICE(p_hwfn, false, "Emulation - can't get MFW version\n");
return ECORE_SUCCESS;
}
#endif
if (IS_VF(p_dev)) {
if (IS_VF(p_hwfn->p_dev)) {
if (p_hwfn->vf_iov_info) {
struct pfvf_acquire_resp_tlv *p_resp;
p_resp = &p_hwfn->vf_iov_info->acquire_resp;
*p_mfw_ver = p_resp->pfdev_info.mfw_ver;
return ECORE_SUCCESS;
}
DP_VERBOSE(p_dev, ECORE_MSG_IOV,
"VF requested MFW vers prior to ACQUIRE\n");
} else {
DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
"VF requested MFW version prior to ACQUIRE\n");
return ECORE_INVAL;
}
}
global_offsize = ecore_rd(p_hwfn, p_ptt,
SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->
@ -1280,18 +1263,25 @@ enum _ecore_status_t ecore_mcp_fill_shmem_func_info(struct ecore_hwfn *p_hwfn,
DP_NOTICE(p_hwfn, false, "MAC is 0 in shmem\n");
}
/* TODO - are these calculations true for BE machine? */
info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_upper |
(((u64)shmem_info.fcoe_wwn_port_name_lower) << 32);
info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_upper |
(((u64)shmem_info.fcoe_wwn_node_name_lower) << 32);
info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
DP_VERBOSE(p_hwfn, (ECORE_MSG_SP | ECORE_MSG_IFUP),
"Read configuration from shmem: pause_on_host %02x"
" protocol %02x BW [%02x - %02x]"
" MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %" PRIx64
" node %" PRIx64 " ovlan %04x\n",
" MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %lx"
" node %lx ovlan %04x\n",
info->pause_on_host, info->protocol,
info->bandwidth_min, info->bandwidth_max,
info->mac[0], info->mac[1], info->mac[2],
info->mac[3], info->mac[4], info->mac[5],
info->wwn_port, info->wwn_node, info->ovlan);
(unsigned long)info->wwn_port,
(unsigned long)info->wwn_node, info->ovlan);
return ECORE_SUCCESS;
}
@ -1331,14 +1321,14 @@ struct ecore_mcp_link_capabilities
enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
enum _ecore_status_t rc;
u32 resp = 0, param = 0;
enum _ecore_status_t rc;
rc = ecore_mcp_cmd(p_hwfn, p_ptt,
DRV_MSG_CODE_NIG_DRAIN, 100, &resp, &param);
DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, &param);
/* Wait for the drain to complete before returning */
OSAL_MSLEEP(120);
OSAL_MSLEEP(1020);
return rc;
}
@ -1464,6 +1454,12 @@ enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
u32 resp = 0, param = 0, rc_param = 0;
enum _ecore_status_t rc;
/* Only Leader can configure MSIX, and need to take CMT into account */
if (!IS_LEAD_HWFN(p_hwfn))
return ECORE_SUCCESS;
num *= p_hwfn->p_dev->num_hwfns;
param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
@ -1476,6 +1472,10 @@ enum _ecore_status_t ecore_mcp_config_vf_msix(struct ecore_hwfn *p_hwfn,
DP_NOTICE(p_hwfn, true, "VF[%d]: MFW failed to set MSI-X\n",
vf_id);
rc = ECORE_INVAL;
} else {
DP_VERBOSE(p_hwfn, ECORE_MSG_IOV,
"Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
num, vf_id);
}
return rc;
@ -1485,10 +1485,10 @@ enum _ecore_status_t
ecore_mcp_send_drv_version(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
struct ecore_mcp_drv_version *p_ver)
{
u32 param = 0, reply = 0, num_words, i;
struct drv_version_stc *p_drv_version;
struct ecore_mcp_mb_params mb_params;
union drv_union_data union_data;
u32 num_words, i;
void *p_name;
OSAL_BE32 val;
enum _ecore_status_t rc;
@ -1705,6 +1705,14 @@ enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
break;
}
/* This can be a lengthy process, and it's possible scheduler
* isn't preemptible. Sleep a bit to prevent CPU hogging.
*/
if (bytes_left % 0x1000 <
(bytes_left - *params.nvm_rd.buf_size) % 0x1000)
OSAL_MSLEEP(1);
offset += *params.nvm_rd.buf_size;
bytes_left -= *params.nvm_rd.buf_size;
}
@ -1842,6 +1850,13 @@ enum _ecore_status_t ecore_mcp_nvm_write(struct ecore_dev *p_dev, u32 cmd,
FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK)))
DP_NOTICE(p_dev, false, "MCP command rc = %d\n", rc);
/* This can be a lengthy process, and it's possible scheduler
* isn't preemptible. Sleep a bit to prevent CPU hogging.
*/
if (buf_idx % 0x1000 >
(buf_idx + buf_size) % 0x1000)
OSAL_MSLEEP(1);
buf_idx += buf_size;
}
@ -1912,10 +1927,9 @@ enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
u32 bytes_left, bytes_to_copy, buf_size;
OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
SET_FIELD(params.nvm_common.offset,
DRV_MB_PARAM_TRANSCEIVER_PORT, port);
SET_FIELD(params.nvm_common.offset,
DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS, addr);
params.nvm_common.offset =
(port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
(addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
addr = offset;
offset = 0;
bytes_left = len;
@ -1926,10 +1940,14 @@ enum _ecore_status_t ecore_mcp_phy_sfp_read(struct ecore_hwfn *p_hwfn,
bytes_to_copy = OSAL_MIN_T(u32, bytes_left,
MAX_I2C_TRANSACTION_SIZE);
params.nvm_rd.buf = (u32 *)(p_buf + offset);
SET_FIELD(params.nvm_common.offset,
DRV_MB_PARAM_TRANSCEIVER_OFFSET, addr + offset);
SET_FIELD(params.nvm_common.offset,
DRV_MB_PARAM_TRANSCEIVER_SIZE, bytes_to_copy);
params.nvm_common.offset &=
(DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
params.nvm_common.offset |=
((addr + offset) <<
DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
params.nvm_common.offset |=
(bytes_to_copy << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
if ((params.nvm_common.resp & FW_MSG_CODE_MASK) ==
FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT) {
@ -1955,20 +1973,23 @@ enum _ecore_status_t ecore_mcp_phy_sfp_write(struct ecore_hwfn *p_hwfn,
u32 buf_idx, buf_size;
OSAL_MEMSET(&params, 0, sizeof(struct ecore_mcp_nvm_params));
SET_FIELD(params.nvm_common.offset,
DRV_MB_PARAM_TRANSCEIVER_PORT, port);
SET_FIELD(params.nvm_common.offset,
DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS, addr);
params.nvm_common.offset =
(port << DRV_MB_PARAM_TRANSCEIVER_PORT_SHIFT) |
(addr << DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_SHIFT);
params.type = ECORE_MCP_NVM_WR;
params.nvm_common.cmd = DRV_MSG_CODE_TRANSCEIVER_WRITE;
buf_idx = 0;
while (buf_idx < len) {
buf_size = OSAL_MIN_T(u32, (len - buf_idx),
MAX_I2C_TRANSACTION_SIZE);
SET_FIELD(params.nvm_common.offset,
DRV_MB_PARAM_TRANSCEIVER_OFFSET, offset + buf_idx);
SET_FIELD(params.nvm_common.offset,
DRV_MB_PARAM_TRANSCEIVER_SIZE, buf_size);
params.nvm_common.offset &=
(DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK |
DRV_MB_PARAM_TRANSCEIVER_PORT_MASK);
params.nvm_common.offset |=
((offset + buf_idx) <<
DRV_MB_PARAM_TRANSCEIVER_OFFSET_SHIFT);
params.nvm_common.offset |=
(buf_size << DRV_MB_PARAM_TRANSCEIVER_SIZE_SHIFT);
params.nvm_wr.buf_size = buf_size;
params.nvm_wr.buf = (u32 *)&p_buf[buf_idx];
rc = ecore_mcp_nvm_command(p_hwfn, p_ptt, &params);
@ -1992,11 +2013,14 @@ enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t rc = ECORE_SUCCESS;
u32 drv_mb_param = 0, rsp;
SET_FIELD(drv_mb_param, DRV_MB_PARAM_GPIO_NUMBER, gpio);
drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT);
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_READ,
drv_mb_param, &rsp, gpio_val);
if (rc != ECORE_SUCCESS)
return rc;
if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
return ECORE_UNKNOWN_ERROR;
@ -2010,12 +2034,15 @@ enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t rc = ECORE_SUCCESS;
u32 drv_mb_param = 0, param, rsp;
SET_FIELD(drv_mb_param, DRV_MB_PARAM_GPIO_NUMBER, gpio);
SET_FIELD(drv_mb_param, DRV_MB_PARAM_GPIO_VALUE, gpio_val);
drv_mb_param = (gpio << DRV_MB_PARAM_GPIO_NUMBER_SHIFT) |
(gpio_val << DRV_MB_PARAM_GPIO_VALUE_SHIFT);
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GPIO_WRITE,
drv_mb_param, &rsp, &param);
if (rc != ECORE_SUCCESS)
return rc;
if ((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_GPIO_OK)
return ECORE_UNKNOWN_ERROR;
@ -2143,78 +2170,6 @@ enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
return rc;
}
enum _ecore_status_t ecore_mcp_get_nvm_image(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
enum ecore_nvm_images image_id,
char *p_buffer, u16 buffer_len)
{
struct bist_nvm_image_att image_att;
/* enum nvm_image_type type; */ /* @DPDK */
u32 type;
u32 num_images, i;
enum _ecore_status_t rc;
OSAL_MEM_ZERO(p_buffer, buffer_len);
/* Translate image_id into MFW definitions */
switch (image_id) {
case ECORE_NVM_IMAGE_ISCSI_CFG:
/* @DPDK */
type = 0x1d; /* NVM_TYPE_ISCSI_CFG; */
break;
case ECORE_NVM_IMAGE_FCOE_CFG:
type = 0x1f; /* NVM_TYPE_FCOE_CFG; */
break;
default:
DP_NOTICE(p_hwfn, false, "Unknown request of image_id %08x\n",
image_id);
return ECORE_INVAL;
}
/* Learn number of images, then traverse and see if one fits */
rc = ecore_mcp_bist_nvm_test_get_num_images(p_hwfn, p_ptt,
&num_images);
if ((rc != ECORE_SUCCESS) || (!num_images))
return ECORE_INVAL;
for (i = 0; i < num_images; i++) {
rc = ecore_mcp_bist_nvm_test_get_image_att(p_hwfn, p_ptt,
&image_att, i);
if (rc != ECORE_SUCCESS)
return ECORE_INVAL;
if (type == image_att.image_type)
break;
}
if (i == num_images) {
DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
"Failed to find nvram image of type %08x\n",
image_id);
return ECORE_INVAL;
}
/* Validate sizes - both the image's and the supplied buffer's */
if (image_att.len <= 4) {
DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
"Image [%d] is too small - only %d bytes\n",
image_id, image_att.len);
return ECORE_INVAL;
}
/* Each NVM image is suffixed by CRC; Upper-layer has no need for it */
image_att.len -= 4;
if (image_att.len > buffer_len) {
DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
"Image [%d] is too big - %08x bytes where only %08x are available\n",
image_id, image_att.len, buffer_len);
return ECORE_NOMEM;
}
return ecore_mcp_nvm_read(p_hwfn->p_dev, image_att.nvm_start_addr,
(u8 *)p_buffer, image_att.len);
}
enum _ecore_status_t
ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
@ -2245,9 +2200,9 @@ ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
val = p_mfw_temp_info->sensor[i];
p_temp_sensor = &p_temp_info->sensors[i];
p_temp_sensor->sensor_location = (val & SENSOR_LOCATION_MASK) >>
SENSOR_LOCATION_SHIFT;
SENSOR_LOCATION_SHIFT;
p_temp_sensor->threshold_high = (val & THRESHOLD_HIGH_MASK) >>
THRESHOLD_HIGH_SHIFT;
THRESHOLD_HIGH_SHIFT;
p_temp_sensor->critical = (val & CRITICAL_TEMPERATURE_MASK) >>
CRITICAL_TEMPERATURE_SHIFT;
p_temp_sensor->current_temp = (val & CURRENT_TEMP_MASK) >>
@ -2297,12 +2252,12 @@ enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
0, &rsp, (u32 *)num_events);
}
#define ECORE_RESC_ALLOC_VERSION_MAJOR 1
#define ECORE_RESC_ALLOC_VERSION_MINOR 0
#define ECORE_RESC_ALLOC_VERSION \
((ECORE_RESC_ALLOC_VERSION_MAJOR << \
DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
(ECORE_RESC_ALLOC_VERSION_MINOR << \
#define ECORE_RESC_ALLOC_VERSION_MAJOR 1
#define ECORE_RESC_ALLOC_VERSION_MINOR 0
#define ECORE_RESC_ALLOC_VERSION \
((ECORE_RESC_ALLOC_VERSION_MAJOR << \
DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
(ECORE_RESC_ALLOC_VERSION_MINOR << \
DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
@ -2328,7 +2283,8 @@ enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
*p_mcp_param = mb_params.mcp_param;
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x, offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n",
"MFW resource_info: version 0x%x, res_id 0x%x, size 0x%x,"
" offset 0x%x, vf_size 0x%x, vf_offset 0x%x, flags 0x%x\n",
*p_mcp_param, p_resc_info->res_id, p_resc_info->size,
p_resc_info->offset, p_resc_info->vf_size,
p_resc_info->vf_offset, p_resc_info->flags);

29
drivers/net/qede/base/ecore_mcp.h
View File

@ -25,27 +25,24 @@
rel_pfid)
#define MCP_PF_ID(p_hwfn) MCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id)
/* TODO - this is only correct as long as only BB is supported, and
* no port-swapping is implemented; Afterwards we'll need to fix it.
*/
#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
((_p_hwfn)->p_dev->num_ports_in_engines * 2))
((_p_hwfn)->p_dev->num_ports_in_engines * \
ecore_device_num_engines((_p_hwfn)->p_dev)))
struct ecore_mcp_info {
osal_spinlock_t lock; /* Spinlock used for accessing MCP mailbox */
/* Flag to indicate whether sending a MFW mailbox is forbidden */
bool block_mb_sending;
u32 public_base; /* Address of the MCP public area */
u32 drv_mb_addr; /* Address of the driver mailbox */
u32 mfw_mb_addr; /* Address of the MFW mailbox */
u32 port_addr; /* Address of the port configuration (link) */
u16 drv_mb_seq; /* Current driver mailbox sequence */
u16 drv_pulse_seq; /* Current driver pulse sequence */
struct ecore_mcp_link_params link_input;
struct ecore_mcp_link_state link_output;
struct ecore_mcp_link_params link_input;
struct ecore_mcp_link_state link_output;
struct ecore_mcp_link_capabilities link_capabilities;
struct ecore_mcp_function_info func_info;
struct ecore_mcp_function_info func_info;
u8 *mfw_mb_cur;
u8 *mfw_mb_shadow;
@ -153,7 +150,8 @@ enum _ecore_status_t ecore_mcp_load_req(struct ecore_hwfn *p_hwfn,
* @param p_hwfn
* @param p_ptt
*/
void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
void ecore_mcp_read_mb(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
/**
* @brief Ack to mfw that driver finished FLR process for VFs
@ -211,7 +209,8 @@ enum _ecore_status_t ecore_mcp_nvm_wr_cmd(struct ecore_hwfn *p_hwfn,
u32 param,
u32 *o_mcp_resp,
u32 *o_mcp_param,
u32 i_txn_size, u32 *i_buf);
u32 i_txn_size,
u32 *i_buf);
/**
* @brief - Sends an NVM read command request to the MFW to get
@ -235,7 +234,8 @@ enum _ecore_status_t ecore_mcp_nvm_rd_cmd(struct ecore_hwfn *p_hwfn,
u32 param,
u32 *o_mcp_resp,
u32 *o_mcp_param,
u32 *o_txn_size, u32 *o_buf);
u32 *o_txn_size,
u32 *o_buf);
/**
* @brief indicates whether the MFW objects [under mcp_info] are accessible
@ -292,4 +292,9 @@ int __ecore_configure_pf_min_bandwidth(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t ecore_mcp_mask_parities(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 mask_parities);
enum _ecore_status_t ecore_mcp_get_resc_info(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct resource_info *p_resc_info,
u32 *p_mcp_resp, u32 *p_mcp_param);
#endif /* __ECORE_MCP_H__ */

81
drivers/net/qede/base/ecore_mcp_api.h
View File

@ -31,6 +31,8 @@ struct ecore_mcp_link_params {
struct ecore_mcp_link_capabilities {
u32 speed_capabilities;
bool default_speed_autoneg; /* In Mb/s */
u32 default_speed; /* In Mb/s */
};
struct ecore_mcp_link_state {
@ -115,10 +117,12 @@ struct ecore_mcp_nvm_params {
};
};
#ifndef __EXTRACT__LINUX__
enum ecore_nvm_images {
ECORE_NVM_IMAGE_ISCSI_CFG,
ECORE_NVM_IMAGE_FCOE_CFG,
};
#endif
struct ecore_mcp_drv_version {
u32 version;
@ -133,13 +137,39 @@ struct ecore_mcp_lan_stats {
#ifndef ECORE_PROTO_STATS
#define ECORE_PROTO_STATS
struct ecore_mcp_fcoe_stats {
u64 rx_pkts;
u64 tx_pkts;
u32 fcs_err;
u32 login_failure;
};
struct ecore_mcp_iscsi_stats {
u64 rx_pdus;
u64 tx_pdus;
u64 rx_bytes;
u64 tx_bytes;
};
struct ecore_mcp_rdma_stats {
u64 rx_pkts;
u64 tx_pkts;
u64 rx_bytes;
u64 tx_byts;
};
enum ecore_mcp_protocol_type {
ECORE_MCP_LAN_STATS,
ECORE_MCP_FCOE_STATS,
ECORE_MCP_ISCSI_STATS,
ECORE_MCP_RDMA_STATS
};
union ecore_mcp_protocol_stats {
struct ecore_mcp_lan_stats lan_stats;
struct ecore_mcp_fcoe_stats fcoe_stats;
struct ecore_mcp_iscsi_stats iscsi_stats;
struct ecore_mcp_rdma_stats rdma_stats;
};
#endif
@ -183,7 +213,7 @@ struct ecore_temperature_sensor {
u8 current_temp;
};
#define ECORE_MAX_NUM_OF_SENSORS 7
#define ECORE_MAX_NUM_OF_SENSORS 7
struct ecore_temperature_info {
u32 num_sensors;
struct ecore_temperature_sensor sensors[ECORE_MAX_NUM_OF_SENSORS];
@ -243,19 +273,20 @@ struct ecore_mcp_link_capabilities
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_mcp_set_link(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, bool b_up);
struct ecore_ptt *p_ptt,
bool b_up);
/**
* @brief Get the management firmware version value
*
* @param p_dev - ecore dev pointer
* @param p_hwfn
* @param p_ptt
* @param p_mfw_ver - mfw version value
* @param p_running_bundle_id - image id in nvram; Optional.
*
* @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
*/
enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_dev *p_dev,
enum _ecore_status_t ecore_mcp_get_mfw_ver(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *p_mfw_ver,
u32 *p_running_bundle_id);
@ -301,6 +332,7 @@ enum _ecore_status_t ecore_mcp_cmd(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
#ifndef LINUX_REMOVE
/**
* @brief - return the mcp function info of the hw function
*
@ -310,6 +342,7 @@ enum _ecore_status_t ecore_mcp_drain(struct ecore_hwfn *p_hwfn,
*/
const struct ecore_mcp_function_info
*ecore_mcp_get_function_info(struct ecore_hwfn *p_hwfn);
#endif
/**
* @brief - Function for reading/manipulating the nvram. Following are supported
@ -349,6 +382,7 @@ enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct ecore_mcp_nvm_params *params);
#ifndef LINUX_REMOVE
/**
* @brief - count number of function with a matching personality on engine.
*
@ -360,7 +394,9 @@ enum _ecore_status_t ecore_mcp_nvm_command(struct ecore_hwfn *p_hwfn,
* the bitsmasks.
*/
int ecore_mcp_get_personality_cnt(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u32 personalities);
struct ecore_ptt *p_ptt,
u32 personalities);
#endif
/**
* @brief Get the flash size value
@ -539,7 +575,8 @@ enum _ecore_status_t ecore_mcp_nvm_put_file_begin(struct ecore_dev *p_dev,
*
* @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
*/
enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev, u32 addr);
enum _ecore_status_t ecore_mcp_nvm_del_file(struct ecore_dev *p_dev,
u32 addr);
/**
* @brief Check latest response
@ -641,6 +678,7 @@ enum _ecore_status_t ecore_mcp_gpio_read(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t ecore_mcp_gpio_write(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 gpio, u16 gpio_val);
/**
* @brief Gpio get information
*
@ -686,14 +724,14 @@ enum _ecore_status_t ecore_mcp_bist_clock_test(struct ecore_hwfn *p_hwfn,
* @param p_hwfn - hw function
* @param p_ptt - PTT required for register access
* @param num_images - number of images if operation was
* successful. 0 if not.
* successful. 0 if not.
*
* @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
*/
enum _ecore_status_t
ecore_mcp_bist_nvm_test_get_num_images(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *num_images);
enum _ecore_status_t ecore_mcp_bist_nvm_test_get_num_images(
struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 *num_images);
/**
* @brief Bist nvm test - get image attributes by index
@ -705,11 +743,11 @@ ecore_mcp_bist_nvm_test_get_num_images(struct ecore_hwfn *p_hwfn,
*
* @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
*/
enum _ecore_status_t
ecore_mcp_bist_nvm_test_get_image_att(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct bist_nvm_image_att *p_image_att,
u32 image_index);
enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct bist_nvm_image_att *p_image_att,
u32 image_index);
/**
* @brief ecore_mcp_get_temperature_info - get the status of the temperature
@ -726,6 +764,7 @@ enum _ecore_status_t
ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct ecore_temperature_info *p_temp_info);
/**
* @brief Get MBA versions - get MBA sub images versions
*
@ -753,14 +792,4 @@ enum _ecore_status_t ecore_mcp_mem_ecc_events(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u64 *num_events);
/**
* @brief Sets whether a critical error notification from the MFW is acked, or
* is it being ignored and thus allowing the MFW crash dump.
*
* @param p_dev
* @param mdump_enable
*
*/
void ecore_mcp_mdump_enable(struct ecore_dev *p_dev, bool mdump_enable);
#endif

59
drivers/net/qede/base/ecore_proto_if.h
View File

@ -13,6 +13,8 @@
* PF parameters (according to personality/protocol)
*/
#define ECORE_ROCE_PROTOCOL_INDEX (3)
struct ecore_eth_pf_params {
/* The following parameters are used during HW-init
* and these parameters need to be passed as arguments
@ -21,8 +23,65 @@ struct ecore_eth_pf_params {
u16 num_cons;
};
/* Most of the the parameters below are described in the FW iSCSI / TCP HSI */
struct ecore_iscsi_pf_params {
u64 glbl_q_params_addr;
u64 bdq_pbl_base_addr[2];
u16 cq_num_entries;
u16 cmdq_num_entries;
u32 two_msl_timer;
u16 tx_sws_timer;
/* The following parameters are used during HW-init
* and these parameters need to be passed as arguments
* to update_pf_params routine invoked before slowpath start
*/
u16 num_cons;
u16 num_tasks;
/* The following parameters are used during protocol-init */
u16 half_way_close_timeout;
u16 bdq_xoff_threshold[2];
u16 bdq_xon_threshold[2];
u16 cmdq_xoff_threshold;
u16 cmdq_xon_threshold;
u16 rq_buffer_size;
u8 num_sq_pages_in_ring;
u8 num_r2tq_pages_in_ring;
u8 num_uhq_pages_in_ring;
u8 num_queues;
u8 log_page_size;
u8 rqe_log_size;
u8 max_fin_rt;
u8 gl_rq_pi;
u8 gl_cmd_pi;
u8 debug_mode;
u8 ll2_ooo_queue_id;
u8 ooo_enable;
u8 is_target;
u8 bdq_pbl_num_entries[2];
};
struct ecore_rdma_pf_params {
/* Supplied to ECORE during resource allocation (may affect the ILT and
* the doorbell BAR).
*/
u32 min_dpis; /* number of requested DPIs */
u32 num_mrs; /* number of requested memory regions*/
u32 num_qps; /* number of requested Queue Pairs */
u32 num_srqs; /* number of requested SRQ */
u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
u8 gl_pi; /* protocol index */
/* Will allocate rate limiters to be used with QPs */
u8 enable_dcqcn;
};
struct ecore_pf_params {
struct ecore_eth_pf_params eth_pf_params;
struct ecore_iscsi_pf_params iscsi_pf_params;
struct ecore_rdma_pf_params rdma_pf_params;
};
#endif

639
drivers/net/qede/base/ecore_rt_defs.h
View File

@ -49,6 +49,10 @@
#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
@ -97,350 +101,353 @@
#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6704
#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28704
#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705
#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706
#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707
#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708
#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709
#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710
#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711
#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712
#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713
#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714
#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28705
#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28706
#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28707
#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28708
#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28709
#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28710
#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28711
#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28712
#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28713
#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28714
#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28715
#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28716
#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130
#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29132
#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512
#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29642
#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29643
#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29644
#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29645
#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29646
#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29647
#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29648
#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29649
#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29650
#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29651
#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29652
#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29653
#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29654
#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29655
#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29656
#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29657
#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29658
#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29659
#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29660
#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29661
#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29662
#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29663
#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29664
#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29665
#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29666
#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29667
#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29668
#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29669
#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29670
#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29671
#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29672
#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29673
#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29674
#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29675
#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29676
#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29677
#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29678
#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29679
#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29680
#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29681
#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29682
#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29683
#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29684
#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29685
#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29686
#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29687
#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29688
#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29689
#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29690
#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29691
#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29692
#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29693
#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29694
#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29695
#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29696
#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29697
#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29698
#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29699
#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29700
#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29701
#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29702
#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29703
#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29704
#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29705
#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29706
#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29707
#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29708
#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29709
#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29644
#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29645
#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29646
#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29647
#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29648
#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29649
#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29650
#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29651
#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29652
#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29653
#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29654
#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29655
#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29656
#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29657
#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29658
#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29659
#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29660
#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29661
#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29662
#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29663
#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29664
#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29665
#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29666
#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29667
#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29668
#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29669
#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29670
#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29671
#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29672
#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29673
#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29674
#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29675
#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29676
#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29677
#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29678
#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29679
#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29680
#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29681
#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29682
#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29683
#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29684
#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29685
#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29686
#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29687
#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29688
#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29689
#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29690
#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29691
#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29692
#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29693
#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29694
#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29695
#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29696
#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29697
#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29698
#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29699
#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29700
#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29701
#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29702
#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29703
#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29704
#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29705
#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29706
#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29707
#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29708
#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29709
#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29710
#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29711
#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
#define QM_REG_VOQCRDLINE_RT_OFFSET 29837
#define QM_REG_VOQCRDLINE_RT_OFFSET 29839
#define QM_REG_VOQCRDLINE_RT_SIZE 20
#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29857
#define QM_REG_VOQINITCRDLINE_RT_OFFSET 29859
#define QM_REG_VOQINITCRDLINE_RT_SIZE 20
#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29877
#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29878
#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29879
#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29880
#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29881
#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29882
#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29883
#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29884
#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29885
#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29886
#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29887
#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29888
#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29889
#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29890
#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29891
#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29892
#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29893
#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29894
#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29895
#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29896
#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29897
#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29898
#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29899
#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29900
#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29901
#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29902
#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29903
#define QM_REG_PQTX2PF_0_RT_OFFSET 29904
#define QM_REG_PQTX2PF_1_RT_OFFSET 29905
#define QM_REG_PQTX2PF_2_RT_OFFSET 29906
#define QM_REG_PQTX2PF_3_RT_OFFSET 29907
#define QM_REG_PQTX2PF_4_RT_OFFSET 29908
#define QM_REG_PQTX2PF_5_RT_OFFSET 29909
#define QM_REG_PQTX2PF_6_RT_OFFSET 29910
#define QM_REG_PQTX2PF_7_RT_OFFSET 29911
#define QM_REG_PQTX2PF_8_RT_OFFSET 29912
#define QM_REG_PQTX2PF_9_RT_OFFSET 29913
#define QM_REG_PQTX2PF_10_RT_OFFSET 29914
#define QM_REG_PQTX2PF_11_RT_OFFSET 29915
#define QM_REG_PQTX2PF_12_RT_OFFSET 29916
#define QM_REG_PQTX2PF_13_RT_OFFSET 29917
#define QM_REG_PQTX2PF_14_RT_OFFSET 29918
#define QM_REG_PQTX2PF_15_RT_OFFSET 29919
#define QM_REG_PQTX2PF_16_RT_OFFSET 29920
#define QM_REG_PQTX2PF_17_RT_OFFSET 29921
#define QM_REG_PQTX2PF_18_RT_OFFSET 29922
#define QM_REG_PQTX2PF_19_RT_OFFSET 29923
#define QM_REG_PQTX2PF_20_RT_OFFSET 29924
#define QM_REG_PQTX2PF_21_RT_OFFSET 29925
#define QM_REG_PQTX2PF_22_RT_OFFSET 29926
#define QM_REG_PQTX2PF_23_RT_OFFSET 29927
#define QM_REG_PQTX2PF_24_RT_OFFSET 29928
#define QM_REG_PQTX2PF_25_RT_OFFSET 29929
#define QM_REG_PQTX2PF_26_RT_OFFSET 29930
#define QM_REG_PQTX2PF_27_RT_OFFSET 29931
#define QM_REG_PQTX2PF_28_RT_OFFSET 29932
#define QM_REG_PQTX2PF_29_RT_OFFSET 29933
#define QM_REG_PQTX2PF_30_RT_OFFSET 29934
#define QM_REG_PQTX2PF_31_RT_OFFSET 29935
#define QM_REG_PQTX2PF_32_RT_OFFSET 29936
#define QM_REG_PQTX2PF_33_RT_OFFSET 29937
#define QM_REG_PQTX2PF_34_RT_OFFSET 29938
#define QM_REG_PQTX2PF_35_RT_OFFSET 29939
#define QM_REG_PQTX2PF_36_RT_OFFSET 29940
#define QM_REG_PQTX2PF_37_RT_OFFSET 29941
#define QM_REG_PQTX2PF_38_RT_OFFSET 29942
#define QM_REG_PQTX2PF_39_RT_OFFSET 29943
#define QM_REG_PQTX2PF_40_RT_OFFSET 29944
#define QM_REG_PQTX2PF_41_RT_OFFSET 29945
#define QM_REG_PQTX2PF_42_RT_OFFSET 29946
#define QM_REG_PQTX2PF_43_RT_OFFSET 29947
#define QM_REG_PQTX2PF_44_RT_OFFSET 29948
#define QM_REG_PQTX2PF_45_RT_OFFSET 29949
#define QM_REG_PQTX2PF_46_RT_OFFSET 29950
#define QM_REG_PQTX2PF_47_RT_OFFSET 29951
#define QM_REG_PQTX2PF_48_RT_OFFSET 29952
#define QM_REG_PQTX2PF_49_RT_OFFSET 29953
#define QM_REG_PQTX2PF_50_RT_OFFSET 29954
#define QM_REG_PQTX2PF_51_RT_OFFSET 29955
#define QM_REG_PQTX2PF_52_RT_OFFSET 29956
#define QM_REG_PQTX2PF_53_RT_OFFSET 29957
#define QM_REG_PQTX2PF_54_RT_OFFSET 29958
#define QM_REG_PQTX2PF_55_RT_OFFSET 29959
#define QM_REG_PQTX2PF_56_RT_OFFSET 29960
#define QM_REG_PQTX2PF_57_RT_OFFSET 29961
#define QM_REG_PQTX2PF_58_RT_OFFSET 29962
#define QM_REG_PQTX2PF_59_RT_OFFSET 29963
#define QM_REG_PQTX2PF_60_RT_OFFSET 29964
#define QM_REG_PQTX2PF_61_RT_OFFSET 29965
#define QM_REG_PQTX2PF_62_RT_OFFSET 29966
#define QM_REG_PQTX2PF_63_RT_OFFSET 29967
#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29968
#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29969
#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29970
#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29971
#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29972
#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29973
#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29974
#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29975
#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29976
#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29977
#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29978
#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29979
#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29980
#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29981
#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29982
#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29983
#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29984
#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29985
#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29986
#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29987
#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29988
#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29989
#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29990
#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29991
#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29992
#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29993
#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29994
#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29995
#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29996
#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29879
#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29880
#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29881
#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29882
#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29883
#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29884
#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29885
#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29886
#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29887
#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29888
#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29889
#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29890
#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29891
#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29892
#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29893
#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29894
#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29895
#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29896
#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29897
#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29898
#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29899
#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29900
#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29901
#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29902
#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29903
#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29904
#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29905
#define QM_REG_PQTX2PF_0_RT_OFFSET 29906
#define QM_REG_PQTX2PF_1_RT_OFFSET 29907
#define QM_REG_PQTX2PF_2_RT_OFFSET 29908
#define QM_REG_PQTX2PF_3_RT_OFFSET 29909
#define QM_REG_PQTX2PF_4_RT_OFFSET 29910
#define QM_REG_PQTX2PF_5_RT_OFFSET 29911
#define QM_REG_PQTX2PF_6_RT_OFFSET 29912
#define QM_REG_PQTX2PF_7_RT_OFFSET 29913
#define QM_REG_PQTX2PF_8_RT_OFFSET 29914
#define QM_REG_PQTX2PF_9_RT_OFFSET 29915
#define QM_REG_PQTX2PF_10_RT_OFFSET 29916
#define QM_REG_PQTX2PF_11_RT_OFFSET 29917
#define QM_REG_PQTX2PF_12_RT_OFFSET 29918
#define QM_REG_PQTX2PF_13_RT_OFFSET 29919
#define QM_REG_PQTX2PF_14_RT_OFFSET 29920
#define QM_REG_PQTX2PF_15_RT_OFFSET 29921
#define QM_REG_PQTX2PF_16_RT_OFFSET 29922
#define QM_REG_PQTX2PF_17_RT_OFFSET 29923
#define QM_REG_PQTX2PF_18_RT_OFFSET 29924
#define QM_REG_PQTX2PF_19_RT_OFFSET 29925
#define QM_REG_PQTX2PF_20_RT_OFFSET 29926
#define QM_REG_PQTX2PF_21_RT_OFFSET 29927
#define QM_REG_PQTX2PF_22_RT_OFFSET 29928
#define QM_REG_PQTX2PF_23_RT_OFFSET 29929
#define QM_REG_PQTX2PF_24_RT_OFFSET 29930
#define QM_REG_PQTX2PF_25_RT_OFFSET 29931
#define QM_REG_PQTX2PF_26_RT_OFFSET 29932
#define QM_REG_PQTX2PF_27_RT_OFFSET 29933
#define QM_REG_PQTX2PF_28_RT_OFFSET 29934
#define QM_REG_PQTX2PF_29_RT_OFFSET 29935
#define QM_REG_PQTX2PF_30_RT_OFFSET 29936
#define QM_REG_PQTX2PF_31_RT_OFFSET 29937
#define QM_REG_PQTX2PF_32_RT_OFFSET 29938
#define QM_REG_PQTX2PF_33_RT_OFFSET 29939
#define QM_REG_PQTX2PF_34_RT_OFFSET 29940
#define QM_REG_PQTX2PF_35_RT_OFFSET 29941
#define QM_REG_PQTX2PF_36_RT_OFFSET 29942
#define QM_REG_PQTX2PF_37_RT_OFFSET 29943
#define QM_REG_PQTX2PF_38_RT_OFFSET 29944
#define QM_REG_PQTX2PF_39_RT_OFFSET 29945
#define QM_REG_PQTX2PF_40_RT_OFFSET 29946
#define QM_REG_PQTX2PF_41_RT_OFFSET 29947
#define QM_REG_PQTX2PF_42_RT_OFFSET 29948
#define QM_REG_PQTX2PF_43_RT_OFFSET 29949
#define QM_REG_PQTX2PF_44_RT_OFFSET 29950
#define QM_REG_PQTX2PF_45_RT_OFFSET 29951
#define QM_REG_PQTX2PF_46_RT_OFFSET 29952
#define QM_REG_PQTX2PF_47_RT_OFFSET 29953
#define QM_REG_PQTX2PF_48_RT_OFFSET 29954
#define QM_REG_PQTX2PF_49_RT_OFFSET 29955
#define QM_REG_PQTX2PF_50_RT_OFFSET 29956
#define QM_REG_PQTX2PF_51_RT_OFFSET 29957
#define QM_REG_PQTX2PF_52_RT_OFFSET 29958
#define QM_REG_PQTX2PF_53_RT_OFFSET 29959
#define QM_REG_PQTX2PF_54_RT_OFFSET 29960
#define QM_REG_PQTX2PF_55_RT_OFFSET 29961
#define QM_REG_PQTX2PF_56_RT_OFFSET 29962
#define QM_REG_PQTX2PF_57_RT_OFFSET 29963
#define QM_REG_PQTX2PF_58_RT_OFFSET 29964
#define QM_REG_PQTX2PF_59_RT_OFFSET 29965
#define QM_REG_PQTX2PF_60_RT_OFFSET 29966
#define QM_REG_PQTX2PF_61_RT_OFFSET 29967
#define QM_REG_PQTX2PF_62_RT_OFFSET 29968
#define QM_REG_PQTX2PF_63_RT_OFFSET 29969
#define QM_REG_PQOTHER2PF_0_RT_OFFSET 29970
#define QM_REG_PQOTHER2PF_1_RT_OFFSET 29971
#define QM_REG_PQOTHER2PF_2_RT_OFFSET 29972
#define QM_REG_PQOTHER2PF_3_RT_OFFSET 29973
#define QM_REG_PQOTHER2PF_4_RT_OFFSET 29974
#define QM_REG_PQOTHER2PF_5_RT_OFFSET 29975
#define QM_REG_PQOTHER2PF_6_RT_OFFSET 29976
#define QM_REG_PQOTHER2PF_7_RT_OFFSET 29977
#define QM_REG_PQOTHER2PF_8_RT_OFFSET 29978
#define QM_REG_PQOTHER2PF_9_RT_OFFSET 29979
#define QM_REG_PQOTHER2PF_10_RT_OFFSET 29980
#define QM_REG_PQOTHER2PF_11_RT_OFFSET 29981
#define QM_REG_PQOTHER2PF_12_RT_OFFSET 29982
#define QM_REG_PQOTHER2PF_13_RT_OFFSET 29983
#define QM_REG_PQOTHER2PF_14_RT_OFFSET 29984
#define QM_REG_PQOTHER2PF_15_RT_OFFSET 29985
#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29986
#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29987
#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29988
#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29989
#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29990
#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29991
#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29992
#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29993
#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29994
#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29995
#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29996
#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29997
#define QM_REG_RLGLBLINCVAL_RT_OFFSET 29998
#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30252
#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30254
#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
#define QM_REG_RLGLBLCRD_RT_OFFSET 30508
#define QM_REG_RLGLBLCRD_RT_OFFSET 30510
#define QM_REG_RLGLBLCRD_RT_SIZE 256
#define QM_REG_RLGLBLENABLE_RT_OFFSET 30764
#define QM_REG_RLPFPERIOD_RT_OFFSET 30765
#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30766
#define QM_REG_RLPFINCVAL_RT_OFFSET 30767
#define QM_REG_RLGLBLENABLE_RT_OFFSET 30766
#define QM_REG_RLPFPERIOD_RT_OFFSET 30767
#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30768
#define QM_REG_RLPFINCVAL_RT_OFFSET 30769
#define QM_REG_RLPFINCVAL_RT_SIZE 16
#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30783
#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30785
#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
#define QM_REG_RLPFCRD_RT_OFFSET 30799
#define QM_REG_RLPFCRD_RT_OFFSET 30801
#define QM_REG_RLPFCRD_RT_SIZE 16
#define QM_REG_RLPFENABLE_RT_OFFSET 30815
#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30816
#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30817
#define QM_REG_RLPFENABLE_RT_OFFSET 30817
#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30818
#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30819
#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30833
#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30835
#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
#define QM_REG_WFQPFCRD_RT_OFFSET 30849
#define QM_REG_WFQPFCRD_RT_OFFSET 30851
#define QM_REG_WFQPFCRD_RT_SIZE 160
#define QM_REG_WFQPFENABLE_RT_OFFSET 31009
#define QM_REG_WFQVPENABLE_RT_OFFSET 31010
#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31011
#define QM_REG_WFQPFENABLE_RT_OFFSET 31011
#define QM_REG_WFQVPENABLE_RT_OFFSET 31012
#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31013
#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
#define QM_REG_TXPQMAP_RT_OFFSET 31523
#define QM_REG_TXPQMAP_RT_OFFSET 31525
#define QM_REG_TXPQMAP_RT_SIZE 512
#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32035
#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32037
#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
#define QM_REG_WFQVPCRD_RT_OFFSET 32547
#define QM_REG_WFQVPCRD_RT_OFFSET 32549
#define QM_REG_WFQVPCRD_RT_SIZE 512
#define QM_REG_WFQVPMAP_RT_OFFSET 33059
#define QM_REG_WFQVPMAP_RT_OFFSET 33061
#define QM_REG_WFQVPMAP_RT_SIZE 512
#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33571
#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33573
#define QM_REG_WFQPFCRD_MSB_RT_SIZE 160
#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33731
#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33732
#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33733
#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33734
#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33735
#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33736
#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33737
#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33738
#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 33733
#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 33734
#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 33735
#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 33736
#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 33737
#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 33738
#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 33739
#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 33740
#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33742
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 33744
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33746
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 33748
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33750
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33751
#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 33752
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 33753
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33783
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 33785
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33799
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 33801
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33815
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 33817
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33831
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 33833
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33847
#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33848
#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33849
#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33850
#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33851
#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33852
#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33853
#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33854
#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33855
#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33856
#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33857
#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33858
#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33859
#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33860
#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33861
#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33862
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33863
#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33864
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33865
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33866
#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33867
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33868
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33869
#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33870
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33871
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33872
#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33873
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33874
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33875
#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33876
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33877
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33878
#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33879
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33880
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33881
#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33882
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33883
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33884
#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33885
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33886
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33887
#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33888
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33889
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33890
#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33891
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33892
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33893
#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33894
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33895
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33896
#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33897
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33898
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33899
#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33900
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33901
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33902
#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33903
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33904
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33905
#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33906
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33907
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33908
#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33909
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33910
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33911
#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33912
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33913
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33914
#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33915
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33916
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33917
#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33918
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33919
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33920
#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33921
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33922
#define XCM_REG_CON_PHY_Q3_RT_OFFSET 33923
#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 33849
#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 33850
#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 33851
#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 33852
#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 33853
#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 33854
#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 33855
#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 33856
#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 33857
#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 33858
#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 33859
#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 33860
#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 33861
#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 33862
#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 33863
#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 33864
#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 33865
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 33866
#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 33867
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 33868
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 33869
#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 33870
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 33871
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 33872
#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 33873
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 33874
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 33875
#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 33876
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 33877
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 33878
#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 33879
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 33880
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 33881
#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 33882
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 33883
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 33884
#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 33885
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 33886
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 33887
#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 33888
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 33889
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 33890
#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 33891
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 33892
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 33893
#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 33894
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 33895
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 33896
#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 33897
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 33898
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 33899
#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 33900
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 33901
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 33902
#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 33903
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 33904
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 33905
#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 33906
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 33907
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 33908
#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 33909
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 33910
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 33911
#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 33912
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 33913
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 33914
#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 33915
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 33916
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 33917
#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 33918
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 33919
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 33920
#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 33921
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 33922
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 33923
#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 33924
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 33925
#define XCM_REG_CON_PHY_Q3_RT_OFFSET 33926
#define RUNTIME_ARRAY_SIZE 33924
#define RUNTIME_ARRAY_SIZE 33927
#endif /* __RT_DEFS_H__ */

85
drivers/net/qede/base/ecore_sp_commands.c
View File

@ -21,6 +21,7 @@
#include "ecore_int.h"
#include "ecore_hw.h"
#include "ecore_dcbx.h"
#include "ecore_sriov.h"
enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
struct ecore_spq_entry **pp_ent,
@ -32,6 +33,9 @@ enum _ecore_status_t ecore_sp_init_request(struct ecore_hwfn *p_hwfn,
struct ecore_spq_entry *p_ent = OSAL_NULL;
enum _ecore_status_t rc = ECORE_NOTIMPL;
if (!pp_ent)
return ECORE_INVAL;
/* Get an SPQ entry */
rc = ecore_spq_get_entry(p_hwfn, pp_ent);
if (rc != ECORE_SUCCESS)
@ -95,6 +99,8 @@ static enum tunnel_clss ecore_tunn_get_clss_type(u8 type)
return TUNNEL_CLSS_INNER_MAC_VLAN;
case ECORE_TUNN_CLSS_INNER_MAC_VNI:
return TUNNEL_CLSS_INNER_MAC_VNI;
case ECORE_TUNN_CLSS_MAC_VLAN_DUAL_STAGE:
return TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE;
default:
return TUNNEL_CLSS_MAC_VLAN;
}
@ -351,7 +357,6 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
p_ramrod->event_ring_sb_id = OSAL_CPU_TO_LE16(sb);
p_ramrod->event_ring_sb_index = sb_index;
p_ramrod->path_id = ECORE_PATH_ID(p_hwfn);
p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
/* For easier debugging */
p_ramrod->dont_log_ramrods = 0;
@ -370,6 +375,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
"Unsupported MF mode, init as DEFAULT\n");
p_ramrod->mf_mode = MF_NPAR;
}
p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
/* Place EQ address in RAMROD */
DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
@ -395,8 +401,17 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
p_ramrod->personality = PERSONALITY_ETH;
}
p_ramrod->base_vf_id = (u8)p_hwfn->hw_info.first_vf_in_pf;
p_ramrod->num_vfs = (u8)p_hwfn->p_dev->sriov_info.total_vfs;
if (p_hwfn->p_dev->p_iov_info) {
struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
p_ramrod->base_vf_id = (u8)p_iov->first_vf_in_pf;
p_ramrod->num_vfs = (u8)p_iov->total_vfs;
}
/* @@@TBD - update also the "ROCE_VER_KEY" entries when the FW RoCE HSI
* version is available.
*/
p_ramrod->hsi_fp_ver.major_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MAJOR;
p_ramrod->hsi_fp_ver.minor_ver_arr[ETH_VER_KEY] = ETH_HSI_VER_MINOR;
DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
"Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
@ -437,6 +452,49 @@ enum _ecore_status_t ecore_sp_pf_update(struct ecore_hwfn *p_hwfn)
return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
}
enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
struct ecore_rl_update_params *params)
{
struct ecore_spq_entry *p_ent = OSAL_NULL;
enum _ecore_status_t rc = ECORE_NOTIMPL;
struct rl_update_ramrod_data *rl_update;
struct ecore_sp_init_data init_data;
/* Get SPQ entry */
OSAL_MEMSET(&init_data, 0, sizeof(init_data));
init_data.cid = ecore_spq_get_cid(p_hwfn);
init_data.opaque_fid = p_hwfn->hw_info.opaque_fid;
init_data.comp_mode = ECORE_SPQ_MODE_EBLOCK;
rc = ecore_sp_init_request(p_hwfn, &p_ent,
COMMON_RAMROD_RL_UPDATE, PROTOCOLID_COMMON,
&init_data);
if (rc != ECORE_SUCCESS)
return rc;
rl_update = &p_ent->ramrod.rl_update;
rl_update->qcn_update_param_flg = params->qcn_update_param_flg;
rl_update->dcqcn_update_param_flg = params->dcqcn_update_param_flg;
rl_update->rl_init_flg = params->rl_init_flg;
rl_update->rl_start_flg = params->rl_start_flg;
rl_update->rl_stop_flg = params->rl_stop_flg;
rl_update->rl_id_first = params->rl_id_first;
rl_update->rl_id_last = params->rl_id_last;
rl_update->rl_dc_qcn_flg = params->rl_dc_qcn_flg;
rl_update->rl_bc_rate = OSAL_CPU_TO_LE32(params->rl_bc_rate);
rl_update->rl_max_rate = OSAL_CPU_TO_LE16(params->rl_max_rate);
rl_update->rl_r_ai = OSAL_CPU_TO_LE16(params->rl_r_ai);
rl_update->rl_r_hai = OSAL_CPU_TO_LE16(params->rl_r_hai);
rl_update->dcqcn_g = OSAL_CPU_TO_LE16(params->dcqcn_g);
rl_update->dcqcn_k_us = OSAL_CPU_TO_LE32(params->dcqcn_k_us);
rl_update->dcqcn_timeuot_us = OSAL_CPU_TO_LE32(
params->dcqcn_timeuot_us);
rl_update->qcn_timeuot_us = OSAL_CPU_TO_LE32(params->qcn_timeuot_us);
return ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
}
/* Set pf update ramrod command params */
enum _ecore_status_t
ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,
@ -465,19 +523,18 @@ ecore_sp_pf_update_tunn_cfg(struct ecore_hwfn *p_hwfn,
&p_ent->ramrod.pf_update.tunnel_config);
rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);
if (rc != ECORE_SUCCESS)
return rc;
if ((rc == ECORE_SUCCESS) && p_tunn) {
if (p_tunn->update_vxlan_udp_port)
ecore_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
p_tunn->vxlan_udp_port);
if (p_tunn->update_geneve_udp_port)
ecore_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
p_tunn->geneve_udp_port);
if (p_tunn->update_vxlan_udp_port)
ecore_set_vxlan_dest_port(p_hwfn, p_hwfn->p_main_ptt,
p_tunn->vxlan_udp_port);
if (p_tunn->update_geneve_udp_port)
ecore_set_geneve_dest_port(p_hwfn, p_hwfn->p_main_ptt,
p_tunn->geneve_udp_port);
ecore_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt,
p_tunn->tunn_mode);
p_hwfn->p_dev->tunn_mode = p_tunn->tunn_mode;
}
ecore_set_hw_tunn_mode(p_hwfn, p_hwfn->p_main_ptt, p_tunn->tunn_mode);
p_hwfn->p_dev->tunn_mode = p_tunn->tunn_mode;
return rc;
}

30
drivers/net/qede/base/ecore_sp_commands.h
View File

@ -134,4 +134,34 @@ enum _ecore_status_t ecore_sp_pf_stop(struct ecore_hwfn *p_hwfn);
enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn);
struct ecore_rl_update_params {
u8 qcn_update_param_flg;
u8 dcqcn_update_param_flg;
u8 rl_init_flg;
u8 rl_start_flg;
u8 rl_stop_flg;
u8 rl_id_first;
u8 rl_id_last;
u8 rl_dc_qcn_flg; /* If set, RL will used for DCQCN */
u32 rl_bc_rate; /* Byte Counter Limit */
u16 rl_max_rate; /* Maximum rate in 1.6 Mbps resolution */
u16 rl_r_ai; /* Active increase rate */
u16 rl_r_hai; /* Hyper active increase rate */
u16 dcqcn_g; /* DCQCN Alpha update gain in 1/64K resolution */
u32 dcqcn_k_us; /* DCQCN Alpha update interval */
u32 dcqcn_timeuot_us;
u32 qcn_timeuot_us;
};
/**
* @brief ecore_sp_rl_update - Update rate limiters
*
* @param p_hwfn
* @param params
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_sp_rl_update(struct ecore_hwfn *p_hwfn,
struct ecore_rl_update_params *params);
#endif /*__ECORE_SP_COMMANDS_H__*/

171
drivers/net/qede/base/ecore_spq.c
View File

@ -27,7 +27,11 @@
***************************************************************************/
#define SPQ_HIGH_PRI_RESERVE_DEFAULT (1)
#define SPQ_BLOCK_SLEEP_LENGTH (1000)
#define SPQ_BLOCK_DELAY_MAX_ITER (10)
#define SPQ_BLOCK_DELAY_US (10)
#define SPQ_BLOCK_SLEEP_MAX_ITER (1000)
#define SPQ_BLOCK_SLEEP_MS (5)
/***************************************************************************
* Blocking Imp. (BLOCK/EBLOCK mode)
@ -48,53 +52,76 @@ static void ecore_spq_blocking_cb(struct ecore_hwfn *p_hwfn,
OSAL_SMP_WMB(p_hwfn->p_dev);
}
static enum _ecore_status_t ecore_spq_block(struct ecore_hwfn *p_hwfn,
static enum _ecore_status_t __ecore_spq_block(struct ecore_hwfn *p_hwfn,
struct ecore_spq_entry *p_ent,
u8 *p_fw_ret)
u8 *p_fw_ret,
bool sleep_between_iter)
{
int sleep_count = SPQ_BLOCK_SLEEP_LENGTH;
struct ecore_spq_comp_done *comp_done;
enum _ecore_status_t rc;
u32 iter_cnt;
comp_done = (struct ecore_spq_comp_done *)p_ent->comp_cb.cookie;
while (sleep_count) {
iter_cnt = sleep_between_iter ? SPQ_BLOCK_SLEEP_MAX_ITER
: SPQ_BLOCK_DELAY_MAX_ITER;
while (iter_cnt--) {
OSAL_POLL_MODE_DPC(p_hwfn);
/* validate we receive completion update */
OSAL_SMP_RMB(p_hwfn->p_dev);
if (comp_done->done == 1) {
if (p_fw_ret)
*p_fw_ret = comp_done->fw_return_code;
return ECORE_SUCCESS;
}
OSAL_MSLEEP(5);
sleep_count--;
if (sleep_between_iter)
OSAL_MSLEEP(SPQ_BLOCK_SLEEP_MS);
else
OSAL_UDELAY(SPQ_BLOCK_DELAY_US);
}
return ECORE_TIMEOUT;
}
static enum _ecore_status_t ecore_spq_block(struct ecore_hwfn *p_hwfn,
struct ecore_spq_entry *p_ent,
u8 *p_fw_ret, bool skip_quick_poll)
{
struct ecore_spq_comp_done *comp_done;
enum _ecore_status_t rc;
/* A relatively short polling period w/o sleeping, to allow the FW to
* complete the ramrod and thus possibly to avoid the following sleeps.
*/
if (!skip_quick_poll) {
rc = __ecore_spq_block(p_hwfn, p_ent, p_fw_ret, false);
if (rc == ECORE_SUCCESS)
return ECORE_SUCCESS;
}
/* Move to polling with a sleeping period between iterations */
rc = __ecore_spq_block(p_hwfn, p_ent, p_fw_ret, true);
if (rc == ECORE_SUCCESS)
return ECORE_SUCCESS;
DP_INFO(p_hwfn, "Ramrod is stuck, requesting MCP drain\n");
rc = ecore_mcp_drain(p_hwfn, p_hwfn->p_main_ptt);
if (rc != ECORE_SUCCESS)
if (rc != ECORE_SUCCESS) {
DP_NOTICE(p_hwfn, true, "MCP drain failed\n");
/* Retry after drain */
sleep_count = SPQ_BLOCK_SLEEP_LENGTH;
while (sleep_count) {
/* validate we receive completion update */
OSAL_SMP_RMB(p_hwfn->p_dev);
if (comp_done->done == 1) {
if (p_fw_ret)
*p_fw_ret = comp_done->fw_return_code;
return ECORE_SUCCESS;
}
OSAL_MSLEEP(5);
sleep_count--;
goto err;
}
/* Retry after drain */
rc = __ecore_spq_block(p_hwfn, p_ent, p_fw_ret, true);
if (rc == ECORE_SUCCESS)
return ECORE_SUCCESS;
comp_done = (struct ecore_spq_comp_done *)p_ent->comp_cb.cookie;
if (comp_done->done == 1) {
if (p_fw_ret)
*p_fw_ret = comp_done->fw_return_code;
return ECORE_SUCCESS;
}
err:
DP_NOTICE(p_hwfn, true,
"Ramrod is stuck [CID %08x cmd %02x proto %02x echo %04x]\n",
OSAL_LE32_TO_CPU(p_ent->elem.hdr.cid),
@ -187,10 +214,8 @@ static void ecore_spq_hw_initialize(struct ecore_hwfn *p_hwfn,
p_cxt->xstorm_st_context.spq_base_hi =
DMA_HI_LE(p_spq->chain.p_phys_addr);
p_cxt->xstorm_st_context.consolid_base_addr.lo =
DMA_LO_LE(p_hwfn->p_consq->chain.p_phys_addr);
p_cxt->xstorm_st_context.consolid_base_addr.hi =
DMA_HI_LE(p_hwfn->p_consq->chain.p_phys_addr);
DMA_REGPAIR_LE(p_cxt->xstorm_st_context.consolid_base_addr,
p_hwfn->p_consq->chain.p_phys_addr);
}
static enum _ecore_status_t ecore_spq_hw_post(struct ecore_hwfn *p_hwfn,
@ -218,19 +243,15 @@ static enum _ecore_status_t ecore_spq_hw_post(struct ecore_hwfn *p_hwfn,
SET_FIELD(db.params, CORE_DB_DATA_AGG_VAL_SEL,
DQ_XCM_CORE_SPQ_PROD_CMD);
db.agg_flags = DQ_XCM_CORE_DQ_CF_CMD;
/* validate producer is up to-date */
OSAL_RMB(p_hwfn->p_dev);
db.spq_prod = OSAL_CPU_TO_LE16(ecore_chain_get_prod_idx(p_chain));
/* do not reorder */
OSAL_BARRIER(p_hwfn->p_dev);
/* make sure the SPQE is updated before the doorbell */
OSAL_WMB(p_hwfn->p_dev);
DOORBELL(p_hwfn, DB_ADDR(p_spq->cid, DQ_DEMS_LEGACY), *(u32 *)&db);
/* make sure doorbell is rang */
OSAL_MMIOWB(p_hwfn->p_dev);
OSAL_WMB(p_hwfn->p_dev);
DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
"Doorbelled [0x%08x, CID 0x%08x] with Flags: %02x"
@ -305,10 +326,11 @@ enum _ecore_status_t ecore_eq_completion(struct ecore_hwfn *p_hwfn,
}
DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
"op %x prot %x res0 %x echo %x "
"fwret %x flags %x\n", p_eqe->opcode,
"op %x prot %x res0 %x echo %x fwret %x flags %x\n",
p_eqe->opcode, /* Event Opcode */
p_eqe->protocol_id, /* Event Protocol ID */
p_eqe->reserved0, /* Reserved */
/* Echo value from ramrod data on the host */
OSAL_LE16_TO_CPU(p_eqe->echo),
p_eqe->fw_return_code, /* FW return code for SP
* ramrods
@ -338,7 +360,7 @@ struct ecore_eq *ecore_eq_alloc(struct ecore_hwfn *p_hwfn, u16 num_elem)
struct ecore_eq *p_eq;
/* Allocate EQ struct */
p_eq = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(struct ecore_eq));
p_eq = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_eq));
if (!p_eq) {
DP_NOTICE(p_hwfn, true,
"Failed to allocate `struct ecore_eq'\n");
@ -436,8 +458,7 @@ void ecore_spq_setup(struct ecore_hwfn *p_hwfn)
capacity = ecore_chain_get_capacity(&p_spq->chain);
for (i = 0; i < capacity; i++) {
p_virt->elem.data_ptr.hi = DMA_HI_LE(p_phys);
p_virt->elem.data_ptr.lo = DMA_LO_LE(p_phys);
DMA_REGPAIR_LE(p_virt->elem.data_ptr, p_phys);
OSAL_LIST_PUSH_TAIL(&p_virt->list, &p_spq->free_pool);
@ -537,18 +558,18 @@ ecore_spq_get_entry(struct ecore_hwfn *p_hwfn, struct ecore_spq_entry **pp_ent)
{
struct ecore_spq *p_spq = p_hwfn->p_spq;
struct ecore_spq_entry *p_ent = OSAL_NULL;
enum _ecore_status_t rc = ECORE_SUCCESS;
OSAL_SPIN_LOCK(&p_spq->lock);
if (OSAL_LIST_IS_EMPTY(&p_spq->free_pool)) {
p_ent = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC,
sizeof(struct ecore_spq_entry));
p_ent = OSAL_ZALLOC(p_hwfn->p_dev, GFP_ATOMIC, sizeof(*p_ent));
if (!p_ent) {
OSAL_SPIN_UNLOCK(&p_spq->lock);
DP_NOTICE(p_hwfn, true,
"Failed to allocate an SPQ entry"
" for a pending ramrod\n");
return ECORE_NOMEM;
"Failed to allocate an SPQ entry for a pending"
" ramrod\n");
rc = ECORE_NOMEM;
goto out_unlock;
}
p_ent->queue = &p_spq->unlimited_pending;
} else {
@ -560,9 +581,9 @@ ecore_spq_get_entry(struct ecore_hwfn *p_hwfn, struct ecore_spq_entry **pp_ent)
*pp_ent = p_ent;
out_unlock:
OSAL_SPIN_UNLOCK(&p_spq->lock);
return ECORE_SUCCESS;
return rc;
}
/* Locked variant; Should be called while the SPQ lock is taken */
@ -607,6 +628,7 @@ ecore_spq_add_entry(struct ecore_hwfn *p_hwfn,
p_spq->unlimited_pending_count++;
return ECORE_SUCCESS;
} else {
struct ecore_spq_entry *p_en2;
@ -621,14 +643,10 @@ ecore_spq_add_entry(struct ecore_hwfn *p_hwfn,
*/
p_ent->elem.data_ptr = p_en2->elem.data_ptr;
/* Setting the cookie to the comp_done of the
* new element.
*/
if (p_ent->comp_cb.cookie == &p_ent->comp_done)
p_ent->comp_cb.cookie = &p_en2->comp_done;
*p_en2 = *p_ent;
/* EBLOCK responsible to free the allocated p_ent */
if (p_ent->comp_mode != ECORE_SPQ_MODE_EBLOCK)
OSAL_FREE(p_hwfn->p_dev, p_ent);
p_ent = p_en2;
@ -682,8 +700,13 @@ static enum _ecore_status_t ecore_spq_post_list(struct ecore_hwfn *p_hwfn,
!OSAL_LIST_IS_EMPTY(head)) {
struct ecore_spq_entry *p_ent =
OSAL_LIST_FIRST_ENTRY(head, struct ecore_spq_entry, list);
if (p_ent != OSAL_NULL) {
#if defined(_NTDDK_)
#pragma warning(suppress : 6011 28182)
#endif
OSAL_LIST_REMOVE_ENTRY(&p_ent->list, head);
OSAL_LIST_PUSH_TAIL(&p_ent->list, &p_spq->completion_pending);
OSAL_LIST_PUSH_TAIL(&p_ent->list,
&p_spq->completion_pending);
p_spq->comp_sent_count++;
rc = ecore_spq_hw_post(p_hwfn, p_spq, p_ent);
@ -694,13 +717,13 @@ static enum _ecore_status_t ecore_spq_post_list(struct ecore_hwfn *p_hwfn,
return rc;
}
}
}
return ECORE_SUCCESS;
}
static enum _ecore_status_t ecore_spq_pend_post(struct ecore_hwfn *p_hwfn)
{
enum _ecore_status_t rc = ECORE_NOTIMPL;
struct ecore_spq *p_spq = p_hwfn->p_spq;
struct ecore_spq_entry *p_ent = OSAL_NULL;
@ -713,17 +736,16 @@ static enum _ecore_status_t ecore_spq_pend_post(struct ecore_hwfn *p_hwfn)
if (!p_ent)
return ECORE_INVAL;
#if defined(_NTDDK_)
#pragma warning(suppress : 6011)
#endif
OSAL_LIST_REMOVE_ENTRY(&p_ent->list, &p_spq->unlimited_pending);
ecore_spq_add_entry(p_hwfn, p_ent, p_ent->priority);
}
rc = ecore_spq_post_list(p_hwfn,
return ecore_spq_post_list(p_hwfn,
&p_spq->pending, SPQ_HIGH_PRI_RESERVE_DEFAULT);
if (rc)
return rc;
return ECORE_SUCCESS;
}
enum _ecore_status_t ecore_spq_post(struct ecore_hwfn *p_hwfn,
@ -785,7 +807,21 @@ enum _ecore_status_t ecore_spq_post(struct ecore_hwfn *p_hwfn,
* access p_ent here to see whether it's successful or not.
* Thus, after gaining the answer perform the cleanup here.
*/
rc = ecore_spq_block(p_hwfn, p_ent, fw_return_code);
rc = ecore_spq_block(p_hwfn, p_ent, fw_return_code,
p_ent->queue == &p_spq->unlimited_pending);
if (p_ent->queue == &p_spq->unlimited_pending) {
/* This is an allocated p_ent which does not need to
* return to pool.
*/
OSAL_FREE(p_hwfn->p_dev, p_ent);
/* TBD: handle error flow and remove p_ent from
* completion pending
*/
return rc;
}
if (rc)
goto spq_post_fail2;
@ -885,10 +921,13 @@ enum _ecore_status_t ecore_spq_completion(struct ecore_hwfn *p_hwfn,
found->comp_cb.function(p_hwfn, found->comp_cb.cookie, p_data,
fw_return_code);
if (found->comp_mode != ECORE_SPQ_MODE_EBLOCK) {
/* EBLOCK is responsible for freeing its own entry */
if ((found->comp_mode != ECORE_SPQ_MODE_EBLOCK) ||
(found->queue == &p_spq->unlimited_pending))
/* EBLOCK is responsible for returning its own entry into the
* free list, unless it originally added the entry into the
* unlimited pending list.
*/
ecore_spq_return_entry(p_hwfn, found);
}
/* Attempt to post pending requests */
OSAL_SPIN_LOCK(&p_spq->lock);
@ -904,7 +943,7 @@ struct ecore_consq *ecore_consq_alloc(struct ecore_hwfn *p_hwfn)
/* Allocate ConsQ struct */
p_consq =
OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(struct ecore_consq));
OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_consq));
if (!p_consq) {
DP_NOTICE(p_hwfn, true,
"Failed to allocate `struct ecore_consq'\n");

5
drivers/net/qede/base/ecore_spq.h
View File

@ -18,6 +18,7 @@
union ramrod_data {
struct pf_start_ramrod_data pf_start;
struct pf_update_ramrod_data pf_update;
struct rl_update_ramrod_data rl_update;
struct rx_queue_start_ramrod_data rx_queue_start;
struct rx_queue_update_ramrod_data rx_queue_update;
struct rx_queue_stop_ramrod_data rx_queue_stop;
@ -101,8 +102,8 @@ struct ecore_spq {
/* Bitmap for handling out-of-order completions */
#define SPQ_RING_SIZE \
(CORE_SPQE_PAGE_SIZE_BYTES / sizeof(struct slow_path_element))
#define SPQ_COMP_BMAP_SIZE \
(SPQ_RING_SIZE / (sizeof(unsigned long) * 8 /* BITS_PER_LONG */))
/* BITS_PER_LONG */
#define SPQ_COMP_BMAP_SIZE (SPQ_RING_SIZE / (sizeof(unsigned long) * 8))
unsigned long p_comp_bitmap[SPQ_COMP_BMAP_SIZE];
u8 comp_bitmap_idx;
#define SPQ_COMP_BMAP_SET_BIT(p_spq, idx) \

1594
drivers/net/qede/base/ecore_sriov.c
View File

File diff suppressed because it is too large Load Diff

149
drivers/net/qede/base/ecore_sriov.h
View File

@ -14,8 +14,6 @@
#include "ecore_iov_api.h"
#include "ecore_hsi_common.h"
#define ECORE_ETH_VF_NUM_VLAN_FILTERS 2
#define ECORE_ETH_MAX_VF_NUM_VLAN_FILTERS \
(MAX_NUM_VFS * ECORE_ETH_VF_NUM_VLAN_FILTERS)
@ -33,25 +31,6 @@ struct ecore_vf_mbx_msg {
union pfvf_tlvs resp;
};
/* This data is held in the ecore_hwfn structure for VFs only. */
struct ecore_vf_iov {
union vfpf_tlvs *vf2pf_request;
dma_addr_t vf2pf_request_phys;
union pfvf_tlvs *pf2vf_reply;
dma_addr_t pf2vf_reply_phys;
/* Should be taken whenever the mailbox buffers are accessed */
osal_mutex_t mutex;
u8 *offset;
/* Bulletin Board */
struct ecore_bulletin bulletin;
struct ecore_bulletin_content bulletin_shadow;
/* we set aside a copy of the acquire response */
struct pfvf_acquire_resp_tlv acquire_resp;
};
/* This mailbox is maintained per VF in its PF
* contains all information required for sending / receiving
* a message
@ -91,15 +70,6 @@ struct ecore_vf_q_info {
u8 txq_active;
};
enum int_mod {
VPORT_INT_MOD_UNDEFINED = 0,
VPORT_INT_MOD_ADAPTIVE = 1,
VPORT_INT_MOD_OFF = 2,
VPORT_INT_MOD_LOW = 100,
VPORT_INT_MOD_MEDIUM = 200,
VPORT_INT_MOD_HIGH = 300
};
enum vf_state {
VF_FREE = 0, /* VF ready to be acquired holds no resc */
VF_ACQUIRED = 1, /* VF, acquired, but not initalized */
@ -117,6 +87,8 @@ struct ecore_vf_shadow_config {
/* Shadow copy of all guest vlans */
struct ecore_vf_vlan_shadow vlans[ECORE_ETH_VF_NUM_VLAN_FILTERS + 1];
/* Shadow copy of all configured MACs; Empty if forcing MACs */
u8 macs[ECORE_ETH_VF_NUM_MAC_FILTERS][ETH_ALEN];
u8 inner_vlan_removal;
};
@ -124,11 +96,15 @@ struct ecore_vf_shadow_config {
struct ecore_vf_info {
struct ecore_iov_vf_mbx vf_mbx;
enum vf_state state;
bool b_init;
u8 to_disable;
struct ecore_bulletin bulletin;
dma_addr_t vf_bulletin;
/* PF saves a copy of the last VF acquire message */
struct vfpf_acquire_tlv acquire;
u32 concrete_fid;
u16 opaque_fid;
u16 mtu;
@ -148,7 +124,6 @@ struct ecore_vf_info {
u8 num_mac_filters;
u8 num_vlan_filters;
u8 num_mc_filters;
struct ecore_vf_q_info vf_queues[ECORE_MAX_VF_CHAINS_PER_PF];
u16 igu_sbs[ECORE_MAX_VF_CHAINS_PER_PF];
@ -181,6 +156,13 @@ struct ecore_pf_iov {
u64 pending_flr[ECORE_VF_ARRAY_LENGTH];
u16 base_vport_id;
#ifndef REMOVE_DBG
/* This doesn't serve anything functionally, but it makes windows
* debugging of IOV related issues easier.
*/
u64 active_vfs[ECORE_VF_ARRAY_LENGTH];
#endif
/* Allocate message address continuosuly and split to each VF */
void *mbx_msg_virt_addr;
dma_addr_t mbx_msg_phys_addr;
@ -196,16 +178,13 @@ struct ecore_pf_iov {
#ifdef CONFIG_ECORE_SRIOV
/**
* @brief Read sriov related information and allocated resources
* reads from configuraiton space, shmem, and allocates the VF
* database in the PF.
* reads from configuraiton space, shmem, etc.
*
* @param p_hwfn
* @param p_ptt
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn);
/**
* @brief ecore_add_tlv - place a given tlv on the tlv buffer at next offset
@ -218,7 +197,9 @@ enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn *p_hwfn,
* @return pointer to the newly placed tlv
*/
void *ecore_add_tlv(struct ecore_hwfn *p_hwfn,
u8 **offset, u16 type, u16 length);
u8 **offset,
u16 type,
u16 length);
/**
* @brief list the types and lengths of the tlvs on the buffer
@ -226,7 +207,8 @@ void *ecore_add_tlv(struct ecore_hwfn *p_hwfn,
* @param p_hwfn
* @param tlvs_list
*/
void ecore_dp_tlv_list(struct ecore_hwfn *p_hwfn, void *tlvs_list);
void ecore_dp_tlv_list(struct ecore_hwfn *p_hwfn,
void *tlvs_list);
/**
* @brief ecore_iov_alloc - allocate sriov related resources
@ -243,7 +225,8 @@ enum _ecore_status_t ecore_iov_alloc(struct ecore_hwfn *p_hwfn);
* @param p_hwfn
* @param p_ptt
*/
void ecore_iov_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
void ecore_iov_setup(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
/**
* @brief ecore_iov_free - free sriov related resources
@ -252,6 +235,13 @@ void ecore_iov_setup(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
*/
void ecore_iov_free(struct ecore_hwfn *p_hwfn);
/**
* @brief free sriov related memory that was allocated during hw_prepare
*
* @param p_dev
*/
void ecore_iov_free_hw_info(struct ecore_dev *p_dev);
/**
* @brief ecore_sriov_eqe_event - handle async sriov event arrived on eqe.
*
@ -274,7 +264,9 @@ enum _ecore_status_t ecore_sriov_eqe_event(struct ecore_hwfn *p_hwfn,
*
* @return calculated crc over buffer [with respect to seed].
*/
u32 ecore_crc32(u32 crc, u8 *ptr, u32 length);
u32 ecore_crc32(u32 crc,
u8 *ptr,
u32 length);
/**
* @brief Mark structs of vfs that have been FLR-ed.
@ -284,7 +276,8 @@ u32 ecore_crc32(u32 crc, u8 *ptr, u32 length);
*
* @return 1 iff one of the PF's vfs got FLRed. 0 otherwise.
*/
int ecore_iov_mark_vf_flr(struct ecore_hwfn *p_hwfn, u32 *disabled_vfs);
int ecore_iov_mark_vf_flr(struct ecore_hwfn *p_hwfn,
u32 *disabled_vfs);
/**
* @brief Search extended TLVs in request/reply buffer.
@ -312,79 +305,5 @@ void *ecore_iov_search_list_tlvs(struct ecore_hwfn *p_hwfn,
struct ecore_vf_info *ecore_iov_get_vf_info(struct ecore_hwfn *p_hwfn,
u16 relative_vf_id,
bool b_enabled_only);
#else
static OSAL_INLINE enum _ecore_status_t ecore_iov_hw_info(struct ecore_hwfn
*p_hwfn,
struct ecore_ptt
*p_ptt)
{
return ECORE_SUCCESS;
}
static OSAL_INLINE void *ecore_add_tlv(struct ecore_hwfn *p_hwfn, u8 **offset,
u16 type, u16 length)
{
return OSAL_NULL;
}
static OSAL_INLINE void ecore_dp_tlv_list(struct ecore_hwfn *p_hwfn,
void *tlvs_list)
{
}
static OSAL_INLINE enum _ecore_status_t ecore_iov_alloc(struct ecore_hwfn
*p_hwfn)
{
return ECORE_SUCCESS;
}
static OSAL_INLINE void ecore_iov_setup(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
}
static OSAL_INLINE void ecore_iov_free(struct ecore_hwfn *p_hwfn)
{
}
static OSAL_INLINE enum _ecore_status_t ecore_sriov_eqe_event(struct ecore_hwfn
*p_hwfn,
u8 opcode,
__le16 echo,
union
event_ring_data
* data)
{
return ECORE_INVAL;
}
static OSAL_INLINE u32 ecore_crc32(u32 crc, u8 *ptr, u32 length)
{
return 0;
}
static OSAL_INLINE int ecore_iov_mark_vf_flr(struct ecore_hwfn *p_hwfn,
u32 *disabled_vfs)
{
return 0;
}
static OSAL_INLINE void *ecore_iov_search_list_tlvs(struct ecore_hwfn *p_hwfn,
void *p_tlvs_list,
u16 req_type)
{
return OSAL_NULL;
}
static OSAL_INLINE struct ecore_vf_info *ecore_iov_get_vf_info(struct ecore_hwfn
*p_hwfn,
u16
relative_vf_id,
bool
b_enabled_only)
{
return OSAL_NULL;
}
#endif
#endif /* __ECORE_SRIOV_H__ */

738
drivers/net/qede/base/ecore_vf.c
View File

File diff suppressed because it is too large Load Diff

224
drivers/net/qede/base/ecore_vf.h
View File

@ -14,31 +14,42 @@
#include "ecore_l2_api.h"
#include "ecore_vfpf_if.h"
/* This data is held in the ecore_hwfn structure for VFs only. */
struct ecore_vf_iov {
union vfpf_tlvs *vf2pf_request;
dma_addr_t vf2pf_request_phys;
union pfvf_tlvs *pf2vf_reply;
dma_addr_t pf2vf_reply_phys;
/* Should be taken whenever the mailbox buffers are accessed */
osal_mutex_t mutex;
u8 *offset;
/* Bulletin Board */
struct ecore_bulletin bulletin;
struct ecore_bulletin_content bulletin_shadow;
/* we set aside a copy of the acquire response */
struct pfvf_acquire_resp_tlv acquire_resp;
/* In case PF originates prior to the fp-hsi version comparison,
* this has to be propagated as it affects the fastpath.
*/
bool b_pre_fp_hsi;
};
#ifdef CONFIG_ECORE_SRIOV
/**
*
* @brief hw preparation for VF
* sends ACQUIRE message
*
* @param p_dev
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_dev *p_dev);
/**
*
* @brief VF init in hw (equivalent to hw_init in PF)
* mark interrupts as enabled
*
* @param p_hwfn
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_vf_pf_init(struct ecore_hwfn *p_hwfn);
enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_hwfn *p_hwfn);
/**
*
* @brief VF - start the RX Queue by sending a message to the PF
*
* @param p_hwfn
@ -51,7 +62,7 @@ enum _ecore_status_t ecore_vf_pf_init(struct ecore_hwfn *p_hwfn);
* @param cqe_pbl_addr - physical address of pbl
* @param cqe_pbl_size - pbl size
* @param pp_prod - pointer to the producer to be
* used in fasthwfn
* used in fasthpath
*
* @return enum _ecore_status_t
*/
@ -66,7 +77,6 @@ enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn *p_hwfn,
void OSAL_IOMEM **pp_prod);
/**
*
* @brief VF - start the TX queue by sending a message to the
* PF.
*
@ -89,7 +99,6 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn,
void OSAL_IOMEM **pp_doorbell);
/**
*
* @brief VF - stop the RX queue by sending a message to the PF
*
* @param p_hwfn
@ -99,10 +108,10 @@ enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn *p_hwfn,
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn *p_hwfn,
u16 rx_qid, bool cqe_completion);
u16 rx_qid,
bool cqe_completion);
/**
*
* @brief VF - stop the TX queue by sending a message to the PF
*
* @param p_hwfn
@ -113,6 +122,7 @@ enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn *p_hwfn,
u16 tx_qid);
#ifndef LINUX_REMOVE
/**
* @brief VF - update the RX queue by sending a message to the
* PF
@ -126,14 +136,15 @@ enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn *p_hwfn,
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_vf_pf_rxqs_update(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t ecore_vf_pf_rxqs_update(
struct ecore_hwfn *p_hwfn,
u16 rx_queue_id,
u8 num_rxqs,
u8 comp_cqe_flg,
u8 comp_event_flg);
#endif
/**
*
* @brief VF - send a vport update command
*
* @param p_hwfn
@ -146,7 +157,6 @@ ecore_vf_pf_vport_update(struct ecore_hwfn *p_hwfn,
struct ecore_sp_vport_update_params *p_params);
/**
*
* @brief VF - send a close message to PF
*
* @param p_hwfn
@ -156,7 +166,6 @@ ecore_vf_pf_vport_update(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t ecore_vf_pf_reset(struct ecore_hwfn *p_hwfn);
/**
*
* @brief VF - free vf`s memories
*
* @param p_hwfn
@ -166,7 +175,6 @@ enum _ecore_status_t ecore_vf_pf_reset(struct ecore_hwfn *p_hwfn);
enum _ecore_status_t ecore_vf_pf_release(struct ecore_hwfn *p_hwfn);
/**
*
* @brief ecore_vf_get_igu_sb_id - Get the IGU SB ID for a given
* sb_id. For VFs igu sbs don't have to be contiguous
*
@ -175,7 +183,9 @@ enum _ecore_status_t ecore_vf_pf_release(struct ecore_hwfn *p_hwfn);
*
* @return INLINE u16
*/
u16 ecore_vf_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id);
u16 ecore_vf_get_igu_sb_id(struct ecore_hwfn *p_hwfn,
u16 sb_id);
/**
* @brief ecore_vf_pf_vport_start - perform vport start for VF.
@ -190,7 +200,8 @@ u16 ecore_vf_get_igu_sb_id(struct ecore_hwfn *p_hwfn, u16 sb_id);
*
* @return enum _ecore_status
*/
enum _ecore_status_t ecore_vf_pf_vport_start(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t ecore_vf_pf_vport_start(
struct ecore_hwfn *p_hwfn,
u8 vport_id,
u16 mtu,
u8 inner_vlan_removal,
@ -207,9 +218,9 @@ enum _ecore_status_t ecore_vf_pf_vport_start(struct ecore_hwfn *p_hwfn,
*/
enum _ecore_status_t ecore_vf_pf_vport_stop(struct ecore_hwfn *p_hwfn);
enum _ecore_status_t ecore_vf_pf_filter_ucast(struct ecore_hwfn *p_hwfn,
struct ecore_filter_ucast
*p_param);
enum _ecore_status_t ecore_vf_pf_filter_ucast(
struct ecore_hwfn *p_hwfn,
struct ecore_filter_ucast *p_param);
void ecore_vf_pf_filter_mcast(struct ecore_hwfn *p_hwfn,
struct ecore_filter_mcast *p_filter_cmd);
@ -256,160 +267,5 @@ void __ecore_vf_get_link_caps(struct ecore_hwfn *p_hwfn,
struct ecore_mcp_link_capabilities *p_link_caps,
struct ecore_bulletin_content *p_bulletin);
#else
static OSAL_INLINE enum _ecore_status_t ecore_vf_hw_prepare(struct ecore_dev
*p_dev)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_init(struct ecore_hwfn
*p_hwfn)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_rxq_start(struct ecore_hwfn
*p_hwfn,
u8 rx_queue_id,
u16 sb,
u8 sb_index,
u16 bd_max_bytes,
dma_addr_t
bd_chain_phys_adr,
dma_addr_t
cqe_pbl_addr,
u16 cqe_pbl_size,
void OSAL_IOMEM *
*pp_prod)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_txq_start(struct ecore_hwfn
*p_hwfn,
u16 tx_queue_id,
u16 sb,
u8 sb_index,
dma_addr_t
pbl_addr,
u16 pbl_size,
void OSAL_IOMEM *
*pp_doorbell)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_rxq_stop(struct ecore_hwfn
*p_hwfn,
u16 rx_qid,
bool
cqe_completion)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_txq_stop(struct ecore_hwfn
*p_hwfn,
u16 tx_qid)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_rxqs_update(struct
ecore_hwfn
* p_hwfn,
u16 rx_queue_id,
u8 num_rxqs,
u8 comp_cqe_flg,
u8
comp_event_flg)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_vport_update(
struct ecore_hwfn *p_hwfn,
struct ecore_sp_vport_update_params *p_params)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_reset(struct ecore_hwfn
*p_hwfn)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_release(struct ecore_hwfn
*p_hwfn)
{
return ECORE_INVAL;
}
static OSAL_INLINE u16 ecore_vf_get_igu_sb_id(struct ecore_hwfn *p_hwfn,
u16 sb_id)
{
return 0;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_vport_start(
struct ecore_hwfn *p_hwfn, u8 vport_id, u16 mtu,
u8 inner_vlan_removal, enum ecore_tpa_mode tpa_mode,
u8 max_buffers_per_cqe, u8 only_untagged)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_vport_stop(
struct ecore_hwfn *p_hwfn)
{
return ECORE_INVAL;
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_filter_ucast(
struct ecore_hwfn *p_hwfn, struct ecore_filter_ucast *p_param)
{
return ECORE_INVAL;
}
static OSAL_INLINE void ecore_vf_pf_filter_mcast(struct ecore_hwfn *p_hwfn,
struct ecore_filter_mcast
*p_filter_cmd)
{
}
static OSAL_INLINE enum _ecore_status_t ecore_vf_pf_int_cleanup(struct
ecore_hwfn
* p_hwfn)
{
return ECORE_INVAL;
}
static OSAL_INLINE void __ecore_vf_get_link_params(struct ecore_hwfn *p_hwfn,
struct ecore_mcp_link_params
*p_params,
struct ecore_bulletin_content
*p_bulletin)
{
}
static OSAL_INLINE void __ecore_vf_get_link_state(struct ecore_hwfn *p_hwfn,
struct ecore_mcp_link_state
*p_link,
struct ecore_bulletin_content
*p_bulletin)
{
}
static OSAL_INLINE void __ecore_vf_get_link_caps(struct ecore_hwfn *p_hwfn,
struct
ecore_mcp_link_capabilities
* p_link_caps,
struct ecore_bulletin_content
*p_bulletin)
{
}
#endif
#endif /* __ECORE_VF_H__ */

93
drivers/net/qede/base/ecore_vf_api.h
View File

@ -57,7 +57,8 @@ void ecore_vf_get_link_caps(struct ecore_hwfn *p_hwfn,
* @param p_hwfn
* @param num_rxqs - allocated RX queues
*/
void ecore_vf_get_num_rxqs(struct ecore_hwfn *p_hwfn, u8 *num_rxqs);
void ecore_vf_get_num_rxqs(struct ecore_hwfn *p_hwfn,
u8 *num_rxqs);
/**
* @brief Get port mac address for VF
@ -65,7 +66,8 @@ void ecore_vf_get_num_rxqs(struct ecore_hwfn *p_hwfn, u8 *num_rxqs);
* @param p_hwfn
* @param port_mac - destination location for port mac
*/
void ecore_vf_get_port_mac(struct ecore_hwfn *p_hwfn, u8 *port_mac);
void ecore_vf_get_port_mac(struct ecore_hwfn *p_hwfn,
u8 *port_mac);
/**
* @brief Get number of VLAN filters allocated for VF by ecore
@ -80,7 +82,7 @@ void ecore_vf_get_num_vlan_filters(struct ecore_hwfn *p_hwfn,
* @brief Get number of MAC filters allocated for VF by ecore
*
* @param p_hwfn
* @param num_mac - allocated MAC filters
* @param num_mac_filters - allocated MAC filters
*/
void ecore_vf_get_num_mac_filters(struct ecore_hwfn *p_hwfn,
u32 *num_mac_filters);
@ -95,6 +97,7 @@ void ecore_vf_get_num_mac_filters(struct ecore_hwfn *p_hwfn,
*/
bool ecore_vf_check_mac(struct ecore_hwfn *p_hwfn, u8 *mac);
#ifndef LINUX_REMOVE
/**
* @brief Copy forced MAC address from bulletin board
*
@ -120,8 +123,20 @@ bool ecore_vf_bulletin_get_forced_mac(struct ecore_hwfn *hwfn, u8 *dst_mac,
bool ecore_vf_bulletin_get_forced_vlan(struct ecore_hwfn *hwfn, u16 *dst_pvid);
/**
* @brief Set firmware version information in dev_info from VFs acquire response
* tlv
* @brief Check if VF is based on PF whose driver is pre-fp-hsi version;
* This affects the fastpath implementation of the driver.
*
* @param p_hwfn
*
* @return bool - true iff PF is pre-fp-hsi version.
*/
bool ecore_vf_get_pre_fp_hsi(struct ecore_hwfn *p_hwfn);
#endif
/**
* @brief Set firmware version information in dev_info from VFs acquire
* response tlv
*
* @param p_hwfn
* @param fw_major
@ -131,70 +146,8 @@ bool ecore_vf_bulletin_get_forced_vlan(struct ecore_hwfn *hwfn, u16 *dst_pvid);
*/
void ecore_vf_get_fw_version(struct ecore_hwfn *p_hwfn,
u16 *fw_major,
u16 *fw_minor, u16 *fw_rev, u16 *fw_eng);
#else
static OSAL_INLINE enum _ecore_status_t ecore_vf_read_bulletin(struct ecore_hwfn
*p_hwfn,
u8 *p_change)
{
return ECORE_INVAL;
}
static OSAL_INLINE void ecore_vf_get_link_params(struct ecore_hwfn *p_hwfn,
struct ecore_mcp_link_params
*params)
{
}
static OSAL_INLINE void ecore_vf_get_link_state(struct ecore_hwfn *p_hwfn,
struct ecore_mcp_link_state
*link)
{
}
static OSAL_INLINE void ecore_vf_get_link_caps(struct ecore_hwfn *p_hwfn,
struct
ecore_mcp_link_capabilities
* p_link_caps)
{
}
static OSAL_INLINE void ecore_vf_get_num_rxqs(struct ecore_hwfn *p_hwfn,
u8 *num_rxqs)
{
}
static OSAL_INLINE void ecore_vf_get_port_mac(struct ecore_hwfn *p_hwfn,
u8 *port_mac)
{
}
static OSAL_INLINE void ecore_vf_get_num_vlan_filters(struct ecore_hwfn *p_hwfn,
u8 *num_vlan_filters)
{
}
static OSAL_INLINE void ecore_vf_get_num_mac_filters(struct ecore_hwfn *p_hwfn,
u32 *num_mac)
{
}
static OSAL_INLINE bool ecore_vf_check_mac(struct ecore_hwfn *p_hwfn, u8 *mac)
{
return false;
}
static OSAL_INLINE bool ecore_vf_bulletin_get_forced_mac(struct ecore_hwfn
*hwfn, u8 *dst_mac,
u8 *p_is_forced)
{
return false;
}
static OSAL_INLINE void ecore_vf_get_fw_version(struct ecore_hwfn *p_hwfn,
u16 *fw_major, u16 *fw_minor,
u16 *fw_rev, u16 *fw_eng)
{
}
u16 *fw_minor,
u16 *fw_rev,
u16 *fw_eng);
#endif
#endif

162
drivers/net/qede/base/ecore_vfpf_if.h
View File

@ -9,11 +9,9 @@
#ifndef __ECORE_VF_PF_IF_H__
#define __ECORE_VF_PF_IF_H__
/* @@@ TBD MichalK this should be HSI? */
#define T_ETH_INDIRECTION_TABLE_SIZE 128
#define T_ETH_RSS_KEY_SIZE 10
#ifndef aligned_u64
#define aligned_u64 u64
#endif
#define T_ETH_RSS_KEY_SIZE 10 /* @@@ TBD this should be HSI? */
/***********************************************
*
@ -44,29 +42,6 @@ struct hw_sb_info {
*
**/
#define TLV_BUFFER_SIZE 1024
#define TLV_ALIGN sizeof(u64)
#define PF_VF_BULLETIN_SIZE 512
#define VFPF_RX_MASK_ACCEPT_NONE 0x00000000
#define VFPF_RX_MASK_ACCEPT_MATCHED_UNICAST 0x00000001
#define VFPF_RX_MASK_ACCEPT_MATCHED_MULTICAST 0x00000002
#define VFPF_RX_MASK_ACCEPT_ALL_UNICAST 0x00000004
#define VFPF_RX_MASK_ACCEPT_ALL_MULTICAST 0x00000008
#define VFPF_RX_MASK_ACCEPT_BROADCAST 0x00000010
/* TODO: #define VFPF_RX_MASK_ACCEPT_ANY_VLAN 0x00000020 */
#define BULLETIN_CONTENT_SIZE (sizeof(struct pf_vf_bulletin_content))
#define BULLETIN_ATTEMPTS 5 /* crc failures before throwing towel */
#define BULLETIN_CRC_SEED 0
enum {
PFVF_STATUS_WAITING = 0,
PFVF_STATUS_SUCCESS,
PFVF_STATUS_FAILURE,
PFVF_STATUS_NOT_SUPPORTED,
PFVF_STATUS_NO_RESOURCE,
PFVF_STATUS_FORCED,
};
/* vf pf channel tlvs */
/* general tlv header (used for both vf->pf request and pf->vf response) */
@ -81,7 +56,7 @@ struct channel_tlv {
struct vfpf_first_tlv {
struct channel_tlv tl;
u32 padding;
aligned_u64 reply_address;
u64 reply_address;
};
/* header of pf->vf tlvs, carries the status of handling the request */
@ -107,8 +82,17 @@ struct vfpf_acquire_tlv {
struct vfpf_first_tlv first_tlv;
struct vf_pf_vfdev_info {
#define VFPF_ACQUIRE_CAP_OVERRIDE_FW_VER (1 << 0)
aligned_u64 capabilties;
#ifndef LINUX_REMOVE
/* First bit was used on 8.7.x and 8.8.x versions, which had different
* FWs used but with the same faspath HSI. As this was prior to the
* fastpath versioning, wanted to have ability to override fw matching
* and allow them to interact.
*/
#endif
/* VF pre-FP hsi version */
#define VFPF_ACQUIRE_CAP_PRE_FP_HSI (1 << 0)
#define VFPF_ACQUIRE_CAP_100G (1 << 1) /* VF can support 100g */
u64 capabilities;
u8 fw_major;
u8 fw_minor;
u8 fw_revision;
@ -116,12 +100,14 @@ struct vfpf_acquire_tlv {
u32 driver_version;
u16 opaque_fid; /* ME register value */
u8 os_type; /* VFPF_ACQUIRE_OS_* value */
u8 padding[5];
u8 eth_fp_hsi_major;
u8 eth_fp_hsi_minor;
u8 padding[3];
} vfdev_info;
struct vf_pf_resc_request resc_request;
aligned_u64 bulletin_addr;
u64 bulletin_addr;
u32 bulletin_size;
u32 padding;
};
@ -168,14 +154,27 @@ struct pfvf_acquire_resp_tlv {
u16 fw_rev;
u16 fw_eng;
aligned_u64 capabilities;
u64 capabilities;
#define PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED (1 << 0)
#define PFVF_ACQUIRE_CAP_100G (1 << 1) /* If set, 100g PF */
/* There are old PF versions where the PF might mistakenly override the sanity
* mechanism [version-based] and allow a VF that can't be supported to pass
* the acquisition phase.
* To overcome this, PFs now indicate that they're past that point and the new
* VFs would fail probe on the older PFs that fail to do so.
*/
#ifndef LINUX_REMOVE
/* Said bug was in quest/serpens; Can't be certain no official release included
* the bug since the fix arrived very late in the programs.
*/
#endif
#define PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE (1 << 2)
u16 db_size;
u8 indices_per_sb;
u8 os_type;
/* Thesee should match the PF's ecore_dev values */
/* These should match the PF's ecore_dev values */
u16 chip_rev;
u8 dev_type;
@ -184,7 +183,14 @@ struct pfvf_acquire_resp_tlv {
struct pfvf_stats_info stats_info;
u8 port_mac[ETH_ALEN];
u8 padding2[2];
/* It's possible PF had to configure an older fastpath HSI
* [in case VF is newer than PF]. This is communicated back
* to the VF. It can also be used in case of error due to
* non-matching versions to shed light in VF about failure.
*/
u8 major_fp_hsi;
u8 minor_fp_hsi;
} pfdev_info;
struct pf_vf_resc {
@ -211,16 +217,10 @@ struct pfvf_acquire_resp_tlv {
u32 padding;
};
/* Init VF */
struct vfpf_init_tlv {
struct vfpf_first_tlv first_tlv;
aligned_u64 stats_addr;
u16 rx_mask;
u16 tx_mask;
u8 drop_ttl0_flg;
u8 padding[3];
struct pfvf_start_queue_resp_tlv {
struct pfvf_tlv hdr;
u32 offset; /* offset to consumer/producer of queue */
u8 padding[4];
};
/* Setup Queue */
@ -228,9 +228,9 @@ struct vfpf_start_rxq_tlv {
struct vfpf_first_tlv first_tlv;
/* physical addresses */
aligned_u64 rxq_addr;
aligned_u64 deprecated_sge_addr;
aligned_u64 cqe_pbl_addr;
u64 rxq_addr;
u64 deprecated_sge_addr;
u64 cqe_pbl_addr;
u16 cqe_pbl_size;
u16 hw_sb;
@ -248,7 +248,7 @@ struct vfpf_start_txq_tlv {
struct vfpf_first_tlv first_tlv;
/* physical addresses */
aligned_u64 pbl_addr;
u64 pbl_addr;
u16 pbl_size;
u16 stat_id;
u16 tx_qid;
@ -282,7 +282,7 @@ struct vfpf_stop_txqs_tlv {
struct vfpf_update_rxq_tlv {
struct vfpf_first_tlv first_tlv;
aligned_u64 deprecated_sge_addr[PFVF_MAX_QUEUES_PER_VF];
u64 deprecated_sge_addr[PFVF_MAX_QUEUES_PER_VF];
u16 rx_qid;
u8 num_rxqs;
@ -311,7 +311,7 @@ struct vfpf_q_mac_vlan_filter {
struct vfpf_vport_start_tlv {
struct vfpf_first_tlv first_tlv;
aligned_u64 sb_addr[PFVF_MAX_SBS_PER_VF];
u64 sb_addr[PFVF_MAX_SBS_PER_VF];
u32 tpa_mode;
u16 dep1;
@ -351,7 +351,7 @@ struct vfpf_vport_update_mcast_bin_tlv {
struct channel_tlv tl;
u8 padding[4];
aligned_u64 bins[8];
u64 bins[8];
};
struct vfpf_vport_update_accept_param_tlv {
@ -423,7 +423,6 @@ struct tlv_buffer_size {
union vfpf_tlvs {
struct vfpf_first_tlv first_tlv;
struct vfpf_acquire_tlv acquire;
struct vfpf_init_tlv init;
struct vfpf_start_rxq_tlv start_rxq;
struct vfpf_start_txq_tlv start_txq;
struct vfpf_stop_rxqs_tlv stop_rxqs;
@ -432,15 +431,14 @@ union vfpf_tlvs {
struct vfpf_vport_start_tlv start_vport;
struct vfpf_vport_update_tlv vport_update;
struct vfpf_ucast_filter_tlv ucast_filter;
struct channel_list_end_tlv list_end;
struct tlv_buffer_size tlv_buf_size;
};
union pfvf_tlvs {
struct pfvf_def_resp_tlv default_resp;
struct pfvf_acquire_resp_tlv acquire_resp;
struct channel_list_end_tlv list_end;
struct tlv_buffer_size tlv_buf_size;
struct pfvf_start_queue_resp_tlv queue_start;
};
/* This is a structure which is allocated in the VF, which the PF may update
@ -469,20 +467,19 @@ enum ecore_bulletin_bit {
};
struct ecore_bulletin_content {
u32 crc; /* crc of structure to ensure is not in
* mid-update
*/
/* crc of structure to ensure is not in mid-update */
u32 crc;
u32 version;
aligned_u64 valid_bitmap; /* bitmap indicating wich fields
* hold valid values
*/
/* bitmap indicating which fields hold valid values */
u64 valid_bitmap;
u8 mac[ETH_ALEN]; /* used for MAC_ADDR or MAC_ADDR_FORCED */
/* used for MAC_ADDR or MAC_ADDR_FORCED */
u8 mac[ETH_ALEN];
u8 default_only_untagged; /* If valid, 1 => only untagged Rx
* if no vlan filter is configured.
*/
/* If valid, 1 => only untagged Rx if no vlan is configured */
u8 default_only_untagged;
u8 padding;
/* The following is a 'copy' of ecore_mcp_link_state,
@ -529,7 +526,6 @@ struct ecore_bulletin {
u32 size;
};
#ifndef print_enum
enum {
/*!!!!! Make sure to update STRINGS structure accordingly !!!!!*/
@ -556,35 +552,15 @@ enum {
CHANNEL_TLV_VPORT_UPDATE_RSS,
CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN,
CHANNEL_TLV_VPORT_UPDATE_SGE_TPA,
CHANNEL_TLV_MAX
CHANNEL_TLV_MAX,
/* Required for iterating over vport-update tlvs.
* Will break in case non-sequential vport-update tlvs.
*/
CHANNEL_TLV_VPORT_UPDATE_MAX = CHANNEL_TLV_VPORT_UPDATE_SGE_TPA + 1,
/*!!!!! Make sure to update STRINGS structure accordingly !!!!!*/
};
extern const char *ecore_channel_tlvs_string[];
#else
print_enum(channel_tlvs, CHANNEL_TLV_NONE, /* ends tlv sequence */
CHANNEL_TLV_ACQUIRE,
CHANNEL_TLV_VPORT_START,
CHANNEL_TLV_VPORT_UPDATE,
CHANNEL_TLV_VPORT_TEARDOWN,
CHANNEL_TLV_SETUP_RXQ,
CHANNEL_TLV_SETUP_TXQ,
CHANNEL_TLV_STOP_RXQS,
CHANNEL_TLV_STOP_TXQS,
CHANNEL_TLV_UPDATE_RXQ,
CHANNEL_TLV_INT_CLEANUP,
CHANNEL_TLV_CLOSE,
CHANNEL_TLV_RELEASE,
CHANNEL_TLV_LIST_END,
CHANNEL_TLV_UCAST_FILTER,
CHANNEL_TLV_VPORT_UPDATE_ACTIVATE,
CHANNEL_TLV_VPORT_UPDATE_TX_SWITCH,
CHANNEL_TLV_VPORT_UPDATE_VLAN_STRIP,
CHANNEL_TLV_VPORT_UPDATE_MCAST,
CHANNEL_TLV_VPORT_UPDATE_ACCEPT_PARAM,
CHANNEL_TLV_VPORT_UPDATE_RSS,
CHANNEL_TLV_VPORT_UPDATE_ACCEPT_ANY_VLAN,
CHANNEL_TLV_VPORT_UPDATE_SGE_TPA, CHANNEL_TLV_MAX);
#endif
#endif /* __ECORE_VF_PF_IF_H__ */

199
drivers/net/qede/base/eth_common.h
View File

@ -11,6 +11,21 @@
/********************/
/* ETH FW CONSTANTS */
/********************/
/* FP HSI version. FP HSI is compatible if (fwVer.major == drvVer.major &&
* fwVer.minor >= drvVer.minor)
*/
/* ETH FP HSI Major version */
#define ETH_HSI_VER_MAJOR 3
/* ETH FP HSI Minor version */
#define ETH_HSI_VER_MINOR 10
/* Alias for 8.7.x.x/8.8.x.x ETH FP HSI MINOR version. In this version driver
* is not required to set pkt_len field in eth_tx_1st_bd struct, and tunneling
* offload is not supported.
*/
#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
#define ETH_CACHE_LINE_SIZE 64
#define ETH_RX_CQE_GAP 32
#define ETH_MAX_RAMROD_PER_CON 8
@ -21,19 +36,40 @@
#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
#define ETH_TX_MAX_LSO_HDR_NBD 4
#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 12 + 8))
/* (QM_REG_TASKBYTECRDCOST_0, QM_VOQ_BYTE_CRD_TASK_COST) -
* (VLAN-TAG + CRC + IPG + PREAMBLE)
*/
#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
#define ETH_TX_MAX_LSO_HDR_BYTES 510
#define ETH_TX_LSO_WINDOW_BDS_NUM 18
/* Number of BDs to consider for LSO sliding window restriction is
* (ETH_TX_LSO_WINDOW_BDS_NUM - hdr_nbd)
*/
#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
/* Minimum data length (in bytes) in LSO sliding window */
#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFFFF
/* Maximum LSO packet TCP payload length (in bytes) */
#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
/* Number of same-as-last resources in tx switching */
#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
/* Value for a connection for which same as last feature is disabled */
#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
/* Maximum number of statistics counters */
#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
/* Maximum number of statistics counters when doubled VF zone used */
#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
(ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
/* Maximum number of statistics counters when quad VF zone used */
#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
(ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
/* Maximum number of buffers, used for RX packet placement */
#define ETH_RX_MAX_BUFF_PER_PKT 5
/* num of MAC/VLAN filters */
@ -62,6 +98,12 @@
#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
/* Control frame check constants */
/* Number of etherType values configured by driver for control frame check */
#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
/*
* Destination port mode
*/
@ -108,19 +150,21 @@ struct eth_tx_1st_bd_flags {
* The parsing information data for the first tx bd of a given packet.
*/
struct eth_tx_data_1st_bd {
__le16 vlan /* VLAN to insert to packet (if needed). */;
/* Number of BDs in packet. Should be at least 2 in non-LSO
* packet and at least 3 in LSO (or Tunnel with IPv6+ext) packet.
__le16 vlan /* VLAN tag to insert to packet (if needed). */;
/* Number of BDs in packet. Should be at least 2 in non-LSO packet and at least
* 3 in LSO (or Tunnel with IPv6+ext) packet.
*/
u8 nbds;
struct eth_tx_1st_bd_flags bd_flags;
__le16 bitfields;
#define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_MASK 0x1
#define ETH_TX_DATA_1ST_BD_TUNN_CFG_OVERRIDE_SHIFT 0
/* Indicates a tunneled packet. Must be set for encapsulated packet. */
#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
#define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_MASK 0x3FFF
#define ETH_TX_DATA_1ST_BD_FW_USE_ONLY_SHIFT 2
/* Total packet length - must be filled for non-LSO packets. */
#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
};
/*
@ -171,25 +215,51 @@ struct eth_edpm_fw_data {
* FW debug.
*/
struct eth_fast_path_cqe_fw_debug {
u8 reserved0 /* FW reserved. */;
u8 reserved1 /* FW reserved. */;
__le16 reserved2 /* FW reserved. */;
};
struct tunnel_parsing_flags {
/*
* tunneling parsing flags
*/
struct eth_tunnel_parsing_flags {
u8 flags;
#define TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
#define TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
#define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
#define TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
#define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
#define TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
#define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
#define TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
#define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
#define TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
#define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
#define TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
/* 0 - no tunneling, 1 - GENEVE, 2 - GRE, 3 - VXLAN
* (use enum eth_rx_tunn_type)
*/
#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
#define ETH_TUNNEL_PARSING_FLAGS_TYPE_SHIFT 0
/* If it s not an encapsulated packet then put 0x0. If it s an encapsulated
* packet but the tenant-id doesn t exist then put 0x0. Else put 0x1
*
*/
#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_MASK 0x1
#define ETH_TUNNEL_PARSING_FLAGS_TENNANT_ID_EXIST_SHIFT 2
/* Type of the next header above the tunneling: 0 - unknown, 1 - L2, 2 - Ipv4,
* 3 - IPv6 (use enum tunnel_next_protocol)
*/
#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_MASK 0x3
#define ETH_TUNNEL_PARSING_FLAGS_NEXT_PROTOCOL_SHIFT 3
/* The result of comparing the DA-ip of the tunnel header. */
#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_MASK 0x1
#define ETH_TUNNEL_PARSING_FLAGS_FIRSTHDRIPMATCH_SHIFT 5
#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_MASK 0x1
#define ETH_TUNNEL_PARSING_FLAGS_IPV4_FRAGMENT_SHIFT 6
#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_MASK 0x1
#define ETH_TUNNEL_PARSING_FLAGS_IPV4_OPTIONS_SHIFT 7
};
/*
* PMD flow control bits
*/
struct eth_pmd_flow_flags {
u8 flags;
#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1 /* CQE valid bit */
#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1 /* CQE ring toggle bit */
#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
};
/*
@ -205,25 +275,19 @@ struct eth_fast_path_rx_reg_cqe {
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
__le16 pkt_len /* Total packet length (from the parser) */;
struct parsing_and_err_flags pars_flags
/* Parsing and error flags from the parser */;
/* Parsing and error flags from the parser */
struct parsing_and_err_flags pars_flags;
__le16 vlan_tag /* 802.1q VLAN tag */;
__le32 rss_hash /* RSS hash result */;
__le16 len_on_first_bd /* Number of bytes placed on first BD */;
u8 placement_offset /* Offset of placement from BD start */;
struct tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */
;
/* Tunnel Parsing Flags */
struct eth_tunnel_parsing_flags tunnel_pars_flags;
u8 bd_num /* Number of BDs, used for packet */;
u8 reserved[7];
u8 reserved[9];
struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
u8 reserved1[3];
u8 flags;
#define ETH_FAST_PATH_RX_REG_CQE_VALID_MASK 0x1
#define ETH_FAST_PATH_RX_REG_CQE_VALID_SHIFT 0
#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_MASK 0x1
#define ETH_FAST_PATH_RX_REG_CQE_VALID_TOGGLE_SHIFT 1
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_MASK 0x3F
#define ETH_FAST_PATH_RX_REG_CQE_RESERVED2_SHIFT 2
struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
};
/*
@ -234,9 +298,11 @@ struct eth_fast_path_rx_tpa_cont_cqe {
u8 tpa_agg_index /* TPA aggregation index */;
__le16 len_list[ETH_TPA_CQE_CONT_LEN_LIST_SIZE]
/* List of the segment sizes */;
u8 reserved[5];
u8 reserved;
u8 reserved1 /* FW reserved. */;
__le16 reserved2[ETH_TPA_CQE_CONT_LEN_LIST_SIZE] /* FW reserved. */;
u8 reserved3[3];
struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
};
/*
@ -253,9 +319,10 @@ struct eth_fast_path_rx_tpa_end_cqe {
__le32 ts_delta /* TCP timestamp delta */;
__le16 len_list[ETH_TPA_CQE_END_LEN_LIST_SIZE]
/* List of the segment sizes */;
u8 reserved1[3];
u8 reserved2 /* FW reserved. */;
__le16 reserved3[ETH_TPA_CQE_END_LEN_LIST_SIZE] /* FW reserved. */;
__le16 reserved1;
u8 reserved2 /* FW reserved. */;
struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
};
/*
@ -277,13 +344,15 @@ struct eth_fast_path_rx_tpa_start_cqe {
__le32 rss_hash /* RSS hash result */;
__le16 len_on_first_bd /* Number of bytes placed on first BD */;
u8 placement_offset /* Offset of placement from BD start */;
struct tunnel_parsing_flags tunnel_pars_flags /* Tunnel Parsing Flags */
;
/* Tunnel Parsing Flags */
struct eth_tunnel_parsing_flags tunnel_pars_flags;
u8 tpa_agg_index /* TPA aggregation index */;
u8 header_len /* Packet L2+L3+L4 header length */;
__le16 ext_bd_len_list[ETH_TPA_CQE_START_LEN_LIST_SIZE]
/* Additional BDs length list. */;
struct eth_fast_path_cqe_fw_debug fw_debug /* FW reserved. */;
u8 reserved;
struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
};
/*
@ -315,13 +384,7 @@ struct eth_slow_path_rx_cqe {
u8 reserved[25];
__le16 echo;
u8 reserved1;
u8 flags;
#define ETH_SLOW_PATH_RX_CQE_VALID_MASK 0x1
#define ETH_SLOW_PATH_RX_CQE_VALID_SHIFT 0
#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_MASK 0x1
#define ETH_SLOW_PATH_RX_CQE_VALID_TOGGLE_SHIFT 1
#define ETH_SLOW_PATH_RX_CQE_RESERVED2_MASK 0x3F
#define ETH_SLOW_PATH_RX_CQE_RESERVED2_SHIFT 2
struct eth_pmd_flow_flags pmd_flags /* CQE valid and toggle bits */;
};
/*
@ -360,6 +423,17 @@ struct eth_rx_pmd_cqe {
u8 reserved[ETH_RX_CQE_GAP];
};
/*
* Eth RX Tunnel Type
*/
enum eth_rx_tunn_type {
ETH_RX_NO_TUNN /* No Tunnel. */,
ETH_RX_TUNN_GENEVE /* GENEVE Tunnel. */,
ETH_RX_TUNN_GRE /* GRE Tunnel. */,
ETH_RX_TUNN_VXLAN /* VXLAN Tunnel. */,
MAX_ETH_RX_TUNN_TYPE
};
/*
* Aggregation end reason.
*/
@ -377,16 +451,7 @@ enum eth_tpa_end_reason {
MAX_ETH_TPA_END_REASON
};
/*
* Eth Tunnel Type
*/
enum eth_tunn_type {
ETH_TUNN_GENEVE /* GENEVE Tunnel. */,
ETH_TUNN_TTAG /* T-Tag Tunnel. */,
ETH_TUNN_GRE /* GRE Tunnel. */,
ETH_TUNN_VXLAN /* VXLAN Tunnel. */,
MAX_ETH_TUNN_TYPE
};
/*
* The first tx bd of a given packet
@ -466,20 +531,24 @@ union eth_tx_bd_types {
};
/*
* Mstorm Queue Zone
* Eth Tx Tunnel Type
*/
struct mstorm_eth_queue_zone {
struct eth_rx_prod_data rx_producers;
__le32 reserved[2];
enum eth_tx_tunn_type {
ETH_TX_TUNN_GENEVE /* GENEVE Tunnel. */,
ETH_TX_TUNN_TTAG /* T-Tag Tunnel. */,
ETH_TX_TUNN_GRE /* GRE Tunnel. */,
ETH_TX_TUNN_VXLAN /* VXLAN Tunnel. */,
MAX_ETH_TX_TUNN_TYPE
};
/*
* Ystorm Queue Zone
*/
struct ystorm_eth_queue_zone {
struct xstorm_eth_queue_zone {
struct coalescing_timeset int_coalescing_timeset
/* Tx interrupt coalescing TimeSet */;
__le16 reserved[3];
u8 reserved[7];
};
/*

402
drivers/net/qede/base/mcp_public.h
View File

@ -42,15 +42,22 @@ typedef u32 offsize_t; /* In DWORDS !!! */
#define SECTION_SIZE(_offsize) \
(((_offsize & OFFSIZE_SIZE_MASK) >> OFFSIZE_SIZE_SHIFT) << 2)
/* SECTION_ADDR returns the GRC addr of a section, given offsize and index
* within section
*/
#define SECTION_ADDR(_offsize, idx) \
(MCP_REG_SCRATCH + SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))
(MCP_REG_SCRATCH + \
SECTION_OFFSET(_offsize) + (SECTION_SIZE(_offsize) * idx))
/* SECTION_OFFSIZE_ADDR returns the GRC addr to the offsize address. Use
* offsetof, since the OFFSETUP collide with the firmware definition
*/
#define SECTION_OFFSIZE_ADDR(_pub_base, _section) \
(_pub_base + offsetof(struct mcp_public_data, sections[_section]))
/* PHY configuration */
struct pmm_phy_cfg {
u32 speed; /* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
/* 0 = autoneg, 1000/10000/20000/25000/40000/50000/100000 */
u32 speed;
#define PMM_SPEED_AUTONEG 0
#define PMM_SPEED_SMARTLINQ 0x8
@ -93,12 +100,15 @@ struct pmm_stats {
u64 r255; /* 0x02 (Offset 0x10 ) RX 128 to 255 byte frame counter*/
u64 r511; /* 0x03 (Offset 0x18 ) RX 256 to 511 byte frame counter*/
u64 r1023; /* 0x04 (Offset 0x20 ) RX 512 to 1023 byte frame counter*/
u64 r1518; /* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
u64 r1522; /* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged */
/* 0x05 (Offset 0x28 ) RX 1024 to 1518 byte frame counter */
u64 r1518;
/* 0x06 (Offset 0x30 ) RX 1519 to 1522 byte VLAN-tagged frame counter */
u64 r1522;
u64 r2047; /* 0x07 (Offset 0x38 ) RX 1519 to 2047 byte frame counter*/
u64 r4095; /* 0x08 (Offset 0x40 ) RX 2048 to 4095 byte frame counter*/
u64 r9216; /* 0x09 (Offset 0x48 ) RX 4096 to 9216 byte frame counter*/
u64 r16383; /* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame ctr */
/* 0x0A (Offset 0x50 ) RX 9217 to 16383 byte frame counter */
u64 r16383;
u64 rfcs; /* 0x0F (Offset 0x58 ) RX FCS error frame counter*/
u64 rxcf; /* 0x10 (Offset 0x60 ) RX control frame counter*/
u64 rxpf; /* 0x11 (Offset 0x68 ) RX pause frame counter*/
@ -114,25 +124,36 @@ struct pmm_stats {
u64 t255; /* 0x42 (Offset 0xb8 ) TX 128 to 255 byte frame counter*/
u64 t511; /* 0x43 (Offset 0xc0 ) TX 256 to 511 byte frame counter*/
u64 t1023; /* 0x44 (Offset 0xc8 ) TX 512 to 1023 byte frame counter*/
u64 t1518; /* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
u64 t2047; /* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
u64 t4095; /* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
u64 t9216; /* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
u64 t16383; /* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame ctr */
/* 0x45 (Offset 0xd0 ) TX 1024 to 1518 byte frame counter */
u64 t1518;
/* 0x47 (Offset 0xd8 ) TX 1519 to 2047 byte frame counter */
u64 t2047;
/* 0x48 (Offset 0xe0 ) TX 2048 to 4095 byte frame counter */
u64 t4095;
/* 0x49 (Offset 0xe8 ) TX 4096 to 9216 byte frame counter */
u64 t9216;
/* 0x4A (Offset 0xf0 ) TX 9217 to 16383 byte frame counter */
u64 t16383;
u64 txpf; /* 0x50 (Offset 0xf8 ) TX pause frame counter */
u64 txpp; /* 0x51 (Offset 0x100) TX PFC frame counter */
u64 tlpiec; /* 0x6C (Offset 0x108) Transmit Logical Type LLFC */
/* 0x6C (Offset 0x108) Transmit Logical Type LLFC message counter */
u64 tlpiec;
u64 tncl; /* 0x6E (Offset 0x110) Transmit Total Collision Counter */
u64 rbyte; /* 0x3d (Offset 0x118) RX byte counter */
u64 rxuca; /* 0x0c (Offset 0x120) RX UC frame counter */
u64 rxmca; /* 0x0d (Offset 0x128) RX MC frame counter */
u64 rxbca; /* 0x0e (Offset 0x130) RX BC frame counter */
u64 rxpok; /* 0x22 (Offset 0x138) RX good frame */
/* 0x22 (Offset 0x138) RX good frame (good CRC, not oversized, no ERROR) */
u64 rxpok;
u64 tbyte; /* 0x6f (Offset 0x140) TX byte counter */
u64 txuca; /* 0x4d (Offset 0x148) TX UC frame counter */
u64 txmca; /* 0x4e (Offset 0x150) TX MC frame counter */
u64 txbca; /* 0x4f (Offset 0x158) TX BC frame counter */
u64 txcf; /* 0x54 (Offset 0x160) TX control frame counter */
/* HSI - Cannot add more stats to this struct. If needed, then need to open new
* struct
*/
};
struct brb_stats {
@ -145,25 +166,26 @@ struct port_stats {
struct pmm_stats pmm;
};
/*-----+-----------------------------------------------------------------------
* Chip | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines
* | rate of physical | team #1 | team #2 |are used|per path | (paths)
* | ports | | | | |
*======+==================+=========+=========+========+======================
* BB | 1x100G | This is special mode, where there are 2 HW func
/*----+------------------------------------------------------------------------
* C | Number and | Ports in| Ports in|2 PHY-s |# of ports|# of engines
* h | rate of | team #1 | team #2 |are used|per path | (paths)
* i | physical | | | | | enabled
* p | ports | | | | |
*====+============+=========+=========+========+==========+===================
* BB | 1x100G | This is special mode, where there are actually 2 HW func
* BB | 2x10/20Gbps| 0,1 | NA | No | 1 | 1
* BB | 2x40 Gbps | 0,1 | NA | Yes | 1 | 1
* BB | 2x50Gbps | 0,1 | NA | No | 1 | 1
* BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2
* BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2
* BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2
* BB | 4x10Gbps | 0,2 | 1,3 | No | 1/2 | 1,2 (2 is optional)
* BB | 4x10Gbps | 0,1 | 2,3 | No | 1/2 | 1,2 (2 is optional)
* BB | 4x10Gbps | 0,3 | 1,2 | No | 1/2 | 1,2 (2 is optional)
* BB | 4x10Gbps | 0,1,2,3 | NA | No | 1 | 1
* AH | 2x10/20Gbps| 0,1 | NA | NA | 1 | NA
* AH | 4x10Gbps | 0,1 | 2,3 | NA | 2 | NA
* AH | 4x10Gbps | 0,2 | 1,3 | NA | 2 | NA
* AH | 4x10Gbps | 0,3 | 1,2 | NA | 2 | NA
* AH | 4x10Gbps | 0,1,2,3 | NA | NA | 1 | NA
*======+==================+=========+=========+========+=======================
*====+============+=========+=========+========+==========+===================
*/
#define CMT_TEAM0 0
@ -225,7 +247,6 @@ struct lldp_status_params_s {
u32 status; /* TBD */
/* Holds remote Chassis ID TLV header, subtype and 9B of payload.
*/
u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
/* Holds remote Port ID TLV header, subtype and 9B of payload.
*/
@ -245,10 +266,26 @@ struct dcbx_ets_feature {
#define DCBX_ETS_CBS_SHIFT 3
#define DCBX_ETS_MAX_TCS_MASK 0x000000f0
#define DCBX_ETS_MAX_TCS_SHIFT 4
#define DCBX_ISCSI_OOO_TC_MASK 0x00000f00
#define DCBX_ISCSI_OOO_TC_SHIFT 8
/* Entries in tc table are orginized that the left most is pri 0, right most is
* prio 7
*/
u32 pri_tc_tbl[1];
#define DCBX_ISCSI_OOO_TC (4)
#define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_ISCSI_OOO_TC + 1)
#define DCBX_CEE_STRICT_PRIORITY 0xf
#define DCBX_CEE_STRICT_PRIORITY_TC 0x7
/* Entries in tc table are orginized that the left most is pri 0, right most is
* prio 7
*/
u32 tc_bw_tbl[2];
/* Entries in tc table are orginized that the left most is pri 0, right most is
* prio 7
*/
u32 tc_tsa_tbl[2];
#define DCBX_ETS_TSA_STRICT 0
#define DCBX_ETS_TSA_CBS 1
@ -271,6 +308,14 @@ struct dcbx_app_priority_entry {
#define DCBX_APP_SF_SHIFT 8
#define DCBX_APP_SF_ETHTYPE 0
#define DCBX_APP_SF_PORT 1
#define DCBX_APP_SF_IEEE_MASK 0x0000f000
#define DCBX_APP_SF_IEEE_SHIFT 12
#define DCBX_APP_SF_IEEE_RESERVED 0
#define DCBX_APP_SF_IEEE_ETHTYPE 1
#define DCBX_APP_SF_IEEE_TCP_PORT 2
#define DCBX_APP_SF_IEEE_UDP_PORT 3
#define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4
#define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000
#define DCBX_APP_PROTOCOL_ID_SHIFT 16
};
@ -287,7 +332,7 @@ struct dcbx_app_priority_feature {
/* Not in use
* #define DCBX_APP_DEFAULT_PRI_MASK 0x00000f00
* #define DCBX_APP_DEFAULT_PRI_SHIFT 8
*/
*/
#define DCBX_APP_MAX_TCS_MASK 0x0000f000
#define DCBX_APP_MAX_TCS_SHIFT 12
#define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000
@ -331,11 +376,12 @@ struct dcbx_features {
struct dcbx_local_params {
u32 config;
#define DCBX_CONFIG_VERSION_MASK 0x00000003
#define DCBX_CONFIG_VERSION_MASK 0x00000007
#define DCBX_CONFIG_VERSION_SHIFT 0
#define DCBX_CONFIG_VERSION_DISABLED 0
#define DCBX_CONFIG_VERSION_IEEE 1
#define DCBX_CONFIG_VERSION_CEE 2
#define DCBX_CONFIG_VERSION_STATIC 4
u32 flags;
struct dcbx_features features;
@ -345,12 +391,13 @@ struct dcbx_mib {
u32 prefix_seq_num;
u32 flags;
/*
* #define DCBX_CONFIG_VERSION_MASK 0x00000003
* #define DCBX_CONFIG_VERSION_MASK 0x00000007
* #define DCBX_CONFIG_VERSION_SHIFT 0
* #define DCBX_CONFIG_VERSION_DISABLED 0
* #define DCBX_CONFIG_VERSION_IEEE 1
* #define DCBX_CONFIG_VERSION_CEE 2
*/
* #define DCBX_CONFIG_VERSION_STATIC 4
*/
struct dcbx_features features;
u32 suffix_seq_num;
};
@ -361,6 +408,14 @@ struct lldp_system_tlvs_buffer_s {
u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
};
struct dcb_dscp_map {
u32 flags;
#define DCB_DSCP_ENABLE_MASK 0x1
#define DCB_DSCP_ENABLE_SHIFT 0
#define DCB_DSCP_ENABLE 1
u32 dscp_pri_map[8];
};
/**************************************/
/* */
/* P U B L I C G L O B A L */
@ -368,7 +423,8 @@ struct lldp_system_tlvs_buffer_s {
/**************************************/
struct public_global {
u32 max_path; /* 32bit is wasty, but this will be used often */
u32 max_ports; /* (Global) 32bit is wasty, this will be used often */
/* (Global) 32bit is wasty, but this will be used often */
u32 max_ports;
#define MODE_1P 1 /* TBD - NEED TO THINK OF A BETTER NAME */
#define MODE_2P 2
#define MODE_3P 3
@ -380,6 +436,10 @@ struct public_global {
u32 mfw_ver;
u32 running_bundle_id;
s32 external_temperature;
u32 mdump_reason;
#define MDUMP_REASON_INTERNAL_ERROR (1 << 0)
#define MDUMP_REASON_EXTERNAL_TRIGGER (1 << 1)
#define MDUMP_REASON_DUMP_AGED (1 << 2)
};
/**************************************/
@ -426,8 +486,8 @@ struct public_path {
*/
u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; /* 0x003c */
u32 process_kill;
/* Reset on mcp reset, and incremented for eveny process kill event. */
u32 process_kill;
#define PROCESS_KILL_COUNTER_MASK 0x0000ffff
#define PROCESS_KILL_COUNTER_SHIFT 0
#define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000
@ -473,7 +533,8 @@ struct public_port {
#define MCP_VALIDITY_RESERVED 0x00000007
/* One licensing bit should be set */
#define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 /* yaniv - tbd */
/* yaniv - tbd ? license */
#define MCP_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
#define MCP_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
#define MCP_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
#define MCP_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
@ -525,9 +586,15 @@ struct public_port {
#define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000
#define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000
#define LINK_STATUS_FEC_MODE_MASK 0x38000000
#define LINK_STATUS_FEC_MODE_NONE (0 << 27)
#define LINK_STATUS_FEC_MODE_FIRECODE_CL74 (1 << 27)
#define LINK_STATUS_FEC_MODE_RS_CL91 (2 << 27)
u32 link_status1;
u32 ext_phy_fw_version;
u32 drv_phy_cfg_addr; /* Points to pmm_phy_cfg (For READ-ONLY) */
/* Points to struct pmm_phy_cfg (For READ-ONLY) */
u32 drv_phy_cfg_addr;
u32 port_stx;
@ -538,11 +605,11 @@ struct public_port {
u32 media_type;
#define MEDIA_UNSPECIFIED 0x0
#define MEDIA_SFPP_10G_FIBER 0x1
#define MEDIA_XFP_FIBER 0x2
#define MEDIA_SFPP_10G_FIBER 0x1 /* Use MEDIA_MODULE_FIBER instead */
#define MEDIA_XFP_FIBER 0x2 /* Use MEDIA_MODULE_FIBER instead */
#define MEDIA_DA_TWINAX 0x3
#define MEDIA_BASE_T 0x4
#define MEDIA_SFP_1G_FIBER 0x5
#define MEDIA_SFP_1G_FIBER 0x5 /* Use MEDIA_MODULE_FIBER instead */
#define MEDIA_MODULE_FIBER 0x6
#define MEDIA_KR 0xf0
#define MEDIA_NOT_PRESENT 0xff
@ -565,6 +632,7 @@ struct public_port {
u32 link_change_count;
/* LLDP params */
/* offset: 536 bytes? */
struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
@ -575,6 +643,7 @@ struct public_port {
struct dcbx_mib operational_dcbx_mib;
/* FC_NPIV table offset & size in NVRAM value of 0 means not present */
u32 fc_npiv_nvram_tbl_addr;
u32 fc_npiv_nvram_tbl_size;
u32 transceiver_data;
@ -628,6 +697,7 @@ struct public_port {
#define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34
#define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35
#define PMM_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36
struct dcb_dscp_map dcb_dscp_map;
};
/**************************************/
@ -637,11 +707,12 @@ struct public_port {
/**************************************/
struct public_func {
u32 dpdk_rsvd1[2];
u32 iscsi_boot_signature;
u32 iscsi_boot_block_offset;
/* MTU size per funciton is needed for the OV feature */
u32 mtu_size;
/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
/* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
/* For PCP values 0-3 use the map lower */
/* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
* 0x0000FF00 - PCP 2, 0x000000FF PCP 3
@ -669,7 +740,10 @@ struct public_func {
#define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0
#define FUNC_MF_CFG_PROTOCOL_SHIFT 4
#define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000
#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000000
#define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010
#define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020
#define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030
#define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030
/* MINBW, MAXBW */
/* value range - 0..100, increments in 1 % */
@ -690,7 +764,11 @@ struct public_func {
u32 mac_lower;
#define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
u32 dpdk_rsvd2[4];
u32 fcoe_wwn_port_name_upper;
u32 fcoe_wwn_port_name_lower;
u32 fcoe_wwn_node_name_upper;
u32 fcoe_wwn_node_name_lower;
u32 ovlan_stag; /* tags */
#define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff
@ -763,9 +841,9 @@ struct mcp_file_att {
struct bist_nvm_image_att {
u32 return_code;
u32 image_type; /* Image type */
u32 nvm_start_addr; /* NVM address of the image */
u32 len; /* Include CRC */
u32 image_type; /* Image type */
u32 nvm_start_addr; /* NVM address of the image */
u32 len; /* Include CRC */
};
#define MCP_DRV_VER_STR_SIZE 16
@ -784,50 +862,82 @@ struct lan_stats_stc {
u32 rserved;
};
struct fcoe_stats_stc {
u64 rx_pkts;
u64 tx_pkts;
u32 fcs_err;
u32 login_failure;
};
struct iscsi_stats_stc {
u64 rx_pdus;
u64 tx_pdus;
u64 rx_bytes;
u64 tx_bytes;
};
struct rdma_stats_stc {
u64 rx_pkts;
u64 tx_pkts;
u64 rx_bytes;
u64 tx_bytes;
};
struct ocbb_data_stc {
u32 ocbb_host_addr;
u32 ocsd_host_addr;
u32 ocsd_req_update_interval;
};
#define MAX_NUM_OF_SENSORS 7
#define MFW_SENSOR_LOCATION_INTERNAL 1
#define MFW_SENSOR_LOCATION_EXTERNAL 2
#define MFW_SENSOR_LOCATION_SFP 3
#define MAX_NUM_OF_SENSORS 7
#define MFW_SENSOR_LOCATION_INTERNAL 1
#define MFW_SENSOR_LOCATION_EXTERNAL 2
#define MFW_SENSOR_LOCATION_SFP 3
#define SENSOR_LOCATION_SHIFT 0
#define SENSOR_LOCATION_MASK 0x000000ff
#define THRESHOLD_HIGH_SHIFT 8
#define THRESHOLD_HIGH_MASK 0x0000ff00
#define CRITICAL_TEMPERATURE_SHIFT 16
#define CRITICAL_TEMPERATURE_MASK 0x00ff0000
#define CURRENT_TEMP_SHIFT 24
#define CURRENT_TEMP_MASK 0xff000000
#define SENSOR_LOCATION_SHIFT 0
#define SENSOR_LOCATION_MASK 0x000000ff
#define THRESHOLD_HIGH_SHIFT 8
#define THRESHOLD_HIGH_MASK 0x0000ff00
#define CRITICAL_TEMPERATURE_SHIFT 16
#define CRITICAL_TEMPERATURE_MASK 0x00ff0000
#define CURRENT_TEMP_SHIFT 24
#define CURRENT_TEMP_MASK 0xff000000
struct temperature_status_stc {
u32 num_of_sensors;
u32 sensor[MAX_NUM_OF_SENSORS];
};
/* crash dump configuration header */
struct mdump_config_stc {
u32 version;
u32 config;
u32 epoc;
u32 num_of_logs;
u32 valid_logs;
};
enum resource_id_enum {
RESOURCE_NUM_SB_E = 0,
RESOURCE_NUM_L2_QUEUE_E = 1,
RESOURCE_NUM_VPORT_E = 2,
RESOURCE_NUM_VMQ_E = 3,
RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
RESOURCE_FACTOR_RSS_PER_VF_E = 5,
RESOURCE_NUM_RL_E = 6,
RESOURCE_NUM_PQ_E = 7,
RESOURCE_NUM_VF_E = 8,
RESOURCE_VFC_FILTER_E = 9,
RESOURCE_ILT_E = 10,
RESOURCE_CQS_E = 11,
RESOURCE_GFT_PROFILES_E = 12,
RESOURCE_NUM_TC_E = 13,
RESOURCE_NUM_RSS_ENGINES_E = 14,
RESOURCE_LL2_QUEUE_E = 15,
RESOURCE_RDMA_STATS_QUEUE_E = 16,
RESOURCE_NUM_SB_E = 0,
RESOURCE_NUM_L2_QUEUE_E = 1,
RESOURCE_NUM_VPORT_E = 2,
RESOURCE_NUM_VMQ_E = 3,
/* Not a real resource!! it's a factor used to calculate others */
RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
/* Not a real resource!! it's a factor used to calculate others */
RESOURCE_FACTOR_RSS_PER_VF_E = 5,
RESOURCE_NUM_RL_E = 6,
RESOURCE_NUM_PQ_E = 7,
RESOURCE_NUM_VF_E = 8,
RESOURCE_VFC_FILTER_E = 9,
RESOURCE_ILT_E = 10,
RESOURCE_CQS_E = 11,
RESOURCE_GFT_PROFILES_E = 12,
RESOURCE_NUM_TC_E = 13,
RESOURCE_NUM_RSS_ENGINES_E = 14,
RESOURCE_LL2_QUEUE_E = 15,
RESOURCE_RDMA_STATS_QUEUE_E = 16,
RESOURCE_MAX_NUM,
RESOURCE_NUM_INVALID = 0xFFFFFFFF
RESOURCE_NUM_INVALID = 0xFFFFFFFF
};
/* Resource ID is to be filled by the driver in the MB request
@ -847,6 +957,8 @@ union drv_union_data {
u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; /* LOAD_REQ */
struct mcp_mac wol_mac; /* UNLOAD_DONE */
/* This configuration should be set by the driver for the LINK_SET command. */
struct pmm_phy_cfg drv_phy_cfg;
struct mcp_val64 val64; /* For PHY / AVS commands */
@ -860,12 +972,14 @@ union drv_union_data {
struct drv_version_stc drv_version;
struct lan_stats_stc lan_stats;
u32 dpdk_rsvd[3];
struct fcoe_stats_stc fcoe_stats;
struct iscsi_stats_stc icsci_stats;
struct rdma_stats_stc rdma_stats;
struct ocbb_data_stc ocbb_info;
struct temperature_status_stc temp_info;
struct resource_info resource;
struct bist_nvm_image_att nvm_image_att;
struct mdump_config_stc mdump_config;
/* ... */
};
@ -896,9 +1010,14 @@ struct public_drv_mb {
#define DRV_MSG_CODE_NIG_DRAIN 0x30000000
/* DRV_MB Param: driver version supp, FW_MB param: MFW version supp,
* data: struct resource_info
*/
#define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000
#define DRV_MSG_CODE_INITIATE_FLR 0x02000000
/*deprecated don't use*/
#define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000
#define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000
#define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
#define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000
#define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000
@ -928,9 +1047,16 @@ struct public_drv_mb {
#define DRV_MSG_CODE_GET_STATS 0x00130000
#define DRV_MSG_CODE_STATS_TYPE_LAN 1
#define DRV_MSG_CODE_STATS_TYPE_FCOE 2
#define DRV_MSG_CODE_STATS_TYPE_ISCSI 3
#define DRV_MSG_CODE_STATS_TYPE_RDMA 4
#define DRV_MSG_CODE_OCBB_DATA 0x00180000
#define DRV_MSG_CODE_SET_BW 0x00190000
#define BW_MAX_MASK 0x000000ff
#define BW_MAX_SHIFT 0
#define BW_MIN_MASK 0x0000ff00
#define BW_MIN_SHIFT 8
#define DRV_MSG_CODE_MASK_PARITIES 0x001a0000
#define DRV_MSG_CODE_INDUCE_FAILURE 0x001b0000
#define DRV_MSG_FAN_FAILURE_TYPE (1 << 0)
@ -938,17 +1064,73 @@ struct public_drv_mb {
#define DRV_MSG_CODE_GPIO_READ 0x001c0000
#define DRV_MSG_CODE_GPIO_WRITE 0x001d0000
#define DRV_MSG_CODE_GPIO_INFO 0x00270000
/* Param: [0:15] - gpio number */
#define DRV_MSG_CODE_GPIO_INFO 0x00270000
/* Param: [0:7] - test enum, [8:15] - image index, [16:31] - reserved */
#define DRV_MSG_CODE_BIST_TEST 0x001e0000
#define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000
#define DRV_MSG_CODE_GET_TEMPERATURE 0x001f0000
#define DRV_MSG_CODE_SET_LED_MODE 0x00200000
#define DRV_MSG_CODE_TIMESTAMP 0x00210000
/* drv_data[7:0] - EPOC in seconds, drv_data[15:8] -
* driver version (MAJ MIN BUILD SUB)
*/
#define DRV_MSG_CODE_TIMESTAMP 0x00210000
/* This is an empty mailbox just return OK*/
#define DRV_MSG_CODE_EMPTY_MB 0x00220000
/* Param[0:4] - resource number (0-31), Param[5:7] - opcode,
* param[15:8] - age
*/
#define DRV_MSG_CODE_RESOURCE_CMD 0x00230000
#define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000
#define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000
/* request resource ownership with default aging */
#define RESOURCE_OPCODE_REQ 1
/* request resource ownership without aging */
#define RESOURCE_OPCODE_REQ_WO_AGING 2
/* request resource ownership with specific aging timer (in seconds) */
#define RESOURCE_OPCODE_REQ_W_AGING 3
#define RESOURCE_OPCODE_RELEASE 4 /* release resource */
#define RESOURCE_OPCODE_FORCE_RELEASE 5 /* force resource release */
/* resource is free and granted to requester */
#define RESOURCE_OPCODE_GNT 1
/* resource is busy, param[7:0] indicates owner as follow 0-15 = PF0-15,
* 16 = MFW, 17 = diag over serial
*/
#define RESOURCE_OPCODE_BUSY 2
/* indicate release request was acknowledged */
#define RESOURCE_OPCODE_RELEASED 3
/* indicate release request was previously received by other owner */
#define RESOURCE_OPCODE_RELEASED_PREVIOUS 4
/* indicate wrong owner during release */
#define RESOURCE_OPCODE_WRONG_OWNER 5
#define RESOURCE_OPCODE_UNKNOWN_CMD 255
/* dedicate resource 0 for dump */
#define RESOURCE_DUMP (1 << 0)
#define DRV_MSG_CODE_GET_MBA_VERSION 0x00240000 /* Get MBA version */
/* Send crash dump commands with param[3:0] - opcode */
#define DRV_MSG_CODE_MDUMP_CMD 0x00250000
#define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f
/* acknowledge reception of error indication */
#define DRV_MSG_CODE_MDUMP_ACK 0x01
/* set epoc and personality as follow: drv_data[3:0] - epoch,
* drv_data[7:4] - personality
*/
#define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02
/* trigger crash dump procedure */
#define DRV_MSG_CODE_MDUMP_TRIGGER 0x03
/* Request valid logs and config words */
#define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04
/* Set triggers mask. drv_mb_param should indicate (bitwise) which trigger
* enabled
*/
#define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05
#define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 /* Clear all logs */
#define DRV_MSG_CODE_MEM_ECC_EVENTS 0x00260000 /* Param: None */
#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
@ -1019,7 +1201,11 @@ struct public_drv_mb {
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_SHIFT 0
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_MASK 0x000000FF
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_NONE (1 << 0)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_IP_ACQUIRED (1 << 1)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS (1 << 1)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_TRARGET_FOUND (1 << 2)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_ISCSI_CHAP_SUCCESS (1 << 3)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_FCOE_LUN_FOUND (1 << 3)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_LOGGED_INTO_TGT (1 << 4)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_IMG_DOWNLOADED (1 << 5)
#define DRV_MB_PARAM_OV_UPDATE_BOOT_PROG_OS_HANDOFF (1 << 6)
@ -1063,28 +1249,27 @@ struct public_drv_mb {
#define DRV_MB_PARAM_GPIO_NUMBER_MASK 0x0000FFFF
#define DRV_MB_PARAM_GPIO_VALUE_SHIFT 16
#define DRV_MB_PARAM_GPIO_VALUE_MASK 0xFFFF0000
#define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16
#define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000
#define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24
#define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000
#define DRV_MB_PARAM_GPIO_DIRECTION_SHIFT 16
#define DRV_MB_PARAM_GPIO_DIRECTION_MASK 0x00FF0000
#define DRV_MB_PARAM_GPIO_CTRL_SHIFT 24
#define DRV_MB_PARAM_GPIO_CTRL_MASK 0xFF000000
/* Resource Allocation params - Driver version support*/
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
#define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
#define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
#define DRV_MB_PARAM_BIST_UNKNOWN_TEST 0
#define DRV_MB_PARAM_BIST_REGISTER_TEST 1
#define DRV_MB_PARAM_BIST_CLOCK_TEST 2
#define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3
#define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4
#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
#define DRV_MB_PARAM_BIST_RC_PASSED 1
#define DRV_MB_PARAM_BIST_RC_FAILED 2
#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
#define DRV_MB_PARAM_BIST_RC_UNKNOWN 0
#define DRV_MB_PARAM_BIST_RC_PASSED 1
#define DRV_MB_PARAM_BIST_RC_FAILED 2
#define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3
#define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0
#define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF
@ -1117,6 +1302,10 @@ struct public_drv_mb {
#define FW_MSG_CODE_UPDATE_DRIVER_STATE_DONE 0x31000000
#define FW_MSG_CODE_DRV_MSG_CODE_BW_UPDATE_DONE 0x32000000
#define FW_MSG_CODE_DRV_MSG_CODE_MTU_SIZE_DONE 0x33000000
#define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000
#define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000
#define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000
#define FW_MSG_CODE_RESOURCE_ALLOC_GEN_ERR 0x37000000
#define FW_MSG_CODE_NIG_DRAIN_DONE 0x30000000
#define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
#define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000
@ -1169,10 +1358,24 @@ struct public_drv_mb {
#define FW_MSG_CODE_GPIO_CTRL_ERR 0x00020000
#define FW_MSG_CODE_GPIO_INVALID 0x000f0000
#define FW_MSG_CODE_GPIO_INVALID_VALUE 0x00050000
#define FW_MSG_CODE_BIST_TEST_INVALID 0x000f0000
/* mdump related response codes */
#define FW_MSG_CODE_MDUMP_NO_IMAGE_FOUND 0x00010000
#define FW_MSG_CODE_MDUMP_ALLOC_FAILED 0x00020000
#define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000
#define FW_MSG_CODE_MDUMP_IN_PROGRESS 0x00040000
#define FW_MSG_CODE_MDUMP_WRITE_FAILED 0x00050000
#define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
u32 fw_mb_param;
/* Resource Allocation params - MFW version support*/
#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000
#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16
#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF
#define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0
u32 drv_pulse_mb;
#define DRV_PULSE_SEQ_MASK 0x00007fff
@ -1232,6 +1435,7 @@ enum MFW_DRV_MSG_TYPE {
MFW_DRV_MSG_GET_RDMA_STATS,
MFW_DRV_MSG_FAILURE_DETECTED,
MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED,
MFW_DRV_MSG_MAX
};

606
drivers/net/qede/base/nvm_cfg.h
View File

@ -13,7 +13,7 @@
* Description: NVM config file - Generated file from nvm cfg excel.
* DO NOT MODIFY !!!
*
* Created: 1/14/2016
* Created: 5/9/2016
*
****************************************************************************/
@ -84,8 +84,11 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_ASPM_SUPPORT_MASK 0x00000018
#define NVM_CFG1_GLOB_ASPM_SUPPORT_OFFSET 3
#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_ENABLED 0x0
#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_DISABLED 0x1
#define NVM_CFG1_GLOB_ASPM_SUPPORT_L1_DISABLED 0x2
#define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK 0x00000020
#define NVM_CFG1_GLOB_ASPM_SUPPORT_L0S_L1_DISABLED 0x3
#define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_MASK \
0x00000020
#define NVM_CFG1_GLOB_RESERVED_MPREVENT_PCIE_L1_MENTRY_OFFSET 5
#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_MASK 0x000003C0
#define NVM_CFG1_GLOB_PCIE_G2_TX_AMPLITUDE_OFFSET 6
@ -101,10 +104,9 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_WWN_NODE_PREFIX1_OFFSET 21
#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_MASK 0x60000000
#define NVM_CFG1_GLOB_NCSI_PACKAGE_ID_OFFSET 29
/* Set the duration, in seconds, fan failure signal should be
* sampled
*/
#define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK 0x80000000
/* Set the duration, in sec, fan failure signal should be sampled */
#define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_MASK \
0x80000000
#define NVM_CFG1_GLOB_RESERVED_FAN_FAILURE_DURATION_OFFSET 31
u32 mgmt_traffic; /* 0x28 */
#define NVM_CFG1_GLOB_RESERVED60_MASK 0x00000001
@ -132,27 +134,28 @@ struct nvm_cfg1_glob {
u32 core_cfg; /* 0x2C */
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X40G 0x0
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X50G 0x1
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X100G 0x2
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_F 0x3
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X10G_E 0x4
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_4X20G 0x5
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X40G 0xB
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_2X25G 0xC
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_DE_1X25G 0xD
#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_MASK 0x00000100
#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_OFFSET 8
#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_DISABLED 0x0
#define NVM_CFG1_GLOB_EAGLE_ENFORCE_TX_FIR_CFG_ENABLED 0x1
#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_MASK 0x00000200
#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_OFFSET 9
#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_DISABLED 0x0
#define NVM_CFG1_GLOB_FALCON_ENFORCE_TX_FIR_CFG_ENABLED 0x1
#define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_MASK 0x0003FC00
#define NVM_CFG1_GLOB_EAGLE_CORE_ADDR_OFFSET 10
#define NVM_CFG1_GLOB_FALCON_CORE_ADDR_MASK 0x03FC0000
#define NVM_CFG1_GLOB_FALCON_CORE_ADDR_OFFSET 18
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD
#define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE
#define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_MASK 0x00000100
#define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_OFFSET 8
#define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_DISABLED 0x0
#define NVM_CFG1_GLOB_MPS10_ENFORCE_TX_FIR_CFG_ENABLED 0x1
#define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_MASK 0x00000200
#define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_OFFSET 9
#define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_DISABLED 0x0
#define NVM_CFG1_GLOB_MPS25_ENFORCE_TX_FIR_CFG_ENABLED 0x1
#define NVM_CFG1_GLOB_MPS10_CORE_ADDR_MASK 0x0003FC00
#define NVM_CFG1_GLOB_MPS10_CORE_ADDR_OFFSET 10
#define NVM_CFG1_GLOB_MPS25_CORE_ADDR_MASK 0x03FC0000
#define NVM_CFG1_GLOB_MPS25_CORE_ADDR_OFFSET 18
#define NVM_CFG1_GLOB_AVS_MODE_MASK 0x1C000000
#define NVM_CFG1_GLOB_AVS_MODE_OFFSET 26
#define NVM_CFG1_GLOB_AVS_MODE_CLOSE_LOOP 0x0
@ -209,7 +212,7 @@ struct nvm_cfg1_glob {
/* Maximum advertised pcie link width */
#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_MASK 0x000F0000
#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_OFFSET 16
#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_16_LANES 0x0
#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_BB_16_LANES 0x0
#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_1_LANE 0x1
#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_2_LANES 0x2
#define NVM_CFG1_GLOB_MAX_LINK_WIDTH_4_LANES 0x3
@ -283,7 +286,7 @@ struct nvm_cfg1_glob {
/* Set max. count for over operational temperature */
#define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_MASK 0xFF000000
#define NVM_CFG1_GLOB_MAX_COUNT_OPER_THRESHOLD_OFFSET 24
u32 eagle_preemphasis; /* 0x40 */
u32 mps10_preemphasis; /* 0x40 */
#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
@ -292,7 +295,7 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
u32 eagle_driver_current; /* 0x44 */
u32 mps10_driver_current; /* 0x44 */
#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
@ -301,7 +304,7 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_LANE2_AMP_OFFSET 16
#define NVM_CFG1_GLOB_LANE3_AMP_MASK 0xFF000000
#define NVM_CFG1_GLOB_LANE3_AMP_OFFSET 24
u32 falcon_preemphasis; /* 0x48 */
u32 mps25_preemphasis; /* 0x48 */
#define NVM_CFG1_GLOB_LANE0_PREEMP_MASK 0x000000FF
#define NVM_CFG1_GLOB_LANE0_PREEMP_OFFSET 0
#define NVM_CFG1_GLOB_LANE1_PREEMP_MASK 0x0000FF00
@ -310,7 +313,7 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_LANE2_PREEMP_OFFSET 16
#define NVM_CFG1_GLOB_LANE3_PREEMP_MASK 0xFF000000
#define NVM_CFG1_GLOB_LANE3_PREEMP_OFFSET 24
u32 falcon_driver_current; /* 0x4C */
u32 mps25_driver_current; /* 0x4C */
#define NVM_CFG1_GLOB_LANE0_AMP_MASK 0x000000FF
#define NVM_CFG1_GLOB_LANE0_AMP_OFFSET 0
#define NVM_CFG1_GLOB_LANE1_AMP_MASK 0x0000FF00
@ -392,12 +395,34 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_BAR2_SIZE_256M 0xD
#define NVM_CFG1_GLOB_BAR2_SIZE_512M 0xE
#define NVM_CFG1_GLOB_BAR2_SIZE_1G 0xF
/* Set the duration, in seconds, fan failure signal should be
* sampled
*/
/* Set the duration, in secs, fan failure signal should be sampled */
#define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_MASK 0x0000F000
#define NVM_CFG1_GLOB_FAN_FAILURE_DURATION_OFFSET 12
u32 eagle_txfir_main; /* 0x5C */
/* This field defines the board total budget for bar2 when disabled
* the regular bar size is used.
*/
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_MASK 0x00FF0000
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_OFFSET 16
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_DISABLED 0x0
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64K 0x1
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128K 0x2
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256K 0x3
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512K 0x4
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1M 0x5
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_2M 0x6
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_4M 0x7
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_8M 0x8
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_16M 0x9
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_32M 0xA
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_64M 0xB
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_128M 0xC
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_256M 0xD
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_512M 0xE
#define NVM_CFG1_GLOB_BAR2_TOTAL_BUDGET_1G 0xF
/* Enable/Disable Crash dump triggers */
#define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_MASK 0xFF000000
#define NVM_CFG1_GLOB_CRASH_DUMP_TRIGGER_ENABLE_OFFSET 24
u32 mps10_txfir_main; /* 0x5C */
#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
@ -406,7 +431,7 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
u32 eagle_txfir_post; /* 0x60 */
u32 mps10_txfir_post; /* 0x60 */
#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
@ -415,7 +440,7 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_LANE2_TXFIR_POST_OFFSET 16
#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_MASK 0xFF000000
#define NVM_CFG1_GLOB_LANE3_TXFIR_POST_OFFSET 24
u32 falcon_txfir_main; /* 0x64 */
u32 mps25_txfir_main; /* 0x64 */
#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_MASK 0x000000FF
#define NVM_CFG1_GLOB_LANE0_TXFIR_MAIN_OFFSET 0
#define NVM_CFG1_GLOB_LANE1_TXFIR_MAIN_MASK 0x0000FF00
@ -424,7 +449,7 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_LANE2_TXFIR_MAIN_OFFSET 16
#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_MASK 0xFF000000
#define NVM_CFG1_GLOB_LANE3_TXFIR_MAIN_OFFSET 24
u32 falcon_txfir_post; /* 0x68 */
u32 mps25_txfir_post; /* 0x68 */
#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_MASK 0x000000FF
#define NVM_CFG1_GLOB_LANE0_TXFIR_POST_OFFSET 0
#define NVM_CFG1_GLOB_LANE1_TXFIR_POST_MASK 0x0000FF00
@ -463,6 +488,14 @@ struct nvm_cfg1_glob {
u32 generic_cont1; /* 0x78 */
#define NVM_CFG1_GLOB_AVS_DAC_CODE_MASK 0x000003FF
#define NVM_CFG1_GLOB_AVS_DAC_CODE_OFFSET 0
#define NVM_CFG1_GLOB_LANE0_SWAP_MASK 0x00000C00
#define NVM_CFG1_GLOB_LANE0_SWAP_OFFSET 10
#define NVM_CFG1_GLOB_LANE1_SWAP_MASK 0x00003000
#define NVM_CFG1_GLOB_LANE1_SWAP_OFFSET 12
#define NVM_CFG1_GLOB_LANE2_SWAP_MASK 0x0000C000
#define NVM_CFG1_GLOB_LANE2_SWAP_OFFSET 14
#define NVM_CFG1_GLOB_LANE3_SWAP_MASK 0x00030000
#define NVM_CFG1_GLOB_LANE3_SWAP_OFFSET 16
u32 mbi_version; /* 0x7C */
#define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF
#define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0
@ -512,6 +545,10 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_I2C_MUX_SEL_GPIO__GPIO31 0x20
u32 device_capabilities; /* 0x88 */
#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1
#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2
#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4
#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8
#define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_IWARP 0x10
u32 power_dissipated; /* 0x8C */
#define NVM_CFG1_GLOB_POWER_DIS_D0_MASK 0x000000FF
#define NVM_CFG1_GLOB_POWER_DIS_D0_OFFSET 0
@ -531,7 +568,17 @@ struct nvm_cfg1_glob {
#define NVM_CFG1_GLOB_POWER_CONS_D3_MASK 0xFF000000
#define NVM_CFG1_GLOB_POWER_CONS_D3_OFFSET 24
u32 efi_version; /* 0x94 */
u32 reserved[42]; /* 0x98 */
u32 multi_network_modes_capability; /* 0x98 */
#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X10G 0x1
#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X25G 0x2
#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X25G 0x4
#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_4X25G 0x8
#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_1X40G 0x10
#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X40G 0x20
#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_2X50G 0x40
#define NVM_CFG1_GLOB_MULTI_NETWORK_MODES_CAPABILITY_BB_1X100G \
0x80
u32 reserved[41]; /* 0x9C */
};
struct nvm_cfg1_path {
@ -560,6 +607,9 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_LED_MODE_PHY10 0xD
#define NVM_CFG1_PORT_LED_MODE_PHY11 0xE
#define NVM_CFG1_PORT_LED_MODE_PHY12 0xF
#define NVM_CFG1_PORT_LED_MODE_BREAKOUT 0x10
#define NVM_CFG1_PORT_ROCE_PRIORITY_MASK 0x0000FF00
#define NVM_CFG1_PORT_ROCE_PRIORITY_OFFSET 8
#define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000
#define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16
#define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0
@ -569,6 +619,8 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000
#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20
#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1
#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2
#define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4
u32 pcie_cfg; /* 0xC */
#define NVM_CFG1_PORT_RESERVED15_MASK 0x00000007
#define NVM_CFG1_PORT_RESERVED15_OFFSET 0
@ -589,7 +641,7 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20
#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_100G 0x40
#define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_MASK 0xFFFF0000
#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_OFFSET 16
#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_1G 0x1
@ -597,7 +649,7 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_50G 0x20
#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_100G 0x40
#define NVM_CFG1_PORT_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
u32 link_settings; /* 0x18 */
#define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F
#define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0
@ -607,7 +659,7 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_DRV_LINK_SPEED_100G 0x7
#define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8
#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070
#define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4
@ -622,26 +674,29 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_MFW_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MFW_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MFW_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MFW_LINK_SPEED_100G 0x7
#define NVM_CFG1_PORT_MFW_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MFW_LINK_SPEED_SMARTLINQ 0x8
#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_MASK 0x00003800
#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_OFFSET 11
#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_AUTONEG 0x1
#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_RX 0x2
#define NVM_CFG1_PORT_MFW_FLOW_CONTROL_TX 0x4
#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK 0x00004000
#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_MASK \
0x00004000
#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_OFFSET 14
#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED 0x0
#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED 0x1
#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_DISABLED \
0x0
#define NVM_CFG1_PORT_OPTIC_MODULE_VENDOR_ENFORCEMENT_ENABLED \
0x1
#define NVM_CFG1_PORT_AN_25G_50G_OUI_MASK 0x00018000
#define NVM_CFG1_PORT_AN_25G_50G_OUI_OFFSET 15
#define NVM_CFG1_PORT_AN_25G_50G_OUI_CONSORTIUM 0x0
#define NVM_CFG1_PORT_AN_25G_50G_OUI_BAM 0x1
#define NVM_CFG1_PORT_FEC_FORCE_MODE_MASK 0x000E0000
#define NVM_CFG1_PORT_FEC_FORCE_MODE_OFFSET 17
#define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_NONE 0x0
#define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_FIRECODE 0x1
#define NVM_CFG1_PORT_FEC_FORCE_MODE_FEC_FORCE_RS 0x2
#define NVM_CFG1_PORT_FEC_FORCE_MODE_NONE 0x0
#define NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE 0x1
#define NVM_CFG1_PORT_FEC_FORCE_MODE_RS 0x2
u32 phy_cfg; /* 0x1C */
#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_MASK 0x0000FFFF
#define NVM_CFG1_PORT_OPTIONAL_LINK_MODES_OFFSET 0
@ -671,9 +726,9 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_AN_MODE_CL73 0x1
#define NVM_CFG1_PORT_AN_MODE_CL37 0x2
#define NVM_CFG1_PORT_AN_MODE_CL73_BAM 0x3
#define NVM_CFG1_PORT_AN_MODE_CL37_BAM 0x4
#define NVM_CFG1_PORT_AN_MODE_HPAM 0x5
#define NVM_CFG1_PORT_AN_MODE_SGMII 0x6
#define NVM_CFG1_PORT_AN_MODE_BB_CL37_BAM 0x4
#define NVM_CFG1_PORT_AN_MODE_BB_HPAM 0x5
#define NVM_CFG1_PORT_AN_MODE_BB_SGMII 0x6
u32 mgmt_traffic; /* 0x20 */
#define NVM_CFG1_PORT_RESERVED61_MASK 0x0000000F
#define NVM_CFG1_PORT_RESERVED61_OFFSET 0
@ -711,9 +766,10 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_100G 0x7
#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_PREBOOT_LINK_SPEED_SMARTLINQ 0x8
#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK 0x00E00000
#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_MASK \
0x00E00000
#define NVM_CFG1_PORT_RESERVED__M_MBA_BOOT_RETRY_COUNT_OFFSET 21
u32 mba_cfg2; /* 0x2C */
#define NVM_CFG1_PORT_RESERVED65_MASK 0x0000FFFF
@ -738,7 +794,7 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_25G 0x8
#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_40G 0x10
#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_50G 0x20
#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_100G 0x40
#define NVM_CFG1_PORT_LANE_LED_SPD__SEL_BB_100G 0x40
u32 transceiver_00; /* 0x40 */
/* Define for mapping of transceiver signal module absent */
#define NVM_CFG1_PORT_TRANS_MODULE_ABS_MASK 0x000000FF
@ -784,6 +840,10 @@ struct nvm_cfg1_port {
u32 device_ids; /* 0x44 */
#define NVM_CFG1_PORT_ETH_DID_SUFFIX_MASK 0x000000FF
#define NVM_CFG1_PORT_ETH_DID_SUFFIX_OFFSET 0
#define NVM_CFG1_PORT_FCOE_DID_SUFFIX_MASK 0x0000FF00
#define NVM_CFG1_PORT_FCOE_DID_SUFFIX_OFFSET 8
#define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_MASK 0x00FF0000
#define NVM_CFG1_PORT_ISCSI_DID_SUFFIX_OFFSET 16
#define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_MASK 0xFF000000
#define NVM_CFG1_PORT_RESERVED_DID_SUFFIX_OFFSET 24
u32 board_cfg; /* 0x48 */
@ -833,7 +893,391 @@ struct nvm_cfg1_port {
#define NVM_CFG1_PORT_TX_DISABLE_GPIO29 0x1E
#define NVM_CFG1_PORT_TX_DISABLE_GPIO30 0x1F
#define NVM_CFG1_PORT_TX_DISABLE_GPIO31 0x20
u32 reserved[131]; /* 0x4C */
u32 mnm_10g_cap; /* 0x4C */
#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_MASK \
0x0000FFFF
#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
#define \
NVM_CFG1_PORT_MNM_10G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_MASK \
0xFFFF0000
#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
16
#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
#define \
NVM_CFG1_PORT_MNM_10G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
u32 mnm_10g_ctrl; /* 0x50 */
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_MASK 0x0000000F
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_OFFSET 0
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_10G_DRV_LINK_SPEED_SMARTLINQ 0x8
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_MASK 0x000000F0
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_OFFSET 4
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_10G_MFW_LINK_SPEED_SMARTLINQ 0x8
/* This field defines the board technology
* (backpane,transceiver,external PHY)
*/
#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MASK 0x0000FF00
#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_OFFSET 8
#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_UNDEFINED 0x0
#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE 0x1
#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_BACKPLANE 0x2
#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_EXT_PHY 0x3
#define NVM_CFG1_PORT_MNM_10G_PORT_TYPE_MODULE_SLAVE 0x4
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_MASK \
0x00FF0000
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_OFFSET 16
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_BYPASS 0x0
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR 0x2
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR2 0x3
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_KR4 0x4
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XFI 0x8
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SFI 0x9
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_1000X 0xB
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_SGMII 0xC
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLAUI 0x11
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_XLPPI 0x12
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CAUI 0x21
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_CPPI 0x22
#define NVM_CFG1_PORT_MNM_10G_SERDES_NET_INTERFACE_25GAUI 0x31
#define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_MASK 0xFF000000
#define NVM_CFG1_PORT_MNM_10G_ETH_DID_SUFFIX_OFFSET 24
u32 mnm_10g_misc; /* 0x54 */
#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_MASK 0x00000007
#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_OFFSET 0
#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_NONE 0x0
#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_FIRECODE 0x1
#define NVM_CFG1_PORT_MNM_10G_FEC_FORCE_MODE_RS 0x2
u32 mnm_25g_cap; /* 0x58 */
#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_MASK \
0x0000FFFF
#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
#define \
NVM_CFG1_PORT_MNM_25G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_MASK \
0xFFFF0000
#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
16
#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
#define \
NVM_CFG1_PORT_MNM_25G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
u32 mnm_25g_ctrl; /* 0x5C */
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_MASK 0x0000000F
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_OFFSET 0
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_25G_DRV_LINK_SPEED_SMARTLINQ 0x8
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_MASK 0x000000F0
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_OFFSET 4
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_25G_MFW_LINK_SPEED_SMARTLINQ 0x8
/* This field defines the board technology
* (backpane,transceiver,external PHY)
*/
#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MASK 0x0000FF00
#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_OFFSET 8
#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_UNDEFINED 0x0
#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE 0x1
#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_BACKPLANE 0x2
#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_EXT_PHY 0x3
#define NVM_CFG1_PORT_MNM_25G_PORT_TYPE_MODULE_SLAVE 0x4
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_MASK \
0x00FF0000
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_OFFSET 16
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_BYPASS 0x0
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR 0x2
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR2 0x3
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_KR4 0x4
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XFI 0x8
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SFI 0x9
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_1000X 0xB
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_SGMII 0xC
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLAUI 0x11
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_XLPPI 0x12
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CAUI 0x21
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_CPPI 0x22
#define NVM_CFG1_PORT_MNM_25G_SERDES_NET_INTERFACE_25GAUI 0x31
#define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_MASK 0xFF000000
#define NVM_CFG1_PORT_MNM_25G_ETH_DID_SUFFIX_OFFSET 24
u32 mnm_25g_misc; /* 0x60 */
#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_MASK 0x00000007
#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_OFFSET 0
#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_NONE 0x0
#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_FIRECODE 0x1
#define NVM_CFG1_PORT_MNM_25G_FEC_FORCE_MODE_RS 0x2
u32 mnm_40g_cap; /* 0x64 */
#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_MASK \
0x0000FFFF
#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
#define \
NVM_CFG1_PORT_MNM_40G_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40
#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_MASK \
0xFFFF0000
#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
16
#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
#define \
NVM_CFG1_PORT_MNM_40G_MFW_SPEED_CAPABILITY_MASK_BB_100G 0x40
u32 mnm_40g_ctrl; /* 0x68 */
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_MASK 0x0000000F
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_OFFSET 0
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_40G_DRV_LINK_SPEED_SMARTLINQ 0x8
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_MASK 0x000000F0
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_OFFSET 4
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_40G_MFW_LINK_SPEED_SMARTLINQ 0x8
/* This field defines the board technology
* (backpane,transceiver,external PHY)
*/
#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MASK 0x0000FF00
#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_OFFSET 8
#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_UNDEFINED 0x0
#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE 0x1
#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_BACKPLANE 0x2
#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_EXT_PHY 0x3
#define NVM_CFG1_PORT_MNM_40G_PORT_TYPE_MODULE_SLAVE 0x4
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_MASK \
0x00FF0000
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_OFFSET 16
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_BYPASS 0x0
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR 0x2
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR2 0x3
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_KR4 0x4
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XFI 0x8
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SFI 0x9
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_1000X 0xB
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_SGMII 0xC
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLAUI 0x11
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_XLPPI 0x12
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CAUI 0x21
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_CPPI 0x22
#define NVM_CFG1_PORT_MNM_40G_SERDES_NET_INTERFACE_25GAUI 0x31
#define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_MASK 0xFF000000
#define NVM_CFG1_PORT_MNM_40G_ETH_DID_SUFFIX_OFFSET 24
u32 mnm_40g_misc; /* 0x6C */
#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_MASK 0x00000007
#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_OFFSET 0
#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_NONE 0x0
#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_FIRECODE 0x1
#define NVM_CFG1_PORT_MNM_40G_FEC_FORCE_MODE_RS 0x2
u32 mnm_50g_cap; /* 0x70 */
#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_MASK \
0x0000FFFF
#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_OFFSET 0
#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_50G 0x20
#define \
NVM_CFG1_PORT_MNM_50G_DRV_SPEED_CAPABILITY_MASK_BB_100G \
0x40
#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_MASK \
0xFFFF0000
#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_OFFSET \
16
#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_50G 0x20
#define \
NVM_CFG1_PORT_MNM_50G_MFW_SPEED_CAPABILITY_MASK_BB_100G \
0x40
u32 mnm_50g_ctrl; /* 0x74 */
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_MASK 0x0000000F
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_OFFSET 0
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_50G_DRV_LINK_SPEED_SMARTLINQ 0x8
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_MASK 0x000000F0
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_OFFSET 4
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_50G_MFW_LINK_SPEED_SMARTLINQ 0x8
/* This field defines the board technology
* (backpane,transceiver,external PHY)
*/
#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MASK 0x0000FF00
#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_OFFSET 8
#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_UNDEFINED 0x0
#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE 0x1
#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_BACKPLANE 0x2
#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_EXT_PHY 0x3
#define NVM_CFG1_PORT_MNM_50G_PORT_TYPE_MODULE_SLAVE 0x4
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_MASK \
0x00FF0000
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_OFFSET 16
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_BYPASS 0x0
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR 0x2
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR2 0x3
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_KR4 0x4
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XFI 0x8
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SFI 0x9
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_1000X 0xB
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_SGMII 0xC
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLAUI 0x11
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_XLPPI 0x12
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CAUI 0x21
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_CPPI 0x22
#define NVM_CFG1_PORT_MNM_50G_SERDES_NET_INTERFACE_25GAUI 0x31
#define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_MASK 0xFF000000
#define NVM_CFG1_PORT_MNM_50G_ETH_DID_SUFFIX_OFFSET 24
u32 mnm_50g_misc; /* 0x78 */
#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_MASK 0x00000007
#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_OFFSET 0
#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_NONE 0x0
#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_FIRECODE 0x1
#define NVM_CFG1_PORT_MNM_50G_FEC_FORCE_MODE_RS 0x2
u32 mnm_100g_cap; /* 0x7C */
#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_MASK \
0x0000FFFF
#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_OFFSET 0
#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_50G 0x20
#define NVM_CFG1_PORT_MNM_100G_DRV_SPEED_CAP_MASK_BB_100G 0x40
#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_MASK \
0xFFFF0000
#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_OFFSET 16
#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_1G 0x1
#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_10G 0x2
#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_25G 0x8
#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_40G 0x10
#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_50G 0x20
#define NVM_CFG1_PORT_MNM_100G_MFW_SPEED_CAP_MASK_BB_100G 0x40
u32 mnm_100g_ctrl; /* 0x80 */
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_MASK 0x0000000F
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_OFFSET 0
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_100G_DRV_LINK_SPEED_SMARTLINQ 0x8
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_MASK 0x000000F0
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_OFFSET 4
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_AUTONEG 0x0
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_1G 0x1
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_10G 0x2
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_25G 0x4
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_40G 0x5
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_50G 0x6
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_BB_100G 0x7
#define NVM_CFG1_PORT_MNM_100G_MFW_LINK_SPEED_SMARTLINQ 0x8
/* This field defines the board technology
* (backpane,transceiver,external PHY)
*/
#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MASK 0x0000FF00
#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_OFFSET 8
#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_UNDEFINED 0x0
#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE 0x1
#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_BACKPLANE 0x2
#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_EXT_PHY 0x3
#define NVM_CFG1_PORT_MNM_100G_PORT_TYPE_MODULE_SLAVE 0x4
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_MASK \
0x00FF0000
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_OFFSET 16
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_BYPASS 0x0
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR 0x2
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR2 0x3
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_KR4 0x4
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XFI 0x8
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SFI 0x9
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_1000X 0xB
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_SGMII 0xC
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLAUI 0x11
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_XLPPI 0x12
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CAUI 0x21
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_CPPI 0x22
#define NVM_CFG1_PORT_MNM_100G_SERDES_NET_INTERFACE_25GAUI 0x31
#define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_MASK 0xFF000000
#define NVM_CFG1_PORT_MNM_100G_ETH_DID_SUFFIX_OFFSET 24
u32 mnm_100g_misc; /* 0x84 */
#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_MASK 0x00000007
#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_OFFSET 0
#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_NONE 0x0
#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_FIRECODE 0x1
#define NVM_CFG1_PORT_MNM_100G_FEC_FORCE_MODE_RS 0x2
u32 reserved[116]; /* 0x88 */
};
struct nvm_cfg1_func {
@ -857,12 +1301,17 @@ struct nvm_cfg1_func {
#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_MASK 0x00000007
#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_OFFSET 0
#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_PXE 0x0
#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_ISCSI_BOOT 0x3
#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_FCOE_BOOT 0x4
#define NVM_CFG1_FUNC_PREBOOT_BOOT_PROTOCOL_NONE 0x7
#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_MASK 0x0007FFF8
#define NVM_CFG1_FUNC_VF_PCI_DEVICE_ID_OFFSET 3
#define NVM_CFG1_FUNC_PERSONALITY_MASK 0x00780000
#define NVM_CFG1_FUNC_PERSONALITY_OFFSET 19
#define NVM_CFG1_FUNC_PERSONALITY_ETHERNET 0x0
#define NVM_CFG1_FUNC_PERSONALITY_ISCSI 0x1
#define NVM_CFG1_FUNC_PERSONALITY_FCOE 0x2
#define NVM_CFG1_FUNC_PERSONALITY_ROCE 0x3
#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_MASK 0x7F800000
#define NVM_CFG1_FUNC_BANDWIDTH_WEIGHT_OFFSET 23
#define NVM_CFG1_FUNC_PAUSE_ON_HOST_RING_MASK 0x80000000
@ -872,8 +1321,25 @@ struct nvm_cfg1_func {
u32 pci_cfg; /* 0x18 */
#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_MASK 0x0000007F
#define NVM_CFG1_FUNC_NUMBER_OF_VFS_PER_PF_OFFSET 0
#define NVM_CFG1_FUNC_RESERVESD12_MASK 0x00003F80
#define NVM_CFG1_FUNC_RESERVESD12_OFFSET 7
/* AH VF BAR2 size */
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_MASK 0x00003F80
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_OFFSET 7
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_DISABLED 0x0
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4K 0x1
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8K 0x2
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16K 0x3
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32K 0x4
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64K 0x5
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_128K 0x6
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_256K 0x7
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_512K 0x8
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_1M 0x9
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_2M 0xA
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_4M 0xB
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_8M 0xC
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_16M 0xD
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_32M 0xE
#define NVM_CFG1_FUNC_VF_PCI_BAR2_SIZE_64M 0xF
#define NVM_CFG1_FUNC_BAR1_SIZE_MASK 0x0003C000
#define NVM_CFG1_FUNC_BAR1_SIZE_OFFSET 14
#define NVM_CFG1_FUNC_BAR1_SIZE_DISABLED 0x0
@ -894,6 +1360,28 @@ struct nvm_cfg1_func {
#define NVM_CFG1_FUNC_BAR1_SIZE_1G 0xF
#define NVM_CFG1_FUNC_MAX_BANDWIDTH_MASK 0x03FC0000
#define NVM_CFG1_FUNC_MAX_BANDWIDTH_OFFSET 18
/* Hide function in npar mode */
#define NVM_CFG1_FUNC_FUNCTION_HIDE_MASK 0x04000000
#define NVM_CFG1_FUNC_FUNCTION_HIDE_OFFSET 26
#define NVM_CFG1_FUNC_FUNCTION_HIDE_DISABLED 0x0
#define NVM_CFG1_FUNC_FUNCTION_HIDE_ENABLED 0x1
/* AH BAR2 size (per function) */
#define NVM_CFG1_FUNC_BAR2_SIZE_MASK 0x78000000
#define NVM_CFG1_FUNC_BAR2_SIZE_OFFSET 27
#define NVM_CFG1_FUNC_BAR2_SIZE_DISABLED 0x0
#define NVM_CFG1_FUNC_BAR2_SIZE_1M 0x5
#define NVM_CFG1_FUNC_BAR2_SIZE_2M 0x6
#define NVM_CFG1_FUNC_BAR2_SIZE_4M 0x7
#define NVM_CFG1_FUNC_BAR2_SIZE_8M 0x8
#define NVM_CFG1_FUNC_BAR2_SIZE_16M 0x9
#define NVM_CFG1_FUNC_BAR2_SIZE_32M 0xA
#define NVM_CFG1_FUNC_BAR2_SIZE_64M 0xB
#define NVM_CFG1_FUNC_BAR2_SIZE_128M 0xC
#define NVM_CFG1_FUNC_BAR2_SIZE_256M 0xD
#define NVM_CFG1_FUNC_BAR2_SIZE_512M 0xE
#define NVM_CFG1_FUNC_BAR2_SIZE_1G 0xF
struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; /* 0x1C */
struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; /* 0x24 */
u32 preboot_generic_cfg; /* 0x2C */
#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_MASK 0x0000FFFF
#define NVM_CFG1_FUNC_PREBOOT_VLAN_VALUE_OFFSET 0

1
drivers/net/qede/qede_eth_if.c
View File

@ -246,6 +246,7 @@ qed_start_txq(struct ecore_dev *edev,
vport_id,
sb,
sb_index,
0 /* tc */,
pbl_addr, pbl_size, pp_doorbell);
if (rc) {

20
drivers/net/qede/qede_main.c
View File

@ -20,7 +20,7 @@ static uint8_t npar_tx_switching = 1;
char fw_file[PATH_MAX];
const char *QEDE_DEFAULT_FIRMWARE =
"/lib/firmware/qed/qed_init_values_zipped-8.7.7.0.bin";
"/lib/firmware/qed/qed_init_values_zipped-8.10.9.0.bin";
static void
qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params)
@ -44,6 +44,7 @@ qed_probe(struct ecore_dev *edev, struct rte_pci_device *pci_dev,
enum qed_protocol protocol, uint32_t dp_module,
uint8_t dp_level, bool is_vf)
{
struct ecore_hw_prepare_params hw_prepare_params;
struct qede_dev *qdev = (struct qede_dev *)edev;
int rc;
@ -51,11 +52,16 @@ qed_probe(struct ecore_dev *edev, struct rte_pci_device *pci_dev,
qdev->protocol = protocol;
if (is_vf) {
edev->b_is_vf = true;
edev->sriov_info.b_hw_channel = true;
edev->b_hw_channel = true; /* @DPDK */
}
ecore_init_dp(edev, dp_module, dp_level, NULL);
qed_init_pci(edev, pci_dev);
rc = ecore_hw_prepare(edev, ECORE_PCI_DEFAULT);
memset(&hw_prepare_params, 0, sizeof(hw_prepare_params));
hw_prepare_params.personality = ECORE_PCI_ETH;
hw_prepare_params.drv_resc_alloc = false;
hw_prepare_params.chk_reg_fifo = false;
rc = ecore_hw_prepare(edev, &hw_prepare_params);
if (rc) {
DP_ERR(edev, "hw prepare failed\n");
return rc;
@ -256,8 +262,9 @@ static int qed_slowpath_start(struct ecore_dev *edev,
/* Start the slowpath */
#ifdef CONFIG_ECORE_BINARY_FW
if (IS_PF(edev))
data = edev->firmware;
data = (const uint8_t *)edev->firmware + sizeof(u32);
#endif
allow_npar_tx_switching = npar_tx_switching ? true : false;
#ifdef QED_ENC_SUPPORTED
@ -346,7 +353,7 @@ qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)
if (IS_PF(edev)) {
ptt = ecore_ptt_acquire(ECORE_LEADING_HWFN(edev));
if (ptt) {
ecore_mcp_get_mfw_ver(edev, ptt,
ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt,
&dev_info->mfw_rev, NULL);
ecore_mcp_get_flash_size(ECORE_LEADING_HWFN(edev), ptt,
@ -361,7 +368,8 @@ qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)
ecore_ptt_release(ECORE_LEADING_HWFN(edev), ptt);
}
} else {
ecore_mcp_get_mfw_ver(edev, ptt, &dev_info->mfw_rev, NULL);
ecore_mcp_get_mfw_ver(ECORE_LEADING_HWFN(edev), ptt,
&dev_info->mfw_rev, NULL);
}
return 0;

4
drivers/net/qede/qede_rxtx.h
View File

@ -44,6 +44,10 @@
(bd)->addr.hi = rte_cpu_to_le_32(U64_HI(maddr)); \
(bd)->addr.lo = rte_cpu_to_le_32(U64_LO(maddr)); \
(bd)->nbytes = rte_cpu_to_le_16(len); \
/* FW 8.10.x specific change */ \
(bd)->data.bitfields = ((len) & \
ETH_TX_DATA_1ST_BD_PKT_LEN_MASK) \
<< ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT; \
} while (0)
#define CQE_HAS_VLAN(flags) \