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net/qede/base: add changes for debug data collection

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This patch adds base driver APIs required for debug data collection.
It adds support for dumping internal lookup tables(ilt), reading nvram
image, register definitions.

Signed-off-by: Rasesh Mody <rmody@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
This commit is contained in:
Rasesh Mody 2020-07-08 15:50:52 -07:00 committed by Ferruh Yigit
parent 519438f7c1
commit 2352f348c9
15 changed files with 1417 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
drivers/net/qede/base/bcm_osal.c
View File

@ -289,3 +289,9 @@ u32 qede_crc32(u32 crc, u8 *ptr, u32 length)
}
return crc;
}
void qed_set_platform_str(struct ecore_hwfn *p_hwfn,
char *buf_str, u32 buf_size)
{
snprintf(buf_str, buf_size, "%s.", rte_version());
}

8
drivers/net/qede/base/bcm_osal.h
View File

@ -8,6 +8,7 @@
#define __BCM_OSAL_H
#include <stdbool.h>
#include <time.h>
#include <rte_bitops.h>
#include <rte_byteorder.h>
#include <rte_spinlock.h>
@ -19,6 +20,7 @@
#include <rte_debug.h>
#include <rte_ether.h>
#include <rte_io.h>
#include <rte_version.h>
/* Forward declaration */
struct ecore_dev;
@ -450,7 +452,11 @@ u32 qede_crc32(u32 crc, u8 *ptr, u32 length);
#define OSAL_DIV_S64(a, b) ((a) / (b))
#define OSAL_LLDP_RX_TLVS(p_hwfn, tlv_buf, tlv_size) nothing
#define OSAL_GET_EPOCH(p_hwfn) 0
void qed_set_platform_str(struct ecore_hwfn *p_hwfn,
char *buf_str, u32 buf_size);
#define OSAL_SET_PLATFORM_STR(p_hwfn, buf_str, buf_size) \
qed_set_platform_str(p_hwfn, buf_str, buf_size)
#define OSAL_GET_EPOCH(p_hwfn) ((u32)time(NULL))
#define OSAL_DBG_ALLOC_USER_DATA(p_hwfn, user_data_ptr) (0)
#define OSAL_DB_REC_OCCURRED(p_hwfn) nothing

1
drivers/net/qede/base/common_hsi.h
View File

@ -145,6 +145,7 @@
#define NUM_OF_CONNECTION_TYPES (8)
#define NUM_OF_TASK_TYPES (8)
#define NUM_OF_LCIDS (320)
#define NUM_OF_LTIDS (320)
/* Global PXP windows (GTT) */
#define NUM_OF_GTT 19

58
drivers/net/qede/base/ecore.h
View File

@ -576,6 +576,12 @@ enum BAR_ID {
BAR_ID_1 /* Used for doorbells */
};
struct ecore_nvm_image_info {
u32 num_images;
struct bist_nvm_image_att *image_att;
bool valid;
};
struct ecore_hwfn {
struct ecore_dev *p_dev;
u8 my_id; /* ID inside the PF */
@ -701,6 +707,9 @@ struct ecore_hwfn {
*/
bool b_en_pacing;
/* Nvm images number and attributes */
struct ecore_nvm_image_info nvm_info;
struct phys_mem_desc *fw_overlay_mem;
/* @DPDK */
@ -714,26 +723,34 @@ enum ecore_mf_mode {
ECORE_MF_UFP,
};
enum ecore_dev_type {
ECORE_DEV_TYPE_BB,
ECORE_DEV_TYPE_AH,
};
/* @DPDK */
enum ecore_dbg_features {
DBG_FEATURE_GRC,
DBG_FEATURE_IDLE_CHK,
DBG_FEATURE_MCP_TRACE,
DBG_FEATURE_REG_FIFO,
DBG_FEATURE_IGU_FIFO,
DBG_FEATURE_PROTECTION_OVERRIDE,
DBG_FEATURE_FW_ASSERTS,
DBG_FEATURE_ILT,
DBG_FEATURE_NUM
};
struct ecore_dbg_feature {
u8 *dump_buf;
u32 buf_size;
u32 dumped_dwords;
};
enum qed_dbg_features {
DBG_FEATURE_BUS,
DBG_FEATURE_GRC,
DBG_FEATURE_IDLE_CHK,
DBG_FEATURE_MCP_TRACE,
DBG_FEATURE_REG_FIFO,
DBG_FEATURE_PROTECTION_OVERRIDE,
DBG_FEATURE_NUM
};
enum ecore_dev_type {
ECORE_DEV_TYPE_BB,
ECORE_DEV_TYPE_AH,
struct ecore_dbg_params {
struct ecore_dbg_feature features[DBG_FEATURE_NUM];
u8 engine_for_debug;
bool print_data;
};
struct ecore_dev {
@ -914,10 +931,12 @@ struct ecore_dev {
void *firmware;
u64 fw_len;
#endif
bool disable_ilt_dump;
/* @DPDK */
struct ecore_dbg_feature dbg_features[DBG_FEATURE_NUM];
u8 engine_for_debug;
struct ecore_dbg_params dbg_params;
osal_mutex_t dbg_lock;
};
enum ecore_hsi_def_type {
@ -1067,6 +1086,17 @@ enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);
enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);
/**
* @brief ecore_set_platform_str - Set the debug dump platform string.
* Write the ecore version and device's string to the given buffer.
*
* @param p_hwfn
* @param buf_str
* @param buf_size
*/
void ecore_set_platform_str(struct ecore_hwfn *p_hwfn,
char *buf_str, u32 buf_size);
#define TSTORM_QZONE_START PXP_VF_BAR0_START_SDM_ZONE_A
#define MSTORM_QZONE_START(dev) \

60
drivers/net/qede/base/ecore_cxt.c
View File

@ -2186,3 +2186,63 @@ static u16 ecore_blk_calculate_pages(struct ecore_ilt_cli_blk *p_blk)
return DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
}
u16 ecore_get_cdut_num_pf_init_pages(struct ecore_hwfn *p_hwfn)
{
struct ecore_ilt_client_cfg *p_cli;
struct ecore_ilt_cli_blk *p_blk;
u16 i, pages = 0;
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)];
pages += ecore_blk_calculate_pages(p_blk);
}
return pages;
}
u16 ecore_get_cdut_num_vf_init_pages(struct ecore_hwfn *p_hwfn)
{
struct ecore_ilt_client_cfg *p_cli;
struct ecore_ilt_cli_blk *p_blk;
u16 i, pages = 0;
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) {
p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(i, VF)];
pages += ecore_blk_calculate_pages(p_blk);
}
return pages;
}
u16 ecore_get_cdut_num_pf_work_pages(struct ecore_hwfn *p_hwfn)
{
struct ecore_ilt_client_cfg *p_cli;
struct ecore_ilt_cli_blk *p_blk;
u16 i, pages = 0;
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)];
pages += ecore_blk_calculate_pages(p_blk);
}
return pages;
}
u16 ecore_get_cdut_num_vf_work_pages(struct ecore_hwfn *p_hwfn)
{
struct ecore_ilt_client_cfg *p_cli;
struct ecore_ilt_cli_blk *p_blk;
u16 pages = 0, i;
p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) {
p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(i)];
pages += ecore_blk_calculate_pages(p_blk);
}
return pages;
}

5
drivers/net/qede/base/ecore_cxt.h
View File

@ -345,4 +345,9 @@ struct ecore_cxt_mngr {
u16 task_ctx_size;
u16 conn_ctx_size;
};
u16 ecore_get_cdut_num_pf_init_pages(struct ecore_hwfn *p_hwfn);
u16 ecore_get_cdut_num_vf_init_pages(struct ecore_hwfn *p_hwfn);
u16 ecore_get_cdut_num_pf_work_pages(struct ecore_hwfn *p_hwfn);
u16 ecore_get_cdut_num_vf_work_pages(struct ecore_hwfn *p_hwfn);
#endif /* _ECORE_CID_ */

13
drivers/net/qede/base/ecore_dev.c
View File

@ -6798,6 +6798,19 @@ void ecore_set_fw_mac_addr(__le16 *fw_msb,
((u8 *)fw_lsb)[1] = mac[4];
}
void ecore_set_platform_str(struct ecore_hwfn *p_hwfn,
char *buf_str, u32 buf_size)
{
u32 len;
OSAL_SNPRINTF(buf_str, buf_size, "Ecore %d.%d.%d.%d. ",
ECORE_MAJOR_VERSION, ECORE_MINOR_VERSION,
ECORE_REVISION_VERSION, ECORE_ENGINEERING_VERSION);
len = OSAL_STRLEN(buf_str);
OSAL_SET_PLATFORM_STR(p_hwfn, &buf_str[len], buf_size - len);
}
bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
{
return !!OSAL_GET_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);

184
drivers/net/qede/base/ecore_hsi_common.h
View File

@ -10,6 +10,7 @@
/* Add include to common target */
/********************************/
#include "common_hsi.h"
#include "mcp_public.h"
/*
@ -2229,7 +2230,40 @@ struct fw_info_location {
};
/* DMAE parameters */
struct ecore_dmae_params {
u32 flags;
/* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the
* source is a block of length DMAE_MAX_RW_SIZE and the
* destination is larger, the source block will be duplicated as
* many times as required to fill the destination block. This is
* used mostly to write a zeroed buffer to destination address
* using DMA
*/
#define ECORE_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1
#define ECORE_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0
#define ECORE_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1
#define ECORE_DMAE_PARAMS_SRC_VF_VALID_SHIFT 1
#define ECORE_DMAE_PARAMS_DST_VF_VALID_MASK 0x1
#define ECORE_DMAE_PARAMS_DST_VF_VALID_SHIFT 2
#define ECORE_DMAE_PARAMS_COMPLETION_DST_MASK 0x1
#define ECORE_DMAE_PARAMS_COMPLETION_DST_SHIFT 3
#define ECORE_DMAE_PARAMS_PORT_VALID_MASK 0x1
#define ECORE_DMAE_PARAMS_PORT_VALID_SHIFT 4
#define ECORE_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1
#define ECORE_DMAE_PARAMS_SRC_PF_VALID_SHIFT 5
#define ECORE_DMAE_PARAMS_DST_PF_VALID_MASK 0x1
#define ECORE_DMAE_PARAMS_DST_PF_VALID_SHIFT 6
#define ECORE_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF
#define ECORE_DMAE_PARAMS_RESERVED_SHIFT 7
u8 src_vfid;
u8 dst_vfid;
u8 port_id;
u8 src_pfid;
u8 dst_pfid;
u8 reserved1;
__le16 reserved2;
};
/*
* IGU cleanup command
@ -2543,4 +2577,152 @@ struct ystorm_core_conn_ag_ctx {
__le32 reg3 /* reg3 */;
};
/*********/
/* DEBUG */
/*********/
#define MFW_TRACE_SIGNATURE 0x25071946
/* The trace in the buffer */
#define MFW_TRACE_EVENTID_MASK 0x00ffff
#define MFW_TRACE_PRM_SIZE_MASK 0x0f0000
#define MFW_TRACE_PRM_SIZE_OFFSET 16
#define MFW_TRACE_ENTRY_SIZE 3
struct mcp_trace {
u32 signature; /* Help to identify that the trace is valid */
u32 size; /* the size of the trace buffer in bytes*/
u32 curr_level; /* 2 - all will be written to the buffer
* 1 - debug trace will not be written
* 0 - just errors will be written to the buffer
*/
/* a bit per module, 1 means mask it off, 0 means add it to the trace
* buffer
*/
u32 modules_mask[2];
/* Warning: the following pointers are assumed to be 32bits as they are
* used only in the MFW
*/
/* The next trace will be written to this offset */
u32 trace_prod;
/* The oldest valid trace starts at this offset (usually very close
* after the current producer)
*/
u32 trace_oldest;
};
enum spad_sections {
SPAD_SECTION_TRACE,
SPAD_SECTION_NVM_CFG,
SPAD_SECTION_PUBLIC,
SPAD_SECTION_PRIVATE,
SPAD_SECTION_MAX
};
#define MCP_TRACE_SIZE 2048 /* 2kb */
/* This section is located at a fixed location in the beginning of the
* scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
* All the rest of data has a floating location which differs from version to
* version, and is pointed by the mcp_meta_data below.
* Moreover, the spad_layout section is part of the MFW firmware, and is loaded
* with it from nvram in order to clear this portion.
*/
struct static_init {
u32 num_sections;
offsize_t sections[SPAD_SECTION_MAX];
#define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
struct mcp_trace trace;
#define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
u8 trace_buffer[MCP_TRACE_SIZE];
#define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
/* running_mfw has the same definition as in nvm_map.h.
* This bit indicate both the running dir, and the running bundle.
* It is set once when the LIM is loaded.
*/
u32 running_mfw;
#define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
u32 build_time;
#define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
u32 reset_type;
#define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
u32 mfw_secure_mode;
#define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
u16 pme_status_pf_bitmap;
#define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
u16 pme_enable_pf_bitmap;
#define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
u32 mim_nvm_addr;
u32 mim_start_addr;
u32 ah_pcie_link_params;
#define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
#define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
#define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8)
#define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
#define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16)
#define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
#define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24)
#define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */
};
#define NVM_MAGIC_VALUE 0x669955aa
enum nvm_image_type {
NVM_TYPE_TIM1 = 0x01,
NVM_TYPE_TIM2 = 0x02,
NVM_TYPE_MIM1 = 0x03,
NVM_TYPE_MIM2 = 0x04,
NVM_TYPE_MBA = 0x05,
NVM_TYPE_MODULES_PN = 0x06,
NVM_TYPE_VPD = 0x07,
NVM_TYPE_MFW_TRACE1 = 0x08,
NVM_TYPE_MFW_TRACE2 = 0x09,
NVM_TYPE_NVM_CFG1 = 0x0a,
NVM_TYPE_L2B = 0x0b,
NVM_TYPE_DIR1 = 0x0c,
NVM_TYPE_EAGLE_FW1 = 0x0d,
NVM_TYPE_FALCON_FW1 = 0x0e,
NVM_TYPE_PCIE_FW1 = 0x0f,
NVM_TYPE_HW_SET = 0x10,
NVM_TYPE_LIM = 0x11,
NVM_TYPE_AVS_FW1 = 0x12,
NVM_TYPE_DIR2 = 0x13,
NVM_TYPE_CCM = 0x14,
NVM_TYPE_EAGLE_FW2 = 0x15,
NVM_TYPE_FALCON_FW2 = 0x16,
NVM_TYPE_PCIE_FW2 = 0x17,
NVM_TYPE_AVS_FW2 = 0x18,
NVM_TYPE_INIT_HW = 0x19,
NVM_TYPE_DEFAULT_CFG = 0x1a,
NVM_TYPE_MDUMP = 0x1b,
NVM_TYPE_META = 0x1c,
NVM_TYPE_ISCSI_CFG = 0x1d,
NVM_TYPE_FCOE_CFG = 0x1f,
NVM_TYPE_ETH_PHY_FW1 = 0x20,
NVM_TYPE_ETH_PHY_FW2 = 0x21,
NVM_TYPE_BDN = 0x22,
NVM_TYPE_8485X_PHY_FW = 0x23,
NVM_TYPE_PUB_KEY = 0x24,
NVM_TYPE_RECOVERY = 0x25,
NVM_TYPE_PLDM = 0x26,
NVM_TYPE_UPK1 = 0x27,
NVM_TYPE_UPK2 = 0x28,
NVM_TYPE_MASTER_KC = 0x29,
NVM_TYPE_BACKUP_KC = 0x2a,
NVM_TYPE_HW_DUMP = 0x2b,
NVM_TYPE_HW_DUMP_OUT = 0x2c,
NVM_TYPE_BIN_NVM_META = 0x30,
NVM_TYPE_ROM_TEST = 0xf0,
NVM_TYPE_88X33X0_PHY_FW = 0x31,
NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,
NVM_TYPE_MAX,
};
#define DIR_ID_1 (0)
#endif /* __ECORE_HSI_COMMON__ */

2
drivers/net/qede/base/ecore_hsi_debug_tools.h
View File

@ -245,6 +245,7 @@ struct dbg_mode_hdr {
* Attention register
*/
struct dbg_attn_reg {
struct dbg_mode_hdr mode /* Mode header */;
/* The offset of this registers attentions within the blocks attentions list
* (a value in the range 0..number of block attentions-1)
*/
@ -1049,5 +1050,4 @@ struct dbg_tools_data {
};
#endif /* __ECORE_HSI_DEBUG_TOOLS__ */

211
drivers/net/qede/base/ecore_mcp.c
View File

@ -3621,6 +3621,217 @@ enum _ecore_status_t ecore_mcp_bist_nvm_test_get_image_att(
return rc;
}
enum _ecore_status_t
ecore_mcp_bist_nvm_get_num_images(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u32 *num_images)
{
u32 drv_mb_param = 0, rsp;
enum _ecore_status_t rc = ECORE_SUCCESS;
SET_MFW_FIELD(drv_mb_param, DRV_MB_PARAM_BIST_TEST_INDEX,
DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES);
rc = ecore_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
drv_mb_param, &rsp, num_images);
if (rc != ECORE_SUCCESS)
return rc;
if (rsp == FW_MSG_CODE_UNSUPPORTED)
rc = ECORE_NOTIMPL;
else if (rsp != FW_MSG_CODE_OK)
rc = ECORE_UNKNOWN_ERROR;
return rc;
}
enum _ecore_status_t
ecore_mcp_bist_nvm_get_image_att(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct bist_nvm_image_att *p_image_att,
u32 image_index)
{
u32 buf_size, nvm_offset = 0, resp, param;
enum _ecore_status_t rc;
SET_MFW_FIELD(nvm_offset, DRV_MB_PARAM_BIST_TEST_INDEX,
DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX);
SET_MFW_FIELD(nvm_offset, DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX,
image_index);
rc = ecore_mcp_nvm_rd_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
nvm_offset, &resp, &param, &buf_size,
(u32 *)p_image_att);
if (rc != ECORE_SUCCESS)
return rc;
if (resp == FW_MSG_CODE_UNSUPPORTED)
rc = ECORE_NOTIMPL;
else if ((resp != FW_MSG_CODE_OK) || (p_image_att->return_code != 1))
rc = ECORE_UNKNOWN_ERROR;
return rc;
}
enum _ecore_status_t ecore_mcp_nvm_info_populate(struct ecore_hwfn *p_hwfn)
{
struct ecore_nvm_image_info nvm_info;
struct ecore_ptt *p_ptt;
enum _ecore_status_t rc;
u32 i;
if (p_hwfn->nvm_info.valid)
return ECORE_SUCCESS;
#ifndef ASIC_ONLY
if (CHIP_REV_IS_EMUL(p_hwfn->p_dev) ||
CHIP_REV_IS_TEDIBEAR(p_hwfn->p_dev))
return ECORE_SUCCESS;
#endif
p_ptt = ecore_ptt_acquire(p_hwfn);
if (!p_ptt) {
DP_ERR(p_hwfn, "failed to acquire ptt\n");
return ECORE_BUSY;
}
/* Acquire from MFW the amount of available images */
OSAL_MEM_ZERO(&nvm_info, sizeof(nvm_info));
rc = ecore_mcp_bist_nvm_get_num_images(p_hwfn, p_ptt,
&nvm_info.num_images);
if (rc == ECORE_NOTIMPL) {
DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n");
goto out;
} else if ((rc != ECORE_SUCCESS) || (nvm_info.num_images == 0)) {
DP_ERR(p_hwfn, "Failed getting number of images\n");
goto err0;
}
nvm_info.image_att = OSAL_ALLOC(p_hwfn->p_dev, GFP_KERNEL,
nvm_info.num_images *
sizeof(struct bist_nvm_image_att));
if (!nvm_info.image_att) {
rc = ECORE_NOMEM;
goto err0;
}
/* Iterate over images and get their attributes */
for (i = 0; i < nvm_info.num_images; i++) {
rc = ecore_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
&nvm_info.image_att[i],
i);
if (rc != ECORE_SUCCESS) {
DP_ERR(p_hwfn,
"Failed getting image index %d attributes\n",
i);
goto err1;
}
DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "image index %d, size %x\n", i,
nvm_info.image_att[i].len);
}
out:
/* Update hwfn's nvm_info */
if (nvm_info.num_images) {
p_hwfn->nvm_info.num_images = nvm_info.num_images;
if (p_hwfn->nvm_info.image_att)
OSAL_FREE(p_hwfn->p_dev, p_hwfn->nvm_info.image_att);
p_hwfn->nvm_info.image_att = nvm_info.image_att;
p_hwfn->nvm_info.valid = true;
}
ecore_ptt_release(p_hwfn, p_ptt);
return ECORE_SUCCESS;
err1:
OSAL_FREE(p_hwfn->p_dev, nvm_info.image_att);
err0:
ecore_ptt_release(p_hwfn, p_ptt);
return rc;
}
enum _ecore_status_t
ecore_mcp_get_nvm_image_att(struct ecore_hwfn *p_hwfn,
enum ecore_nvm_images image_id,
struct ecore_nvm_image_att *p_image_att)
{
enum nvm_image_type type;
u32 i;
/* Translate image_id into MFW definitions */
switch (image_id) {
case ECORE_NVM_IMAGE_ISCSI_CFG:
type = NVM_TYPE_ISCSI_CFG;
break;
case ECORE_NVM_IMAGE_FCOE_CFG:
type = NVM_TYPE_FCOE_CFG;
break;
case ECORE_NVM_IMAGE_MDUMP:
type = NVM_TYPE_MDUMP;
break;
case ECORE_NVM_IMAGE_NVM_CFG1:
type = NVM_TYPE_NVM_CFG1;
break;
case ECORE_NVM_IMAGE_DEFAULT_CFG:
type = NVM_TYPE_DEFAULT_CFG;
break;
case ECORE_NVM_IMAGE_NVM_META:
type = NVM_TYPE_META;
break;
default:
DP_NOTICE(p_hwfn, false, "Unknown request of image_id %08x\n",
image_id);
return ECORE_INVAL;
}
ecore_mcp_nvm_info_populate(p_hwfn);
for (i = 0; i < p_hwfn->nvm_info.num_images; i++) {
if (type == p_hwfn->nvm_info.image_att[i].image_type)
break;
}
if (i == p_hwfn->nvm_info.num_images) {
DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
"Failed to find nvram image of type %08x\n",
image_id);
return ECORE_NOENT;
}
p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
p_image_att->length = p_hwfn->nvm_info.image_att[i].len;
return ECORE_SUCCESS;
}
enum _ecore_status_t ecore_mcp_get_nvm_image(struct ecore_hwfn *p_hwfn,
enum ecore_nvm_images image_id,
u8 *p_buffer, u32 buffer_len)
{
struct ecore_nvm_image_att image_att;
enum _ecore_status_t rc;
OSAL_MEM_ZERO(p_buffer, buffer_len);
rc = ecore_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att);
if (rc != ECORE_SUCCESS)
return rc;
/* Validate sizes - both the image's and the supplied buffer's */
if (image_att.length <= 4) {
DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
"Image [%d] is too small - only %d bytes\n",
image_id, image_att.length);
return ECORE_INVAL;
}
if (image_att.length > buffer_len) {
DP_VERBOSE(p_hwfn, ECORE_MSG_STORAGE,
"Image [%d] is too big - %08x bytes where only %08x are available\n",
image_id, image_att.length, buffer_len);
return ECORE_NOMEM;
}
return ecore_mcp_nvm_read(p_hwfn->p_dev, image_att.start_addr,
(u8 *)p_buffer, image_att.length);
}
enum _ecore_status_t
ecore_mcp_get_temperature_info(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,

37
drivers/net/qede/base/ecore_mcp_api.h
View File

@ -121,6 +121,10 @@ struct ecore_mcp_function_info {
enum ecore_nvm_images {
ECORE_NVM_IMAGE_ISCSI_CFG,
ECORE_NVM_IMAGE_FCOE_CFG,
ECORE_NVM_IMAGE_MDUMP,
ECORE_NVM_IMAGE_NVM_CFG1,
ECORE_NVM_IMAGE_DEFAULT_CFG,
ECORE_NVM_IMAGE_NVM_META,
};
#endif
@ -970,6 +974,39 @@ enum _ecore_status_t ecore_mcp_phy_read(struct ecore_dev *p_dev, u32 cmd,
enum _ecore_status_t ecore_mcp_nvm_read(struct ecore_dev *p_dev, u32 addr,
u8 *p_buf, u32 len);
struct ecore_nvm_image_att {
u32 start_addr;
u32 length;
};
/**
* @brief Allows reading a whole nvram image
*
* @param p_hwfn
* @param image_id - image to get attributes for
* @param p_image_att - image attributes structure into which to fill data
*
* @return enum _ecore_status_t - ECORE_SUCCESS - operation was successful.
*/
enum _ecore_status_t
ecore_mcp_get_nvm_image_att(struct ecore_hwfn *p_hwfn,
enum ecore_nvm_images image_id,
struct ecore_nvm_image_att *p_image_att);
/**
* @brief Allows reading a whole nvram image
*
* @param p_hwfn
* @param image_id - image requested for reading
* @param p_buffer - allocated buffer into which to fill data
* @param buffer_len - length of the allocated buffer.
*
* @return ECORE_SUCCESS if p_buffer now contains the nvram image.
*/
enum _ecore_status_t ecore_mcp_get_nvm_image(struct ecore_hwfn *p_hwfn,
enum ecore_nvm_images image_id,
u8 *p_buffer, u32 buffer_len);
/**
* @brief - Sends an NVM write command request to the MFW with
* payload.

2
drivers/net/qede/base/ecore_status.h
View File

@ -8,6 +8,8 @@
#define __ECORE_STATUS_H__
enum _ecore_status_t {
ECORE_NOENT = -15,
ECORE_CONN_REFUSED = -14,
ECORE_CONN_RESET = -13,
ECORE_UNKNOWN_ERROR = -12,
ECORE_NORESOURCES = -11,

846
drivers/net/qede/base/reg_addr.h
View File

@ -1245,3 +1245,849 @@
#define DORQ_REG_VF_USAGE_CNT_LIM 0x1009ccUL
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST 0x2aa06cUL
#define PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR 0x2aa070UL
#define PSWRQ2_REG_ILT_MEMORY_SIZE_BB 15200
#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 22000
#define TSEM_REG_DBG_GPRE_VECT 0x1701410UL
#define MSEM_REG_DBG_GPRE_VECT 0x1801410UL
#define USEM_REG_DBG_GPRE_VECT 0x1901410UL
#define XSEM_REG_DBG_GPRE_VECT 0x1401410UL
#define YSEM_REG_DBG_GPRE_VECT 0x1501410UL
#define PSEM_REG_DBG_GPRE_VECT 0x1601410UL
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE 0x000748UL
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_WRITE_DISABLE (0x1UL << 0)
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_WRITE_DISABLE_SHIFT 0
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_READ_DISABLE (0x1UL << 1)
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_DRA_READ_DISABLE_SHIFT 1
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_INTERRUPT_DISABLE (0x1UL << 2)
#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE_INTERRUPT_DISABLE_SHIFT 2
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE 0x00074cUL
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_STORE_DATA_DISABLE (0x1UL << 0)
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_STORE_DATA_DISABLE_SHIFT 0
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_LOAD_DATA_DISABLE (0x1UL << 1)
#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE_LOAD_DATA_DISABLE_SHIFT 1
#define NWS_REG_NWS_CMU_K2 0x720000UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2 0x000680UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2 0x000684UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2 0x0006c0UL
#define PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2 0x0006c4UL
#define MS_REG_MS_CMU_K2 0x6a4000UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2 0x000210UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2 0x000214UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2 0x000208UL
#define PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2 0x00020cUL
#define PHY_PCIE_REG_PHY0_K2 0x620000UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2 0x000210UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2 0x000214UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2 0x000208UL
#define PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2 0x00020cUL
#define PHY_PCIE_REG_PHY1_K2 0x624000UL
#define PCIE_REG_DBG_REPEAT_THRESHOLD_COUNT_K2 0x054364UL
#define PCIE_REG_DBG_FW_TRIGGER_ENABLE_K2 0x05436cUL
#define RDIF_REG_DEBUG_ERROR_INFO 0x300400UL
#define RDIF_REG_DEBUG_ERROR_INFO_SIZE 64
#define RDIF_REG_DEBUG_ERROR_INFO_SIZE 64
#define TDIF_REG_DEBUG_ERROR_INFO 0x310400UL
#define TDIF_REG_DEBUG_ERROR_INFO_SIZE 64
#define TDIF_REG_DEBUG_ERROR_INFO_SIZE 64
#define SEM_FAST_REG_VFC_STATUS 0x000b4cUL
#define SEM_FAST_REG_VFC_STATUS_RESPONSE_READY (0x1UL << 0)
#define SEM_FAST_REG_VFC_STATUS_RESPONSE_READY_SHIFT 0
#define SEM_FAST_REG_VFC_STATUS_VFC_BUSY (0x1UL << 1)
#define SEM_FAST_REG_VFC_STATUS_VFC_BUSY_SHIFT 1
#define SEM_FAST_REG_VFC_STATUS_SENDING_CMD_ON_GOING (0x1UL << 2)
#define SEM_FAST_REG_VFC_STATUS_SENDING_CMD_ON_GOING_SHIFT 2
#define RSS_REG_RSS_RAM_DATA_SIZE 4
#define BRB_REG_BIG_RAM_DATA_SIZE 64
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1 0x0084c0UL
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_1_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2 0x0084e4UL
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_2_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3 0x008508UL
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_3_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4 0x00852cUL
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_4_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5 0x008550UL
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_5_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6 0x008574UL
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_6_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7 0x008598UL
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_IGU_OUT_7_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_NIG 0x0085bcUL
#define MISC_REG_AEU_ENABLE1_NIG_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_NIG_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_NIG_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_NIG_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_NIG_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_NIG_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_NIG_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_NIG_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_NIG_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_NIG_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_NIG_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_NIG_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_NIG_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_NIG_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_NIG_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_NIG_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_NIG_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_NIG_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_NIG_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_NIG_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_NIG_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_NIG_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_NIG_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_NIG_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_NIG_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_NIG_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_NIG_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_NIG_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_NIG_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_NIG_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_NIG_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_NIG_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_NIG_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_PXP 0x0085e0UL
#define MISC_REG_AEU_ENABLE1_PXP_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_PXP_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_PXP_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_PXP_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_PXP_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_PXP_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_PXP_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_PXP_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_PXP_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_PXP_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_PXP_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_PXP_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_PXP_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_PXP_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_PXP_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_PXP_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_PXP_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_PXP_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_PXP_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_PXP_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_PXP_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_PXP_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_PXP_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_PXP_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_PXP_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_PXP_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_PXP_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_PXP_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_PXP_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_PXP_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_PXP_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_PXP_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_PXP_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0 0x008628UL
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_MCP_OUT_0_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR 0x008748UL
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_GLB_UNC_ERR_GPIO31_SHIFT 31
#define MISC_REG_AEU_ENABLE1_SYS_KILL 0x008604UL
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO0 (0x1UL << 0)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO0_SHIFT 0
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO1 (0x1UL << 1)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO1_SHIFT 1
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO2 (0x1UL << 2)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO2_SHIFT 2
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO3 (0x1UL << 3)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO3_SHIFT 3
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO4 (0x1UL << 4)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO4_SHIFT 4
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO5 (0x1UL << 5)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO5_SHIFT 5
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO6 (0x1UL << 6)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO6_SHIFT 6
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO (0x1UL << 7)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO_SHIFT 7
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO8 (0x1UL << 8)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO8_SHIFT 8
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO9 (0x1UL << 9)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO9_SHIFT 9
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO10 (0x1UL << 10)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO10_SHIFT 10
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO11 (0x1UL << 11)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO11_SHIFT 11
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO12 (0x1UL << 12)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO12_SHIFT 12
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO13 (0x1UL << 13)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO13_SHIFT 13
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO14 (0x1UL << 14)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO14_SHIFT 14
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO15 (0x1UL << 15)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO15_SHIFT 15
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO16 (0x1UL << 16)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO16_SHIFT 16
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO17 (0x1UL << 17)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO17_SHIFT 17
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO18 (0x1UL << 18)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO18_SHIFT 18
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO19 (0x1UL << 19)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO19_SHIFT 19
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO20 (0x1UL << 20)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO20_SHIFT 20
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO21 (0x1UL << 21)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO21_SHIFT 21
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO22 (0x1UL << 22)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO22_SHIFT 22
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO23 (0x1UL << 23)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO23_SHIFT 23
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO24 (0x1UL << 24)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO24_SHIFT 24
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO25 (0x1UL << 25)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO25_SHIFT 25
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO26 (0x1UL << 26)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO26_SHIFT 26
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO27 (0x1UL << 27)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO27_SHIFT 27
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO28 (0x1UL << 28)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO28_SHIFT 28
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO29 (0x1UL << 29)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO29_SHIFT 29
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO30 (0x1UL << 30)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO30_SHIFT 30
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO31 (0x1UL << 31)
#define MISC_REG_AEU_ENABLE1_SYS_KILL_GPIO31_SHIFT 31
#define DBG_REG_FULL_BUFFER_THR 0x01045cUL
#define MISC_REG_AEU_MASK_ATTN_MCP 0x008498UL
#define MISC_REG_AEU_SYS_KILL_BEHAVIOR 0x008800UL
#define MISC_REG_AEU_GENERAL_MASK 0x008828UL
#define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK (0x1UL << 0)
#define MISC_REG_AEU_GENERAL_MASK_AEU_PXP_CLOSE_MASK_SHIFT 0
#define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK (0x1UL << 1)
#define MISC_REG_AEU_GENERAL_MASK_AEU_NIG_CLOSE_MASK_SHIFT 1
#define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK (0x1UL << 2)
#define MISC_REG_AEU_GENERAL_MASK_AEU_SYS_KILL_MASK_SHIFT 2
#define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK (0x1UL << 3)
#define MISC_REG_AEU_GENERAL_MASK_AEU_GLB_UNC_ERR_MASK_SHIFT 3

1
drivers/net/qede/qede_ethdev.c
View File

@ -7,7 +7,6 @@
#include "qede_ethdev.h"
#include <rte_string_fns.h>
#include <rte_alarm.h>
#include <rte_version.h>
#include <rte_kvargs.h>
static const struct qed_eth_ops *qed_ops;

3
drivers/net/qede/qede_main.c
View File

@ -5,7 +5,6 @@
*/
#include <limits.h>
#include <time.h>
#include <rte_alarm.h>
#include <rte_string_fns.h>
@ -66,7 +65,7 @@ qed_probe(struct ecore_dev *edev, struct rte_pci_device *pci_dev,
hw_prepare_params.initiate_pf_flr = true;
hw_prepare_params.allow_mdump = false;
hw_prepare_params.b_en_pacing = false;
hw_prepare_params.epoch = (u32)time(NULL);
hw_prepare_params.epoch = OSAL_GET_EPOCH(ECORE_LEADING_HWFN(edev));
rc = ecore_hw_prepare(edev, &hw_prepare_params);
if (rc) {
DP_ERR(edev, "hw prepare failed\n");