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net/hns3: check PCI config space reads

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This patch add return value check when calling rte_pci_read_config
function.

Fixes: cea37e513329 ("net/hns3: fix FLR reset")
Cc: stable@dpdk.org

Signed-off-by: Hongbo Zheng <zhenghongbo3@huawei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
This commit is contained in:
Hongbo Zheng 2020-09-29 20:01:16 +08:00 committed by Ferruh Yigit
parent fa29fe45a7
commit 243651cb6c
1 changed files with 51 additions and 11 deletions
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62
drivers/net/hns3/hns3_ethdev_vf.c
View File

@ -64,12 +64,18 @@ static int hns3vf_add_mc_mac_addr(struct hns3_hw *hw,
static int hns3vf_remove_mc_mac_addr(struct hns3_hw *hw,
struct rte_ether_addr *mac_addr);
/* set PCI bus mastering */
static void
static int
hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
{
uint16_t reg;
int ret;
rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
ret = rte_pci_read_config(device, &reg, sizeof(reg), PCI_COMMAND);
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
PCI_COMMAND);
return ret;
}
if (op)
/* set the master bit */
@ -77,7 +83,7 @@ hns3vf_set_bus_master(const struct rte_pci_device *device, bool op)
else
reg &= ~(PCI_COMMAND_MASTER);
rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
return rte_pci_write_config(device, &reg, sizeof(reg), PCI_COMMAND);
}
/**
@ -94,16 +100,34 @@ hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
uint8_t pos;
uint8_t id;
int ttl;
int ret;
ret = rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x", PCI_STATUS);
return 0;
}
rte_pci_read_config(device, &status, sizeof(status), PCI_STATUS);
if (!(status & PCI_STATUS_CAP_LIST))
return 0;
ttl = MAX_PCIE_CAPABILITY;
rte_pci_read_config(device, &pos, sizeof(pos), PCI_CAPABILITY_LIST);
ret = rte_pci_read_config(device, &pos, sizeof(pos),
PCI_CAPABILITY_LIST);
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
PCI_CAPABILITY_LIST);
return 0;
}
while (ttl-- && pos >= PCI_STD_HEADER_SIZEOF) {
rte_pci_read_config(device, &id, sizeof(id),
(pos + PCI_CAP_LIST_ID));
ret = rte_pci_read_config(device, &id, sizeof(id),
(pos + PCI_CAP_LIST_ID));
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
(pos + PCI_CAP_LIST_ID));
break;
}
if (id == 0xFF)
break;
@ -111,8 +135,13 @@ hns3vf_find_pci_capability(const struct rte_pci_device *device, int cap)
if (id == cap)
return (int)pos;
rte_pci_read_config(device, &pos, sizeof(pos),
(pos + PCI_CAP_LIST_NEXT));
ret = rte_pci_read_config(device, &pos, sizeof(pos),
(pos + PCI_CAP_LIST_NEXT));
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
(pos + PCI_CAP_LIST_NEXT));
break;
}
}
return 0;
}
@ -122,11 +151,18 @@ hns3vf_enable_msix(const struct rte_pci_device *device, bool op)
{
uint16_t control;
int pos;
int ret;
pos = hns3vf_find_pci_capability(device, PCI_CAP_ID_MSIX);
if (pos) {
rte_pci_read_config(device, &control, sizeof(control),
ret = rte_pci_read_config(device, &control, sizeof(control),
(pos + PCI_MSIX_FLAGS));
if (ret < 0) {
PMD_INIT_LOG(ERR, "Failed to read PCI offset 0x%x",
(pos + PCI_MSIX_FLAGS));
return -ENXIO;
}
if (op)
control |= PCI_MSIX_FLAGS_ENABLE;
else
@ -2576,7 +2612,11 @@ hns3vf_reinit_dev(struct hns3_adapter *hns)
if (hw->reset.level == HNS3_VF_FULL_RESET) {
rte_intr_disable(&pci_dev->intr_handle);
hns3vf_set_bus_master(pci_dev, true);
ret = hns3vf_set_bus_master(pci_dev, true);
if (ret) {
hns3_err(hw, "failed to set pci bus, ret = %d", ret);
return ret;
}
}
/* Firmware command initialize */