crypto/cnxk: add driver skeleton

Add driver skeleton for crypto_cn9k & crypto_cn10k
PMDs leveraging cnxk common framework.

Signed-off-by: Ankur Dwivedi <adwivedi@marvell.com>
Signed-off-by: Anoob Joseph <anoobj@marvell.com>
Signed-off-by: Archana Muniganti <marchana@marvell.com>
Signed-off-by: Tejasree Kondoj <ktejasree@marvell.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>

MAINTAINERS

@@ -1067,6 +1067,15 @@ F: drivers/crypto/kasumi/
 F: doc/guides/cryptodevs/kasumi.rst
 F: doc/guides/cryptodevs/features/kasumi.ini
 
+Marvell cnxk crypto
+M: Ankur Dwivedi <adwivedi@marvell.com>
+M: Anoob Joseph <anoobj@marvell.com>
+M: Tejasree Kondoj <ktejasree@marvell.com>
+F: drivers/crypto/cnxk/
+F: doc/guides/cryptodevs/cnxk.rst
+F: doc/guides/cryptodevs/features/cn9k.ini
+F: doc/guides/cryptodevs/features/cn10k.ini
+
 Marvell mvsam
 M: Michael Shamis <michaelsh@marvell.com>
 M: Liron Himi <lironh@marvell.com>

doc/guides/cryptodevs/cnxk.rst

@@ -0,0 +1,126 @@
+.. SPDX-License-Identifier: BSD-3-Clause
+   Copyright(c) 2021 Marvell.
+
+Marvell cnxk Crypto Poll Mode Driver
+====================================
+
+The cnxk crypto poll mode driver provides support for offloading
+cryptographic operations to cryptographic accelerator units on the
+**Marvell OCTEON cnxk** SoC family.
+
+The cnxk crypto PMD code is organized into different sets of files.
+The file names starting with cn9k and cn10k provides support for CN9XX
+and CN10XX respectively. The common code between the SoCs is present
+in file names starting with cnxk.
+
+More information about OCTEON cnxk SoCs may be obtained from `<https://www.marvell.com>`_
+
+Supported OCTEON cnxk SoCs
+--------------------------
+
+- CN9XX
+- CN10XX
+
+Installation
+------------
+
+The OCTEON cnxk crypto PMD may be compiled natively on an OCTEON cnxk platform
+or cross-compiled on an x86 platform.
+
+Refer to :doc:`../platform/cnxk` for instructions to build your DPDK
+application.
+
+.. note::
+
+   The OCTEON cnxk crypto PMD uses services from the kernel mode OCTEON cnxk
+   crypto PF driver in linux. This driver is included in the OCTEON TX SDK.
+
+Initialization
+--------------
+
+``CN9K Initialization``
+
+List the CPT PF devices available on cn9k platform:
+
+.. code-block:: console
+
+    lspci -d:a0fd
+
+``a0fd`` is the CPT PF device id. You should see output similar to:
+
+.. code-block:: console
+
+    0002:10:00.0 Class 1080: Device 177d:a0fd
+
+Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
+
+.. code-block:: console
+
+    echo 1 > /sys/bus/pci/devices/0002:10:00.0/sriov_numvfs
+
+Bind the CPT VF device to the vfio_pci driver:
+
+.. code-block:: console
+
+    cd <dpdk directory>
+    ./usertools/dpdk-devbind.py -u 0002:10:00.1
+    ./usertools/dpdk-devbind.py -b vfio-pci 0002:10.00.1
+
+.. note::
+
+    * For CN98xx SoC, it is recommended to use even and odd DBDF VFs to achieve
+      higher performance as even VF uses one crypto engine and odd one uses
+      another crypto engine.
+
+    * Ensure that sufficient huge pages are available for your application::
+
+         dpdk-hugepages.py --setup 4G --pagesize 512M
+
+      Refer to :ref:`linux_gsg_hugepages` for more details.
+
+``CN10K Initialization``
+
+List the CPT PF devices available on cn10k platform:
+
+.. code-block:: console
+
+    lspci -d:a0f2
+
+``a0f2`` is the CPT PF device id. You should see output similar to:
+
+.. code-block:: console
+
+    0002:20:00.0 Class 1080: Device 177d:a0f2
+
+Set ``sriov_numvfs`` on the CPT PF device, to create a VF:
+
+.. code-block:: console
+
+    echo 1 > /sys/bus/pci/devices/0002:20:00.0/sriov_numvfs
+
+Bind the CPT VF device to the vfio_pci driver:
+
+.. code-block:: console
+
+    cd <dpdk directory>
+    ./usertools/dpdk-devbind.py -u 0002:20:00.1
+    ./usertools/dpdk-devbind.py -b vfio-pci 0002:20:00.1
+
+Debugging Options
+-----------------
+
+.. _table_octeon_cnxk_crypto_debug_options:
+
+.. table:: OCTEON cnxk crypto PMD debug options
+
+    +---+------------+-------------------------------------------------------+
+    | # | Component  | EAL log command                                       |
+    +===+============+=======================================================+
+    | 1 | CPT        | --log-level='pmd\.crypto\.cnxk,8'                     |
+    +---+------------+-------------------------------------------------------+
+
+Limitations
+-----------
+
+Multiple lcores may not operate on the same crypto queue pair. The lcore that
+enqueues to a queue pair is the one that must dequeue from it.

doc/guides/cryptodevs/features/cn10k.ini

@@ -0,0 +1,21 @@
+;
+; Supported features of the 'cn10k' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+
+;
+; Supported crypto algorithms of 'cn10k' crypto driver.
+;
+[Cipher]
+
+;
+; Supported authentication algorithms of 'cn10k' crypto driver.
+;
+[Auth]
+
+;
+; Supported AEAD algorithms of 'cn10k' crypto driver.
+;
+[AEAD]

doc/guides/cryptodevs/features/cn9k.ini

@@ -0,0 +1,21 @@
+;
+; Supported features of the 'cn9k' crypto driver.
+;
+; Refer to default.ini for the full list of available PMD features.
+;
+[Features]
+
+;
+; Supported crypto algorithms of 'cn9k' crypto driver.
+;
+[Cipher]
+
+;
+; Supported authentication algorithms of 'cn9k' crypto driver.
+;
+[Auth]
+
+;
+; Supported AEAD algorithms of 'cn9k' crypto driver.
+;
+[AEAD]

doc/guides/cryptodevs/index.rst

@@ -16,6 +16,7 @@ Crypto Device Drivers
     bcmfs
     caam_jr
     ccp
+    cnxk
     dpaa2_sec
     dpaa_sec
     kasumi

drivers/crypto/cnxk/cn10k_cryptodev.c

@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_crypto.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_dev.h>
+#include <rte_pci.h>
+
+#include "cn10k_cryptodev.h"
+#include "roc_api.h"
+
+uint8_t cn10k_cryptodev_driver_id;
+
+static struct rte_pci_id pci_id_cpt_table[] = {
+	{
+		RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM,
+			       PCI_DEVID_CN10K_RVU_CPT_VF)
+	},
+	/* sentinel */
+	{
+		.device_id = 0
+	},
+};
+
+static struct rte_pci_driver cn10k_cryptodev_pmd = {
+	.id_table = pci_id_cpt_table,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+	.probe = NULL,
+	.remove = NULL,
+};
+
+static struct cryptodev_driver cn10k_cryptodev_drv;
+
+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_CN10K_PMD, cn10k_cryptodev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_CN10K_PMD, pci_id_cpt_table);
+RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_CN10K_PMD, "vfio-pci");
+RTE_PMD_REGISTER_CRYPTO_DRIVER(cn10k_cryptodev_drv, cn10k_cryptodev_pmd.driver,
+			       cn10k_cryptodev_driver_id);

drivers/crypto/cnxk/cn10k_cryptodev.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CN10K_CRYPTODEV_H_
+#define _CN10K_CRYPTODEV_H_
+
+/* Marvell OCTEON CN10K Crypto PMD device name */
+#define CRYPTODEV_NAME_CN10K_PMD crypto_cn10k
+
+extern uint8_t cn10k_cryptodev_driver_id;
+
+#endif /* _CN10K_CRYPTODEV_H_ */

drivers/crypto/cnxk/cn9k_cryptodev.c

@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_crypto.h>
+#include <rte_cryptodev.h>
+#include <rte_cryptodev_pmd.h>
+#include <rte_dev.h>
+#include <rte_pci.h>
+
+#include "cn9k_cryptodev.h"
+#include "roc_api.h"
+
+uint8_t cn9k_cryptodev_driver_id;
+
+static struct rte_pci_id pci_id_cpt_table[] = {
+	{
+	},
+	/* sentinel */
+	{
+		.device_id = 0
+	},
+};
+
+static struct rte_pci_driver cn9k_cryptodev_pmd = {
+	.id_table = pci_id_cpt_table,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+	.probe = NULL,
+	.remove = NULL,
+};
+
+static struct cryptodev_driver cn9k_cryptodev_drv;
+
+RTE_PMD_REGISTER_PCI(CRYPTODEV_NAME_CN9K_PMD, cn9k_cryptodev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(CRYPTODEV_NAME_CN9K_PMD, pci_id_cpt_table);
+RTE_PMD_REGISTER_KMOD_DEP(CRYPTODEV_NAME_CN9K_PMD, "vfio-pci");
+RTE_PMD_REGISTER_CRYPTO_DRIVER(cn9k_cryptodev_drv, cn9k_cryptodev_pmd.driver,
+			       cn9k_cryptodev_driver_id);

drivers/crypto/cnxk/cn9k_cryptodev.h

@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CN9K_CRYPTODEV_H_
+#define _CN9K_CRYPTODEV_H_
+
+/* Marvell OCTEON CN9K Crypto PMD device name */
+#define CRYPTODEV_NAME_CN9K_PMD crypto_cn9k
+
+extern uint8_t cn9k_cryptodev_driver_id;
+
+#endif /* _CN9K_CRYPTODEV_H_ */

drivers/crypto/cnxk/meson.build

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright(C) 2021 Marvell.
+#
+
+if not is_linux or not dpdk_conf.get('RTE_ARCH_64')
+	build = false
+	reason = 'only supported on 64-bit Linux'
+	subdir_done()
+endif
+
+sources = files(
+        'cn9k_cryptodev.c',
+        'cn10k_cryptodev.c',
+)
+
+deps += ['bus_pci', 'common_cnxk']

drivers/crypto/cnxk/version.map

@@ -0,0 +1,3 @@
+INTERNAL {
+	local: *;
+};

drivers/crypto/meson.build

@@ -12,6 +12,7 @@ drivers = [
         'bcmfs',
         'caam_jr',
         'ccp',
+        'cnxk',
         'dpaa_sec',
         'dpaa2_sec',
         'kasumi',