d/numam-dpdk
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

net/sfc/base: remove min/max defines for number of Rx descs

Browse Source 
EF100/Riverhead has different min/max limits. So, these limits should
be a part of NIC config, not defines common for all NIC families.

Signed-off-by: Igor Romanov <igor.romanov@oktetlabs.ru>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
This commit is contained in:
Igor Romanov 2019-02-07 16:29:12 +00:00 committed by Ferruh Yigit
parent 61d820eba0
commit 24b4d1f095
9 changed files with 38 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
drivers/net/sfc/base/ef10_impl.h
View File

@ -11,6 +11,9 @@
extern "C" {
#endif
#define EF10_RXQ_MAXNDESCS 4096
#define EF10_RXQ_MINNDESCS 512
#define EF10_TXQ_MINNDESCS 512
/* Number of hardware PIO buffers (for compile-time resource dimensions) */

9
drivers/net/sfc/base/ef10_rx.c
View File

@ -39,7 +39,7 @@ efx_mcdi_init_rxq(
uint32_t dma_mode;
boolean_t want_outer_classes;
EFSYS_ASSERT3U(ndescs, <=, EFX_RXQ_MAXNDESCS);
EFSYS_ASSERT3U(ndescs, <=, encp->enc_rxq_max_ndescs);
if ((esmp == NULL) || (EFSYS_MEM_SIZE(esmp) < EFX_RXQ_SIZE(ndescs))) {
rc = EINVAL;
@ -1012,11 +1012,12 @@ ef10_rx_qcreate(
EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs));
EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs));
if (!ISP2(ndescs) ||
(ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
(ndescs < encp->enc_rxq_min_ndescs) ||
(ndescs > encp->enc_rxq_max_ndescs)) {
rc = EINVAL;
goto fail1;
}

10
drivers/net/sfc/base/efx.h
View File

@ -1271,6 +1271,8 @@ typedef struct efx_nic_cfg_s {
uint32_t enc_evq_limit;
uint32_t enc_txq_limit;
uint32_t enc_rxq_limit;
uint32_t enc_rxq_max_ndescs;
uint32_t enc_rxq_min_ndescs;
uint32_t enc_txq_max_ndescs;
uint32_t enc_txq_min_ndescs;
uint32_t enc_buftbl_limit;
@ -2462,8 +2464,12 @@ efx_pseudo_hdr_pkt_length_get(
__in uint8_t *buffer,
__out uint16_t *pkt_lengthp);
#define EFX_RXQ_MAXNDESCS 4096
#define EFX_RXQ_MINNDESCS 512
/*
* These symbols are deprecated and will be removed.
* Use the fields from efx_nic_cfg_t instead.
*/
#define EFX_RXQ_MAXNDESCS 4096
#define EFX_RXQ_MINNDESCS 512
#define EFX_RXQ_SIZE(_ndescs) ((_ndescs) * sizeof (efx_qword_t))
#define EFX_RXQ_NBUFS(_ndescs) (EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)

12
drivers/net/sfc/base/efx_rx.c
View File

@ -1590,11 +1590,12 @@ siena_rx_qcreate(
EFSYS_ASSERT3U(label, <, EFX_EV_RX_NLABELS);
EFSYS_ASSERT3U(enp->en_rx_qcount + 1, <, encp->enc_rxq_limit);
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MAXNDESCS));
EFX_STATIC_ASSERT(ISP2(EFX_RXQ_MINNDESCS));
EFSYS_ASSERT(ISP2(encp->enc_rxq_max_ndescs));
EFSYS_ASSERT(ISP2(encp->enc_rxq_min_ndescs));
if (!ISP2(ndescs) ||
(ndescs < EFX_RXQ_MINNDESCS) || (ndescs > EFX_RXQ_MAXNDESCS)) {
(ndescs < encp->enc_rxq_min_ndescs) ||
(ndescs > encp->enc_rxq_max_ndescs)) {
rc = EINVAL;
goto fail1;
}
@ -1602,9 +1603,10 @@ siena_rx_qcreate(
rc = EINVAL;
goto fail2;
}
for (size = 0; (1 << size) <= (EFX_RXQ_MAXNDESCS / EFX_RXQ_MINNDESCS);
for (size = 0;
(1U << size) <= encp->enc_rxq_max_ndescs / encp->enc_rxq_min_ndescs;
size++)
if ((1 << size) == (int)(ndescs / EFX_RXQ_MINNDESCS))
if ((1U << size) == (uint32_t)ndescs / encp->enc_rxq_min_ndescs)
break;
if (id + (1 << size) >= encp->enc_buftbl_limit) {
rc = EINVAL;

3
drivers/net/sfc/base/hunt_nic.c
View File

@ -190,6 +190,9 @@ hunt_board_cfg(
encp->enc_rx_buf_align_start = 1;
encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
/*
* The workaround for bug35388 uses the top bit of transmit queue
* descriptor writes, preventing the use of 4096 descriptor TXQs.

3
drivers/net/sfc/base/medford2_nic.c
View File

@ -114,6 +114,9 @@ medford2_board_cfg(
}
encp->enc_rx_buf_align_end = end_padding;
encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
/*
* The maximum supported transmit queue size is 2048. TXQs with 4096
* descriptors are not supported as the top bit is used for vfifo

3
drivers/net/sfc/base/medford_nic.c
View File

@ -112,6 +112,9 @@ medford_board_cfg(
}
encp->enc_rx_buf_align_end = end_padding;
encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
/*
* The maximum supported transmit queue size is 2048. TXQs with 4096
* descriptors are not supported as the top bit is used for vfifo

3
drivers/net/sfc/base/siena_impl.h
View File

@ -27,6 +27,9 @@ extern "C" {
#define SIENA_TXQ_MAXNDESCS 4096
#define SIENA_TXQ_MINNDESCS 512
#define SIENA_RXQ_MAXNDESCS 4096
#define SIENA_RXQ_MINNDESCS 512
#define SIENA_NVRAM_CHUNK 0x80

3
drivers/net/sfc/base/siena_nic.c
View File

@ -149,6 +149,9 @@ siena_board_cfg(
encp->enc_rxq_limit = MIN(EFX_RXQ_LIMIT_TARGET, nrxq);
encp->enc_txq_limit = MIN(EFX_TXQ_LIMIT_TARGET, ntxq);
encp->enc_rxq_max_ndescs = EF10_RXQ_MAXNDESCS;
encp->enc_rxq_min_ndescs = EF10_RXQ_MINNDESCS;
encp->enc_txq_max_ndescs = SIENA_TXQ_MAXNDESCS;
encp->enc_txq_min_ndescs = SIENA_TXQ_MINNDESCS;