raw/cnxk_bphy: add baseband PHY skeleton driver

Add baseband phy skeleton driver. Baseband phy is a hardware subsystem
accelerating 5G/LTE related tasks. Note this driver isn't involved into
any sort baseband protocol processing. Instead it just provides means
for configuring hardware.

Signed-off-by: Jakub Palider <jpalider@marvell.com>
Signed-off-by: Tomasz Duszynski <tduszynski@marvell.com>
Reviewed-by: Jerin Jacob <jerinj@marvell.com>

drivers/raw/cnxk_bphy/cnxk_bphy.c

@@ -0,0 +1,113 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+#include <rte_bus_pci.h>
+#include <rte_common.h>
+#include <rte_dev.h>
+#include <rte_eal.h>
+#include <rte_lcore.h>
+#include <rte_pci.h>
+#include <rte_rawdev.h>
+#include <rte_rawdev_pmd.h>
+
+#include <roc_api.h>
+
+#include "cnxk_bphy_irq.h"
+
+static const struct rte_pci_id pci_bphy_map[] = {
+	{RTE_PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_CNXK_BPHY)},
+	{
+		.vendor_id = 0,
+	},
+};
+
+static void
+bphy_rawdev_get_name(char *name, struct rte_pci_device *pci_dev)
+{
+	snprintf(name, RTE_RAWDEV_NAME_MAX_LEN, "BPHY:%x:%02x.%x",
+		 pci_dev->addr.bus, pci_dev->addr.devid,
+		 pci_dev->addr.function);
+}
+
+static const struct rte_rawdev_ops bphy_rawdev_ops = {
+};
+
+static int
+bphy_rawdev_probe(struct rte_pci_driver *pci_drv,
+		  struct rte_pci_device *pci_dev)
+{
+	struct bphy_device *bphy_dev = NULL;
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *bphy_rawdev;
+	int ret;
+
+	RTE_SET_USED(pci_drv);
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (!pci_dev->mem_resource[0].addr) {
+		plt_err("BARs have invalid values: BAR0 %p\n BAR2 %p",
+			pci_dev->mem_resource[0].addr,
+			pci_dev->mem_resource[2].addr);
+		return -ENODEV;
+	}
+
+	ret = roc_plt_init();
+	if (ret)
+		return ret;
+
+	bphy_rawdev_get_name(name, pci_dev);
+	bphy_rawdev = rte_rawdev_pmd_allocate(name, sizeof(*bphy_dev),
+					      rte_socket_id());
+	if (bphy_rawdev == NULL) {
+		plt_err("Failed to allocate rawdev");
+		return -ENOMEM;
+	}
+
+	bphy_rawdev->dev_ops = &bphy_rawdev_ops;
+	bphy_rawdev->device = &pci_dev->device;
+	bphy_rawdev->driver_name = pci_dev->driver->driver.name;
+
+	bphy_dev = (struct bphy_device *)bphy_rawdev->dev_private;
+	bphy_dev->mem.res0 = pci_dev->mem_resource[0];
+	bphy_dev->mem.res2 = pci_dev->mem_resource[2];
+
+	return 0;
+}
+
+static int
+bphy_rawdev_remove(struct rte_pci_device *pci_dev)
+{
+	char name[RTE_RAWDEV_NAME_MAX_LEN];
+	struct rte_rawdev *rawdev;
+
+	if (rte_eal_process_type() != RTE_PROC_PRIMARY)
+		return 0;
+
+	if (pci_dev == NULL) {
+		plt_err("invalid pci_dev");
+		return -EINVAL;
+	}
+
+	rawdev = rte_rawdev_pmd_get_named_dev(name);
+	if (rawdev == NULL) {
+		plt_err("invalid device name (%s)", name);
+		return -EINVAL;
+	}
+
+	bphy_rawdev_get_name(name, pci_dev);
+
+	return rte_rawdev_pmd_release(rawdev);
+}
+
+static struct rte_pci_driver cnxk_bphy_rawdev_pmd = {
+	.id_table = pci_bphy_map,
+	.drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_NEED_IOVA_AS_VA,
+	.probe = bphy_rawdev_probe,
+	.remove = bphy_rawdev_remove,
+};
+
+RTE_PMD_REGISTER_PCI(bphy_rawdev_pci_driver, cnxk_bphy_rawdev_pmd);
+RTE_PMD_REGISTER_PCI_TABLE(bphy_rawdev_pci_driver, pci_bphy_map);
+RTE_PMD_REGISTER_KMOD_DEP(bphy_rawdev_pci_driver, "vfio-pci");

drivers/raw/cnxk_bphy/cnxk_bphy_irq.h

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(C) 2021 Marvell.
+ */
+
+#ifndef _CNXK_BPHY_IRQ_
+#define _CNXK_BPHY_IRQ_
+
+#include <rte_bus_pci.h>
+#include <rte_dev.h>
+
+#include <roc_api.h>
+
+struct bphy_mem {
+	struct rte_mem_resource res0;
+	struct rte_mem_resource res2;
+};
+
+struct bphy_device {
+	struct roc_bphy_irq_chip *irq_chip;
+	struct bphy_mem mem;
+};
+
+#endif /* _CNXK_BPHY_IRQ_ */

drivers/raw/cnxk_bphy/meson.build

@@ -4,6 +4,7 @@
 
 deps += ['bus_pci', 'common_cnxk', 'rawdev']
 sources = files(
+        'cnxk_bphy.c',
         'cnxk_bphy_cgx.c',
         'cnxk_bphy_cgx_test.c',
 )

usertools/dpdk-devbind.py

@@ -45,6 +45,8 @@
                  'SVendor': None, 'SDevice': None}
 octeontx2_ree = {'Class': '08', 'Vendor': '177d', 'Device': 'a0f4',
                  'SVendor': None, 'SDevice': None}
+cnxk_bphy = {'Class': '08', 'Vendor': '177d', 'Device': 'a089',
+             'SVendor': None, 'SDevice': None}
 cnxk_bphy_cgx = {'Class': '08', 'Vendor': '177d', 'Device': 'a059,a060',
                  'SVendor': None, 'SDevice': None}
 
@@ -71,7 +73,7 @@
 mempool_devices = [cavium_fpa, octeontx2_npa]
 compress_devices = [cavium_zip]
 regex_devices = [octeontx2_ree]
-misc_devices = [cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
+misc_devices = [cnxk_bphy, cnxk_bphy_cgx, intel_ioat_bdw, intel_ioat_skx, intel_ioat_icx, intel_idxd_spr,
                 intel_ntb_skx, intel_ntb_icx,
                 octeontx2_dma]