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eal/arm: adjust memory barriers for IO on ARMv8

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Change the barrier APIs for IO to reflect that Armv8-a is other-multi-copy
atomicity memory model.

Armv8-a memory model has been strengthened to require
other-multi-copy atomicity. This property requires memory accesses
from an observer to become visible to all other observers
simultaneously [3]. This means

a) A write arriving at an endpoint shared between multiple CPUs is
   visible to all CPUs
b) A write that is visible to all CPUs is also visible to all other
   observers in the shareability domain

This allows for using cheaper DMB instructions in the place of DSB
for devices that are visible to all CPUs (i.e. devices that DPDK
caters to).

Please refer to [1], [2] and [3] for more information.

[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=22ec71615d824f4f11d38d0e55a88d8956b7e45f
[2] https://www.youtube.com/watch?v=i6DayghhA8Q
[3] https://www.cl.cam.ac.uk/~pes20/armv8-mca/

Signed-off-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Tested-by: Ruifeng Wang <ruifeng.wang@arm.com>
This commit is contained in:
Honnappa Nagarahalli 2020-07-06 18:43:31 -05:00 committed by David Marchand
parent 06df45af6e
commit 264f7f80e1
2 changed files with 13 additions and 6 deletions
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7
doc/guides/rel_notes/release_20_08.rst
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@ -56,6 +56,13 @@ New Features
Also, make sure to start the actual text at the margin.
=========================================================
* **rte_*mb APIs are updated to use DMB instruction for ARMv8.**
ARMv8 memory model has been strengthened to require other-multi-copy
atomicity. This allows for using DMB instruction instead of DSB for IO
barriers. rte_*mb APIs, for ARMv8 platforms, are changed to use DMB
instruction to reflect this.
* **Added the support for vfio-pci new VF token interface.**
From Linux 5.7, vfio-pci supports to bind both SR-IOV PF and the created VFs,

12
lib/librte_eal/arm/include/rte_atomic_64.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2015 Cavium, Inc
* Copyright(c) 2019 Arm Limited
* Copyright(c) 2020 Arm Limited
*/
#ifndef _RTE_ATOMIC_ARM64_H_
@ -19,11 +19,11 @@ extern "C" {
#include <rte_compat.h>
#include <rte_debug.h>
#define rte_mb() asm volatile("dsb sy" : : : "memory")
#define rte_mb() asm volatile("dmb osh" : : : "memory")
#define rte_wmb() asm volatile("dsb st" : : : "memory")
#define rte_wmb() asm volatile("dmb oshst" : : : "memory")
#define rte_rmb() asm volatile("dsb ld" : : : "memory")
#define rte_rmb() asm volatile("dmb oshld" : : : "memory")
#define rte_smp_mb() asm volatile("dmb ish" : : : "memory")
@ -37,9 +37,9 @@ extern "C" {
#define rte_io_rmb() rte_rmb()
#define rte_cio_wmb() asm volatile("dmb oshst" : : : "memory")
#define rte_cio_wmb() rte_wmb()
#define rte_cio_rmb() asm volatile("dmb oshld" : : : "memory")
#define rte_cio_rmb() rte_rmb()
/*------------------------ 128 bit atomic operations -------------------------*/