igb: update VMDq/DCB support
Signed-off-by: Intel
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32e7aa0b3a
commit
28f682a176
@ -1584,6 +1584,36 @@ igb_alloc_rx_queue_mbufs(struct igb_rx_queue *rxq)
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return 0;
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}
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#define E1000_MRQC_DEF_Q_SHIFT (3)
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static int
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igb_dev_mq_rx_configure(struct rte_eth_dev *dev)
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{
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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uint32_t mrqc;
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if (RTE_ETH_DEV_SRIOV(dev).active == ETH_8_POOLS) {
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/*
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* SRIOV active scheme
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* FIXME if support RSS together with VMDq & SRIOV
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*/
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mrqc = E1000_MRQC_ENABLE_VMDQ;
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/* 011b Def_Q ignore, according to VT_CTL.DEF_PL */
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mrqc |= 0x3 << E1000_MRQC_DEF_Q_SHIFT;
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E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
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} else if(RTE_ETH_DEV_SRIOV(dev).active == 0) {
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/*
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* SRIOV inactive scheme
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*/
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if (dev->data->nb_rx_queues > 1)
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igb_rss_configure(dev);
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else
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igb_rss_disable(dev);
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}
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return 0;
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}
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int
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eth_igb_rx_init(struct rte_eth_dev *dev)
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{
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@ -1733,10 +1763,7 @@ eth_igb_rx_init(struct rte_eth_dev *dev)
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/*
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* Configure RSS if device configured with multiple RX queues.
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*/
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if (dev->data->nb_rx_queues > 1)
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igb_rss_configure(dev);
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else
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igb_rss_disable(dev);
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igb_dev_mq_rx_configure(dev);
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/*
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* Setup the Checksum Register.
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