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net/e1000/base: add missing register defines

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Added defines for the EEC, SHADOWINF and FLFWUPDATE registers needed for
the nvmupd_validate_offset function to correctly validate the NVM update
offset.

Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>
This commit is contained in:
Guinan Sun 2020-07-06 08:12:08 +00:00 committed by Ferruh Yigit
parent 7ee1a3b273
commit 2c7fe65ab9
1 changed files with 5 additions and 0 deletions
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5
drivers/net/e1000/base/e1000_regs.h
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@ -140,6 +140,8 @@
#define E1000_EMIDATA 0x11 /* Extended Memory Indirect Data */
/* Shadow Ram Write Register - RW */
#define E1000_SRWR 0x12018
#define E1000_EEC_REG 0x12010
#define E1000_I210_FLMNGCTL 0x12038
#define E1000_I210_FLMNGDATA 0x1203C
#define E1000_I210_FLMNGCNT 0x12040
@ -150,6 +152,9 @@
#define E1000_I210_FLA 0x1201C
#define E1000_SHADOWINF 0x12068
#define E1000_FLFWUPDATE 0x12108
#define E1000_INVM_DATA_REG(_n) (0x12120 + 4*(_n))
#define E1000_INVM_SIZE 64 /* Number of INVM Data Registers */