ixgbe: fix data access on big endian cpu
1. cpu use data owned by ixgbe must use rte_le_to_cpu_xx(...) 2. cpu fill data to ixgbe must use rte_cpu_to_le_xx(...) 3. checking pci status with converted constant Signed-off-by: Xuelin Shi <xuelin.shi@freescale.com> Acked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>
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8d2686c0e4
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2e49ae79eb
@ -130,7 +130,7 @@ ixgbe_tx_free_bufs(struct ixgbe_tx_queue *txq)
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/* check DD bit on threshold descriptor */
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status = txq->tx_ring[txq->tx_next_dd].wb.status;
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if (! (status & IXGBE_ADVTXD_STAT_DD))
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if (!(status & rte_cpu_to_le_32(IXGBE_ADVTXD_STAT_DD)))
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return 0;
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/*
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@ -175,11 +175,14 @@ tx4(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
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pkt_len = (*pkts)->data_len;
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/* write data to descriptor */
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txdp->read.buffer_addr = buf_dma_addr;
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txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
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txdp->read.cmd_type_len =
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((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
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rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
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txdp->read.olinfo_status =
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(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
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rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
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rte_prefetch0(&(*pkts)->pool);
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}
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}
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@ -195,11 +198,11 @@ tx1(volatile union ixgbe_adv_tx_desc *txdp, struct rte_mbuf **pkts)
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pkt_len = (*pkts)->data_len;
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/* write data to descriptor */
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txdp->read.buffer_addr = buf_dma_addr;
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txdp->read.buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
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txdp->read.cmd_type_len =
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((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
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rte_cpu_to_le_32((uint32_t)DCMD_DTYP_FLAGS | pkt_len);
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txdp->read.olinfo_status =
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(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
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rte_cpu_to_le_32(pkt_len << IXGBE_ADVTXD_PAYLEN_SHIFT);
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rte_prefetch0(&(*pkts)->pool);
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}
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@ -511,6 +514,7 @@ ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
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uint16_t nb_tx_desc = txq->nb_tx_desc;
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uint16_t desc_to_clean_to;
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uint16_t nb_tx_to_clean;
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uint32_t status;
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/* Determine the last descriptor needing to be cleaned */
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desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
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@ -519,7 +523,8 @@ ixgbe_xmit_cleanup(struct ixgbe_tx_queue *txq)
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/* Check to make sure the last descriptor to clean is done */
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desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
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if (! (txr[desc_to_clean_to].wb.status & IXGBE_TXD_STAT_DD))
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status = txr[desc_to_clean_to].wb.status;
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if (!(status & rte_cpu_to_le_32(IXGBE_TXD_STAT_DD)))
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{
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PMD_TX_FREE_LOG(DEBUG,
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"TX descriptor %4u is not done"
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@ -1061,14 +1066,15 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
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int s[LOOK_AHEAD], nb_dd;
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#endif /* RTE_NEXT_ABI */
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int i, j, nb_rx = 0;
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uint32_t status;
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/* get references to current descriptor and S/W ring entry */
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rxdp = &rxq->rx_ring[rxq->rx_tail];
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rxep = &rxq->sw_ring[rxq->rx_tail];
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status = rxdp->wb.upper.status_error;
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/* check to make sure there is at least 1 packet to receive */
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if (! (rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD))
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if (!(status & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
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return 0;
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/*
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@ -1080,7 +1086,7 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
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{
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/* Read desc statuses backwards to avoid race condition */
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for (j = LOOK_AHEAD-1; j >= 0; --j)
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s[j] = rxdp[j].wb.upper.status_error;
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s[j] = rte_le_to_cpu_32(rxdp[j].wb.upper.status_error);
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#ifdef RTE_NEXT_ABI
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for (j = LOOK_AHEAD - 1; j >= 0; --j)
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@ -1098,7 +1104,8 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
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/* Translate descriptor info to mbuf format */
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for (j = 0; j < nb_dd; ++j) {
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mb = rxep[j].mbuf;
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pkt_len = (uint16_t)(rxdp[j].wb.upper.length - rxq->crc_len);
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pkt_len = rte_le_to_cpu_16(rxdp[j].wb.upper.length) -
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rxq->crc_len;
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mb->data_len = pkt_len;
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mb->pkt_len = pkt_len;
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mb->vlan_tci = rte_le_to_cpu_16(rxdp[j].wb.upper.vlan);
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@ -1114,7 +1121,8 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
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ixgbe_rxd_pkt_info_to_pkt_type(pkt_info[j]);
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#else /* RTE_NEXT_ABI */
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pkt_flags = rx_desc_hlen_type_rss_to_pkt_flags(
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rxdp[j].wb.lower.lo_dword.data);
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rte_le_to_cpu_32(
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rxdp[j].wb.lower.lo_dword.data));
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/* reuse status field from scan list */
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pkt_flags |= rx_desc_status_to_pkt_flags(s[j]);
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pkt_flags |= rx_desc_error_to_pkt_flags(s[j]);
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@ -1122,12 +1130,14 @@ ixgbe_rx_scan_hw_ring(struct ixgbe_rx_queue *rxq)
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#endif /* RTE_NEXT_ABI */
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if (likely(pkt_flags & PKT_RX_RSS_HASH))
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mb->hash.rss = rxdp[j].wb.lower.hi_dword.rss;
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mb->hash.rss = rte_le_to_cpu_32(
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rxdp[j].wb.lower.hi_dword.rss);
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else if (pkt_flags & PKT_RX_FDIR) {
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mb->hash.fdir.hash =
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(uint16_t)((rxdp[j].wb.lower.hi_dword.csum_ip.csum)
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& IXGBE_ATR_HASH_MASK);
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mb->hash.fdir.id = rxdp[j].wb.lower.hi_dword.csum_ip.ip_id;
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mb->hash.fdir.hash = rte_le_to_cpu_16(
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rxdp[j].wb.lower.hi_dword.csum_ip.csum) &
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IXGBE_ATR_HASH_MASK;
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mb->hash.fdir.id = rte_le_to_cpu_16(
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rxdp[j].wb.lower.hi_dword.csum_ip.ip_id);
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}
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}
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@ -1346,7 +1356,7 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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*/
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rxdp = &rx_ring[rx_id];
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staterr = rxdp->wb.upper.status_error;
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if (! (staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
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if (!(staterr & rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD)))
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break;
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rxd = *rxdp;
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@ -1464,12 +1474,14 @@ ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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#endif /* RTE_NEXT_ABI */
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if (likely(pkt_flags & PKT_RX_RSS_HASH))
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rxm->hash.rss = rxd.wb.lower.hi_dword.rss;
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rxm->hash.rss = rte_le_to_cpu_32(
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rxd.wb.lower.hi_dword.rss);
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else if (pkt_flags & PKT_RX_FDIR) {
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rxm->hash.fdir.hash =
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(uint16_t)((rxd.wb.lower.hi_dword.csum_ip.csum)
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& IXGBE_ATR_HASH_MASK);
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rxm->hash.fdir.id = rxd.wb.lower.hi_dword.csum_ip.ip_id;
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rxm->hash.fdir.hash = rte_le_to_cpu_16(
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rxd.wb.lower.hi_dword.csum_ip.csum) &
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IXGBE_ATR_HASH_MASK;
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rxm->hash.fdir.id = rte_le_to_cpu_16(
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rxd.wb.lower.hi_dword.csum_ip.ip_id);
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}
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/*
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* Store the mbuf address into the next entry of the array
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@ -1980,7 +1992,7 @@ ixgbe_reset_tx_queue(struct ixgbe_tx_queue *txq)
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prev = (uint16_t) (txq->nb_tx_desc - 1);
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for (i = 0; i < txq->nb_tx_desc; i++) {
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volatile union ixgbe_adv_tx_desc *txd = &txq->tx_ring[i];
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txd->wb.status = IXGBE_TXD_STAT_DD;
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txd->wb.status = rte_cpu_to_le_32(IXGBE_TXD_STAT_DD);
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txe[i].mbuf = NULL;
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txe[i].last_id = i;
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txe[prev].next_id = i;
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@ -2586,7 +2598,8 @@ ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
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rxdp = &(rxq->rx_ring[rxq->rx_tail]);
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while ((desc < rxq->nb_rx_desc) &&
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(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD)) {
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(rxdp->wb.upper.status_error &
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rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD))) {
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desc += IXGBE_RXQ_SCAN_INTERVAL;
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rxdp += IXGBE_RXQ_SCAN_INTERVAL;
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if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
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@ -2611,7 +2624,8 @@ ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
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desc -= rxq->nb_rx_desc;
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rxdp = &rxq->rx_ring[desc];
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return !!(rxdp->wb.upper.status_error & IXGBE_RXDADV_STAT_DD);
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return !!(rxdp->wb.upper.status_error &
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rte_cpu_to_le_32(IXGBE_RXDADV_STAT_DD));
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}
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void __attribute__((cold))
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