net/txgbe: add interrupt operation
Add device interrupt handler and setup misx interrupt. Signed-off-by: Jiawen Wu <jiawenwu@trustnetic.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Jiawen Wu
Ferruh Yigit
parent
86d8adc770
commit
2fc745e6b6
@ -5,6 +5,8 @@
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;
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[Features]
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Speed capabilities = Y
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Link status = Y
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Link status event = Y
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Linux UIO = Y
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Linux VFIO = Y
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ARMv8 = Y
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@ -7,6 +7,11 @@ TXGBE Poll Mode Driver
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The TXGBE PMD (librte_pmd_txgbe) provides poll mode driver support
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for Wangxun 10 Gigabit Ethernet NICs.
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Features
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--------
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- Link state information
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Prerequisites
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-------------
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@ -378,6 +378,14 @@ struct txgbe_mbx_info {
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s32 (*check_for_rst)(struct txgbe_hw *hw, u16 mbx_id);
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};
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enum txgbe_isb_idx {
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TXGBE_ISB_HEADER,
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TXGBE_ISB_MISC,
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TXGBE_ISB_VEC0,
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TXGBE_ISB_VEC1,
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TXGBE_ISB_MAX
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};
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struct txgbe_hw {
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void IOMEM *hw_addr;
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void *back;
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@ -8,8 +8,12 @@
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#include <string.h>
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#include <rte_common.h>
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#include <rte_ethdev_pci.h>
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#include <rte_interrupts.h>
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#include <rte_pci.h>
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#include <rte_memory.h>
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#include <rte_eal.h>
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#include <rte_alarm.h>
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#include "txgbe_logs.h"
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#include "base/txgbe.h"
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@ -18,6 +22,17 @@
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static int txgbe_dev_close(struct rte_eth_dev *dev);
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static void txgbe_dev_link_status_print(struct rte_eth_dev *dev);
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static int txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on);
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static int txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev);
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static int txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev);
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static int txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev);
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static int txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
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struct rte_intr_handle *handle);
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static void txgbe_dev_interrupt_handler(void *param);
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static void txgbe_dev_interrupt_delayed_handler(void *param);
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static void txgbe_configure_msix(struct rte_eth_dev *dev);
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/*
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* The set of PCI devices this driver supports
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*/
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@ -59,6 +74,29 @@ txgbe_is_sfp(struct txgbe_hw *hw)
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}
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}
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static inline void
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txgbe_enable_intr(struct rte_eth_dev *dev)
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{
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struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
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struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
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wr32(hw, TXGBE_IENMISC, intr->mask_misc);
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wr32(hw, TXGBE_IMC(0), TXGBE_IMC_MASK);
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wr32(hw, TXGBE_IMC(1), TXGBE_IMC_MASK);
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txgbe_flush(hw);
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}
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static void
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txgbe_disable_intr(struct txgbe_hw *hw)
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{
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PMD_INIT_FUNC_TRACE();
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wr32(hw, TXGBE_IENMISC, ~BIT_MASK32);
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wr32(hw, TXGBE_IMS(0), TXGBE_IMC_MASK);
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wr32(hw, TXGBE_IMS(1), TXGBE_IMC_MASK);
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txgbe_flush(hw);
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}
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static int
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eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
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{
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@ -145,6 +183,9 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
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return -EIO;
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}
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/* disable interrupt */
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txgbe_disable_intr(hw);
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/* Allocate memory for storing MAC addresses */
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eth_dev->data->mac_addrs = rte_zmalloc("txgbe", RTE_ETHER_ADDR_LEN *
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hw->mac.num_rar_entries, 0);
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@ -182,9 +223,15 @@ eth_txgbe_dev_init(struct rte_eth_dev *eth_dev, void *init_params __rte_unused)
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eth_dev->data->port_id, pci_dev->id.vendor_id,
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pci_dev->id.device_id);
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rte_intr_callback_register(intr_handle,
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txgbe_dev_interrupt_handler, eth_dev);
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/* enable uio/vfio intr/eventfd mapping */
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rte_intr_enable(intr_handle);
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/* enable support intr */
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txgbe_enable_intr(eth_dev);
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return 0;
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}
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@ -252,6 +299,20 @@ static struct rte_pci_driver rte_txgbe_pmd = {
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.remove = eth_txgbe_pci_remove,
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};
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static void
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txgbe_dev_phy_intr_setup(struct rte_eth_dev *dev)
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{
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struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
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struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
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uint32_t gpie;
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gpie = rd32(hw, TXGBE_GPIOINTEN);
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gpie |= TXGBE_GPIOBIT_6;
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wr32(hw, TXGBE_GPIOINTEN, gpie);
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intr->mask_misc |= TXGBE_ICRMISC_GPIO;
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}
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/*
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* Reset and stop device.
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*/
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@ -260,12 +321,30 @@ txgbe_dev_close(struct rte_eth_dev *dev)
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{
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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int retries = 0;
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int ret;
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PMD_INIT_FUNC_TRACE();
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/* disable uio intr before callback unregister */
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rte_intr_disable(intr_handle);
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do {
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ret = rte_intr_callback_unregister(intr_handle,
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txgbe_dev_interrupt_handler, dev);
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if (ret >= 0 || ret == -ENOENT) {
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break;
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} else if (ret != -EAGAIN) {
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PMD_INIT_LOG(ERR,
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"intr callback unregister failed: %d",
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ret);
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}
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rte_delay_ms(100);
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} while (retries++ < (10 + TXGBE_LINK_UP_TIME));
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/* cancel the delay handler before remove dev */
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rte_eal_alarm_cancel(txgbe_dev_interrupt_delayed_handler, dev);
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rte_free(dev->data->mac_addrs);
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dev->data->mac_addrs = NULL;
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@ -338,6 +417,394 @@ txgbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
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return 0;
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}
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static int
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txgbe_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete)
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{
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RTE_SET_USED(dev);
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RTE_SET_USED(wait_to_complete);
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return 0;
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}
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/**
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* It clears the interrupt causes and enables the interrupt.
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* It will be called once only during nic initialized.
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*
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* @param dev
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* Pointer to struct rte_eth_dev.
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* @param on
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* Enable or Disable.
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*
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* @return
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* - On success, zero.
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* - On failure, a negative value.
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*/
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static int
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txgbe_dev_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
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{
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struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
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txgbe_dev_link_status_print(dev);
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if (on)
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intr->mask_misc |= TXGBE_ICRMISC_LSC;
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else
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intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
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return 0;
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}
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/**
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* It clears the interrupt causes and enables the interrupt.
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* It will be called once only during nic initialized.
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*
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* @param dev
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* Pointer to struct rte_eth_dev.
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*
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* @return
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* - On success, zero.
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* - On failure, a negative value.
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*/
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static int
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txgbe_dev_rxq_interrupt_setup(struct rte_eth_dev *dev)
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{
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struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
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intr->mask[0] |= TXGBE_ICR_MASK;
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intr->mask[1] |= TXGBE_ICR_MASK;
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return 0;
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}
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/**
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* It clears the interrupt causes and enables the interrupt.
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* It will be called once only during nic initialized.
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*
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* @param dev
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* Pointer to struct rte_eth_dev.
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*
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* @return
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* - On success, zero.
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* - On failure, a negative value.
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*/
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static int
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txgbe_dev_macsec_interrupt_setup(struct rte_eth_dev *dev)
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{
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struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
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intr->mask_misc |= TXGBE_ICRMISC_LNKSEC;
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return 0;
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}
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/*
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* It reads ICR and sets flag (TXGBE_ICRMISC_LSC) for the link_update.
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*
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* @param dev
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* Pointer to struct rte_eth_dev.
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*
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* @return
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* - On success, zero.
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* - On failure, a negative value.
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*/
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static int
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txgbe_dev_interrupt_get_status(struct rte_eth_dev *dev)
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{
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uint32_t eicr;
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struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
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struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
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/* clear all cause mask */
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txgbe_disable_intr(hw);
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/* read-on-clear nic registers here */
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eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
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PMD_DRV_LOG(DEBUG, "eicr %x", eicr);
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intr->flags = 0;
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/* set flag for async link update */
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if (eicr & TXGBE_ICRMISC_LSC)
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intr->flags |= TXGBE_FLAG_NEED_LINK_UPDATE;
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if (eicr & TXGBE_ICRMISC_VFMBX)
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intr->flags |= TXGBE_FLAG_MAILBOX;
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if (eicr & TXGBE_ICRMISC_LNKSEC)
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intr->flags |= TXGBE_FLAG_MACSEC;
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if (eicr & TXGBE_ICRMISC_GPIO)
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intr->flags |= TXGBE_FLAG_PHY_INTERRUPT;
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return 0;
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}
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/**
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* It gets and then prints the link status.
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*
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* @param dev
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* Pointer to struct rte_eth_dev.
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*
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* @return
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* - On success, zero.
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* - On failure, a negative value.
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*/
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static void
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txgbe_dev_link_status_print(struct rte_eth_dev *dev)
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{
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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struct rte_eth_link link;
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rte_eth_linkstatus_get(dev, &link);
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if (link.link_status) {
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PMD_INIT_LOG(INFO, "Port %d: Link Up - speed %u Mbps - %s",
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(int)(dev->data->port_id),
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(unsigned int)link.link_speed,
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link.link_duplex == ETH_LINK_FULL_DUPLEX ?
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"full-duplex" : "half-duplex");
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} else {
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PMD_INIT_LOG(INFO, " Port %d: Link Down",
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(int)(dev->data->port_id));
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}
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PMD_INIT_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
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pci_dev->addr.domain,
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pci_dev->addr.bus,
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pci_dev->addr.devid,
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pci_dev->addr.function);
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}
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/*
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* It executes link_update after knowing an interrupt occurred.
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*
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* @param dev
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* Pointer to struct rte_eth_dev.
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*
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* @return
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* - On success, zero.
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* - On failure, a negative value.
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*/
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static int
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txgbe_dev_interrupt_action(struct rte_eth_dev *dev,
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struct rte_intr_handle *intr_handle)
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{
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struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
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int64_t timeout;
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struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
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PMD_DRV_LOG(DEBUG, "intr action type %d", intr->flags);
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if (intr->flags & TXGBE_FLAG_MAILBOX)
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intr->flags &= ~TXGBE_FLAG_MAILBOX;
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if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
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hw->phy.handle_lasi(hw);
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intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
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}
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if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
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struct rte_eth_link link;
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/*get the link status before link update, for predicting later*/
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rte_eth_linkstatus_get(dev, &link);
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txgbe_dev_link_update(dev, 0);
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/* likely to up */
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if (!link.link_status)
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/* handle it 1 sec later, wait it being stable */
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timeout = TXGBE_LINK_UP_CHECK_TIMEOUT;
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/* likely to down */
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else
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/* handle it 4 sec later, wait it being stable */
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timeout = TXGBE_LINK_DOWN_CHECK_TIMEOUT;
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txgbe_dev_link_status_print(dev);
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if (rte_eal_alarm_set(timeout * 1000,
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txgbe_dev_interrupt_delayed_handler,
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(void *)dev) < 0) {
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PMD_DRV_LOG(ERR, "Error setting alarm");
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} else {
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/* remember original mask */
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intr->mask_misc_orig = intr->mask_misc;
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/* only disable lsc interrupt */
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intr->mask_misc &= ~TXGBE_ICRMISC_LSC;
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}
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}
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PMD_DRV_LOG(DEBUG, "enable intr immediately");
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txgbe_enable_intr(dev);
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rte_intr_enable(intr_handle);
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return 0;
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}
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/**
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* Interrupt handler which shall be registered for alarm callback for delayed
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* handling specific interrupt to wait for the stable nic state. As the
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* NIC interrupt state is not stable for txgbe after link is just down,
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* it needs to wait 4 seconds to get the stable status.
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*
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* @param handle
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* Pointer to interrupt handle.
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* @param param
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* The address of parameter (struct rte_eth_dev *) registered before.
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*
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* @return
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* void
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*/
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static void
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txgbe_dev_interrupt_delayed_handler(void *param)
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{
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struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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struct txgbe_interrupt *intr = TXGBE_DEV_INTR(dev);
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struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
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uint32_t eicr;
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txgbe_disable_intr(hw);
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eicr = ((u32 *)hw->isb_mem)[TXGBE_ISB_MISC];
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if (intr->flags & TXGBE_FLAG_PHY_INTERRUPT) {
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hw->phy.handle_lasi(hw);
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intr->flags &= ~TXGBE_FLAG_PHY_INTERRUPT;
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}
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if (intr->flags & TXGBE_FLAG_NEED_LINK_UPDATE) {
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txgbe_dev_link_update(dev, 0);
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intr->flags &= ~TXGBE_FLAG_NEED_LINK_UPDATE;
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txgbe_dev_link_status_print(dev);
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rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
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NULL);
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}
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if (intr->flags & TXGBE_FLAG_MACSEC) {
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rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_MACSEC,
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NULL);
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intr->flags &= ~TXGBE_FLAG_MACSEC;
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}
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/* restore original mask */
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intr->mask_misc = intr->mask_misc_orig;
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intr->mask_misc_orig = 0;
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PMD_DRV_LOG(DEBUG, "enable intr in delayed handler S[%08x]", eicr);
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txgbe_enable_intr(dev);
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rte_intr_enable(intr_handle);
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}
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/**
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* Interrupt handler triggered by NIC for handling
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* specific interrupt.
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*
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* @param handle
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* Pointer to interrupt handle.
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* @param param
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* The address of parameter (struct rte_eth_dev *) registered before.
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*
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* @return
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* void
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*/
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static void
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txgbe_dev_interrupt_handler(void *param)
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{
|
||||
struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
|
||||
|
||||
txgbe_dev_interrupt_get_status(dev);
|
||||
txgbe_dev_interrupt_action(dev, dev->intr_handle);
|
||||
}
|
||||
|
||||
/**
|
||||
* set the IVAR registers, mapping interrupt causes to vectors
|
||||
* @param hw
|
||||
* pointer to txgbe_hw struct
|
||||
* @direction
|
||||
* 0 for Rx, 1 for Tx, -1 for other causes
|
||||
* @queue
|
||||
* queue to map the corresponding interrupt to
|
||||
* @msix_vector
|
||||
* the vector to map to the corresponding queue
|
||||
*/
|
||||
void
|
||||
txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
|
||||
uint8_t queue, uint8_t msix_vector)
|
||||
{
|
||||
uint32_t tmp, idx;
|
||||
|
||||
if (direction == -1) {
|
||||
/* other causes */
|
||||
msix_vector |= TXGBE_IVARMISC_VLD;
|
||||
idx = 0;
|
||||
tmp = rd32(hw, TXGBE_IVARMISC);
|
||||
tmp &= ~(0xFF << idx);
|
||||
tmp |= (msix_vector << idx);
|
||||
wr32(hw, TXGBE_IVARMISC, tmp);
|
||||
} else {
|
||||
/* rx or tx causes */
|
||||
/* Workround for ICR lost */
|
||||
idx = ((16 * (queue & 1)) + (8 * direction));
|
||||
tmp = rd32(hw, TXGBE_IVAR(queue >> 1));
|
||||
tmp &= ~(0xFF << idx);
|
||||
tmp |= (msix_vector << idx);
|
||||
wr32(hw, TXGBE_IVAR(queue >> 1), tmp);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* Sets up the hardware to properly generate MSI-X interrupts
|
||||
* @hw
|
||||
* board private structure
|
||||
*/
|
||||
static void
|
||||
txgbe_configure_msix(struct rte_eth_dev *dev)
|
||||
{
|
||||
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
|
||||
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
|
||||
struct txgbe_hw *hw = TXGBE_DEV_HW(dev);
|
||||
uint32_t queue_id, base = TXGBE_MISC_VEC_ID;
|
||||
uint32_t vec = TXGBE_MISC_VEC_ID;
|
||||
uint32_t gpie;
|
||||
|
||||
/* won't configure msix register if no mapping is done
|
||||
* between intr vector and event fd
|
||||
* but if misx has been enabled already, need to configure
|
||||
* auto clean, auto mask and throttling.
|
||||
*/
|
||||
gpie = rd32(hw, TXGBE_GPIE);
|
||||
if (!rte_intr_dp_is_en(intr_handle) &&
|
||||
!(gpie & TXGBE_GPIE_MSIX))
|
||||
return;
|
||||
|
||||
if (rte_intr_allow_others(intr_handle)) {
|
||||
base = TXGBE_RX_VEC_START;
|
||||
vec = base;
|
||||
}
|
||||
|
||||
/* setup GPIE for MSI-x mode */
|
||||
gpie = rd32(hw, TXGBE_GPIE);
|
||||
gpie |= TXGBE_GPIE_MSIX;
|
||||
wr32(hw, TXGBE_GPIE, gpie);
|
||||
|
||||
/* Populate the IVAR table and set the ITR values to the
|
||||
* corresponding register.
|
||||
*/
|
||||
if (rte_intr_dp_is_en(intr_handle)) {
|
||||
for (queue_id = 0; queue_id < dev->data->nb_rx_queues;
|
||||
queue_id++) {
|
||||
/* by default, 1:1 mapping */
|
||||
txgbe_set_ivar_map(hw, 0, queue_id, vec);
|
||||
intr_handle->intr_vec[queue_id] = vec;
|
||||
if (vec < base + intr_handle->nb_efd - 1)
|
||||
vec++;
|
||||
}
|
||||
|
||||
txgbe_set_ivar_map(hw, -1, 1, TXGBE_MISC_VEC_ID);
|
||||
}
|
||||
wr32(hw, TXGBE_ITR(TXGBE_MISC_VEC_ID),
|
||||
TXGBE_ITR_IVAL_10G(TXGBE_QUEUE_ITR_INTERVAL_DEFAULT)
|
||||
| TXGBE_ITR_WRDSA);
|
||||
}
|
||||
|
||||
static const struct eth_dev_ops txgbe_eth_dev_ops = {
|
||||
.dev_infos_get = txgbe_dev_info_get,
|
||||
};
|
||||
|
||||
@ -7,12 +7,21 @@
|
||||
|
||||
#include "base/txgbe.h"
|
||||
|
||||
/* need update link, bit flag */
|
||||
#define TXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
|
||||
#define TXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
|
||||
#define TXGBE_FLAG_PHY_INTERRUPT (uint32_t)(1 << 2)
|
||||
#define TXGBE_FLAG_MACSEC (uint32_t)(1 << 3)
|
||||
#define TXGBE_FLAG_NEED_LINK_CONFIG (uint32_t)(1 << 4)
|
||||
|
||||
/*
|
||||
* Defines that were not part of txgbe_type.h as they are not used by the
|
||||
* FreeBSD driver.
|
||||
*/
|
||||
#define TXGBE_HKEY_MAX_INDEX 10
|
||||
|
||||
#define TXGBE_QUEUE_ITR_INTERVAL_DEFAULT 500 /* 500us */
|
||||
|
||||
#define TXGBE_RSS_OFFLOAD_ALL ( \
|
||||
ETH_RSS_IPV4 | \
|
||||
ETH_RSS_NONFRAG_IPV4_TCP | \
|
||||
@ -24,16 +33,37 @@
|
||||
ETH_RSS_IPV6_TCP_EX | \
|
||||
ETH_RSS_IPV6_UDP_EX)
|
||||
|
||||
#define TXGBE_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
|
||||
#define TXGBE_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
|
||||
|
||||
/* structure for interrupt relative data */
|
||||
struct txgbe_interrupt {
|
||||
uint32_t flags;
|
||||
uint32_t mask_misc;
|
||||
/* to save original mask during delayed handler */
|
||||
uint32_t mask_misc_orig;
|
||||
uint32_t mask[2];
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure to store private data for each driver instance (for each port).
|
||||
*/
|
||||
struct txgbe_adapter {
|
||||
struct txgbe_hw hw;
|
||||
struct txgbe_interrupt intr;
|
||||
};
|
||||
|
||||
#define TXGBE_DEV_HW(dev) \
|
||||
(&((struct txgbe_adapter *)(dev)->data->dev_private)->hw)
|
||||
|
||||
#define TXGBE_DEV_INTR(dev) \
|
||||
(&((struct txgbe_adapter *)(dev)->data->dev_private)->intr)
|
||||
|
||||
void txgbe_set_ivar_map(struct txgbe_hw *hw, int8_t direction,
|
||||
uint8_t queue, uint8_t msix_vector);
|
||||
|
||||
#define TXGBE_LINK_DOWN_CHECK_TIMEOUT 4000 /* ms */
|
||||
#define TXGBE_LINK_UP_CHECK_TIMEOUT 1000 /* ms */
|
||||
#define TXGBE_VMDQ_NUM_UC_MAC 4096 /* Maximum nb. of UC MAC addr. */
|
||||
|
||||
/*
|
||||
|
||||
Loading…
Reference in New Issue
Block a user