common/octeontx2: add PF to VF mailbox IRQ and msg handlers
PF has additional responsibility being server for VF messages and forward to AF and once AF process it then forward the response back to VF. otx2_vf_pf_mbox_irq() will process the VF mailbox request and af_pf_wait_msg() will until getting a response back from AF. Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com> Signed-off-by: Krzysztof Kanas <kkanas@marvell.com>
This commit is contained in:
Nithin Dabilpuram
Thomas Monjalon
parent
9190acdd7a
commit
302e7d4958
@ -7,6 +7,7 @@
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#include <sys/mman.h>
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#include <unistd.h>
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#include <rte_alarm.h>
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#include <rte_common.h>
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#include <rte_eal.h>
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#include <rte_memcpy.h>
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@ -50,6 +51,200 @@ mbox_mem_unmap(void *va, size_t size)
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munmap(va, size);
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}
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static int
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af_pf_wait_msg(struct otx2_dev *dev, uint16_t vf, int num_msg)
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{
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uint32_t timeout = 0, sleep = 1; struct otx2_mbox *mbox = dev->mbox;
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struct otx2_mbox_dev *mdev = &mbox->dev[0];
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volatile uint64_t int_status;
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struct mbox_hdr *req_hdr;
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struct mbox_msghdr *msg;
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struct mbox_msghdr *rsp;
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uint64_t offset;
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size_t size;
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int i;
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/* We need to disable PF interrupts. We are in timer interrupt */
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otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
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/* Send message */
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otx2_mbox_msg_send(mbox, 0);
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do {
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rte_delay_ms(sleep);
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timeout++;
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if (timeout >= MBOX_RSP_TIMEOUT) {
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otx2_err("Routed messages %d timeout: %dms",
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num_msg, MBOX_RSP_TIMEOUT);
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break;
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}
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int_status = otx2_read64(dev->bar2 + RVU_PF_INT);
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} while ((int_status & 0x1) != 0x1);
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/* Clear */
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otx2_write64(~0ull, dev->bar2 + RVU_PF_INT);
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/* Enable interrupts */
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otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
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rte_spinlock_lock(&mdev->mbox_lock);
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req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
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if (req_hdr->num_msgs != num_msg)
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otx2_err("Routed messages: %d received: %d", num_msg,
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req_hdr->num_msgs);
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/* Get messages from mbox */
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offset = mbox->rx_start +
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RTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
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for (i = 0; i < req_hdr->num_msgs; i++) {
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msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
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size = mbox->rx_start + msg->next_msgoff - offset;
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/* Reserve PF/VF mbox message */
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size = RTE_ALIGN(size, MBOX_MSG_ALIGN);
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rsp = otx2_mbox_alloc_msg(&dev->mbox_vfpf, vf, size);
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otx2_mbox_rsp_init(msg->id, rsp);
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/* Copy message from AF<->PF mbox to PF<->VF mbox */
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otx2_mbox_memcpy((uint8_t *)rsp + sizeof(struct mbox_msghdr),
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(uint8_t *)msg + sizeof(struct mbox_msghdr),
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size - sizeof(struct mbox_msghdr));
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/* Set status and sender pf_func data */
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rsp->rc = msg->rc;
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rsp->pcifunc = msg->pcifunc;
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offset = mbox->rx_start + msg->next_msgoff;
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}
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rte_spinlock_unlock(&mdev->mbox_lock);
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return req_hdr->num_msgs;
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}
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static int
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vf_pf_process_msgs(struct otx2_dev *dev, uint16_t vf)
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{
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int offset, routed = 0; struct otx2_mbox *mbox = &dev->mbox_vfpf;
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struct otx2_mbox_dev *mdev = &mbox->dev[vf];
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struct mbox_hdr *req_hdr;
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struct mbox_msghdr *msg;
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size_t size;
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uint16_t i;
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req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
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if (!req_hdr->num_msgs)
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return 0;
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offset = mbox->rx_start + RTE_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
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for (i = 0; i < req_hdr->num_msgs; i++) {
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msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
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size = mbox->rx_start + msg->next_msgoff - offset;
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/* RVU_PF_FUNC_S */
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msg->pcifunc = otx2_pfvf_func(dev->pf, vf);
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if (msg->id == MBOX_MSG_READY) {
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struct ready_msg_rsp *rsp;
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uint16_t max_bits = sizeof(dev->active_vfs[0]) * 8;
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/* Handle READY message in PF */
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dev->active_vfs[vf / max_bits] |=
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BIT_ULL(vf % max_bits);
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rsp = (struct ready_msg_rsp *)
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otx2_mbox_alloc_msg(mbox, vf, sizeof(*rsp));
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otx2_mbox_rsp_init(msg->id, rsp);
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/* PF/VF function ID */
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rsp->hdr.pcifunc = msg->pcifunc;
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rsp->hdr.rc = 0;
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} else {
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struct mbox_msghdr *af_req;
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/* Reserve AF/PF mbox message */
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size = RTE_ALIGN(size, MBOX_MSG_ALIGN);
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af_req = otx2_mbox_alloc_msg(dev->mbox, 0, size);
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otx2_mbox_req_init(msg->id, af_req);
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/* Copy message from VF<->PF mbox to PF<->AF mbox */
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otx2_mbox_memcpy((uint8_t *)af_req +
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sizeof(struct mbox_msghdr),
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(uint8_t *)msg + sizeof(struct mbox_msghdr),
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size - sizeof(struct mbox_msghdr));
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af_req->pcifunc = msg->pcifunc;
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routed++;
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}
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offset = mbox->rx_start + msg->next_msgoff;
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}
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if (routed > 0) {
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otx2_base_dbg("pf:%d routed %d messages from vf:%d to AF",
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dev->pf, routed, vf);
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af_pf_wait_msg(dev, vf, routed);
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otx2_mbox_reset(dev->mbox, 0);
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}
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/* Send mbox responses to VF */
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if (mdev->num_msgs) {
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otx2_base_dbg("pf:%d reply %d messages to vf:%d",
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dev->pf, mdev->num_msgs, vf);
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otx2_mbox_msg_send(mbox, vf);
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}
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return i;
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}
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static void
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otx2_vf_pf_mbox_handle_msg(void *param)
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{
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uint16_t vf, max_vf, max_bits;
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struct otx2_dev *dev = param;
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max_bits = sizeof(dev->intr.bits[0]) * sizeof(uint64_t);
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max_vf = max_bits * MAX_VFPF_DWORD_BITS;
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for (vf = 0; vf < max_vf; vf++) {
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if (dev->intr.bits[vf/max_bits] & BIT_ULL(vf%max_bits)) {
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otx2_base_dbg("Process vf:%d request (pf:%d, vf:%d)",
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vf, dev->pf, dev->vf);
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vf_pf_process_msgs(dev, vf);
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dev->intr.bits[vf/max_bits] &= ~(BIT_ULL(vf%max_bits));
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}
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}
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dev->timer_set = 0;
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}
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static void
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otx2_vf_pf_mbox_irq(void *param)
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{
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struct otx2_dev *dev = param;
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bool alarm_set = false;
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uint64_t intr;
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int vfpf;
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for (vfpf = 0; vfpf < MAX_VFPF_DWORD_BITS; ++vfpf) {
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intr = otx2_read64(dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
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if (!intr)
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continue;
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otx2_base_dbg("vfpf: %d intr: 0x%" PRIx64 " (pf:%d, vf:%d)",
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vfpf, intr, dev->pf, dev->vf);
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/* Save and clear intr bits */
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dev->intr.bits[vfpf] |= intr;
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otx2_write64(intr, dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
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alarm_set = true;
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}
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if (!dev->timer_set && alarm_set) {
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dev->timer_set = 1;
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/* Start timer to handle messages */
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rte_eal_alarm_set(VF_PF_MBOX_TIMER_MS,
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otx2_vf_pf_mbox_handle_msg, dev);
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}
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}
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static void
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otx2_process_msgs(struct otx2_dev *dev, struct otx2_mbox *mbox)
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{
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@ -118,12 +313,33 @@ static int
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mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
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{
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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int rc;
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int i, rc;
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/* HW clear irq */
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for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
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otx2_write64(~0ull, dev->bar2 +
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RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
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otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
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dev->timer_set = 0;
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/* MBOX interrupt for VF(0...63) <-> PF */
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rc = otx2_register_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
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RVU_PF_INT_VEC_VFPF_MBOX0);
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if (rc) {
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otx2_err("Fail to register PF(VF0-63) mbox irq");
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return rc;
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}
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/* MBOX interrupt for VF(64...128) <-> PF */
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rc = otx2_register_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
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RVU_PF_INT_VEC_VFPF_MBOX1);
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if (rc) {
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otx2_err("Fail to register PF(VF64-128) mbox irq");
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return rc;
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}
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/* MBOX interrupt AF <-> PF */
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rc = otx2_register_irq(intr_handle, otx2_af_pf_mbox_irq,
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dev, RVU_PF_INT_VEC_AFPF_MBOX);
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@ -132,6 +348,11 @@ mbox_register_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
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return rc;
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}
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/* HW enable intr */
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for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
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otx2_write64(~0ull, dev->bar2 +
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RVU_PF_VFPF_MBOX_INT_ENA_W1SX(i));
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otx2_write64(~0ull, dev->bar2 + RVU_PF_INT);
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otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
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@ -142,11 +363,28 @@ static void
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mbox_unregister_irq(struct rte_pci_device *pci_dev, struct otx2_dev *dev)
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{
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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int i;
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/* HW clear irq */
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for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
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otx2_write64(~0ull, dev->bar2 +
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RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
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otx2_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
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dev->timer_set = 0;
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rte_eal_alarm_cancel(otx2_vf_pf_mbox_handle_msg, dev);
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/* Unregister the interrupt handler for each vectors */
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/* MBOX interrupt for VF(0...63) <-> PF */
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otx2_unregister_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
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RVU_PF_INT_VEC_VFPF_MBOX0);
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/* MBOX interrupt for VF(64...128) <-> PF */
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otx2_unregister_irq(intr_handle, otx2_vf_pf_mbox_irq, dev,
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RVU_PF_INT_VEC_VFPF_MBOX1);
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/* MBOX interrupt AF <-> PF */
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otx2_unregister_irq(intr_handle, otx2_af_pf_mbox_irq, dev,
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RVU_PF_INT_VEC_AFPF_MBOX);
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