net/igb: support VF mailbox interrupt for link up/down
When using kernel PF and DPDK VF, when the PF driver finds the link state changes, up -> down or down -> up, the driver will send a message to VF by mailbox. This link state change may be triggered by PHY disconnection/reconnection, user config change like *ifconfig down/up* or interface parameter, like MTU change. This patch enables the support of the mailbox interrupt, so VF driver can receive the message for link up/down. After VF receives this message, VF port need to be reset to recover. This needs to be handled by the application so this patch allows the app to register a reset callback so it can reset the VF port. Signed-off-by: Wenzhuo Lu <wenzhuo.lu@intel.com> Acked-by: Jingjing Wu <jingjing.wu@intel.com>
This commit is contained in:
Wenzhuo Lu
Bruce Richardson
parent
77234603fb
commit
316f4f1adc
@ -47,7 +47,7 @@ New Features
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* Dropped specific Xen Dom0 code.
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* Dropped specific anonymous mempool code in testpmd.
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* **Added mailbox interrupt support for ixgbe VF.**
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* **Added mailbox interrupt support for ixgbe and igb VFs.**
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When the physical NIC link comes down or up, the PF driver will send a
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mailbox message to notify each VF. To handle this link up/down event,
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@ -86,6 +86,12 @@
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#define E1000_INCVALUE_82576 (16 << IGB_82576_TSYNC_SHIFT)
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#define E1000_TSAUXC_DISABLE_SYSTIME 0x80000000
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#define E1000_VTIVAR_MISC 0x01740
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#define E1000_VTIVAR_MISC_MASK 0xFF
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#define E1000_VTIVAR_VALID 0x80
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#define E1000_VTIVAR_MISC_MAILBOX 0
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#define E1000_VTIVAR_MISC_INTR_MASK 0x3
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static int eth_igb_configure(struct rte_eth_dev *dev);
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static int eth_igb_start(struct rte_eth_dev *dev);
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static void eth_igb_stop(struct rte_eth_dev *dev);
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@ -265,6 +271,9 @@ static void eth_igb_assign_msix_vector(struct e1000_hw *hw, int8_t direction,
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static void eth_igb_write_ivar(struct e1000_hw *hw, uint8_t msix_vector,
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uint8_t index, uint8_t offset);
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static void eth_igb_configure_msix_intr(struct rte_eth_dev *dev);
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static void eth_igbvf_interrupt_handler(struct rte_intr_handle *handle,
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void *param);
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static void igbvf_mbx_process(struct rte_eth_dev *dev);
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/*
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* Define VF Stats MACRO for Non "cleared on read" register
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@ -562,6 +571,41 @@ igb_intr_disable(struct e1000_hw *hw)
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E1000_WRITE_FLUSH(hw);
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}
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static inline void
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igbvf_intr_enable(struct rte_eth_dev *dev)
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{
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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/* only for mailbox */
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E1000_WRITE_REG(hw, E1000_EIAM, 1 << E1000_VTIVAR_MISC_MAILBOX);
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E1000_WRITE_REG(hw, E1000_EIAC, 1 << E1000_VTIVAR_MISC_MAILBOX);
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E1000_WRITE_REG(hw, E1000_EIMS, 1 << E1000_VTIVAR_MISC_MAILBOX);
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E1000_WRITE_FLUSH(hw);
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}
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/* only for mailbox now. If RX/TX needed, should extend this function. */
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static void
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igbvf_set_ivar_map(struct e1000_hw *hw, uint8_t msix_vector)
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{
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uint32_t tmp = 0;
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/* mailbox */
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tmp |= (msix_vector & E1000_VTIVAR_MISC_INTR_MASK);
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tmp |= E1000_VTIVAR_VALID;
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E1000_WRITE_REG(hw, E1000_VTIVAR_MISC, tmp);
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}
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static void
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eth_igbvf_configure_msix_intr(struct rte_eth_dev *dev)
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{
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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/* Configure VF other cause ivar */
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igbvf_set_ivar_map(hw, E1000_VTIVAR_MISC_MAILBOX);
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}
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static inline int32_t
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igb_pf_reset_hw(struct e1000_hw *hw)
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{
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@ -950,6 +994,10 @@ eth_igbvf_dev_init(struct rte_eth_dev *eth_dev)
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eth_dev->data->port_id, pci_dev->id.vendor_id,
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pci_dev->id.device_id, "igb_mac_82576_vf");
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rte_intr_callback_register(&pci_dev->intr_handle,
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eth_igbvf_interrupt_handler,
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(void *)eth_dev);
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return 0;
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}
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@ -958,6 +1006,7 @@ eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
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{
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struct e1000_adapter *adapter =
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E1000_DEV_PRIVATE(eth_dev->data->dev_private);
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struct rte_pci_device *pci_dev = eth_dev->pci_dev;
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PMD_INIT_FUNC_TRACE();
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@ -974,6 +1023,12 @@ eth_igbvf_dev_uninit(struct rte_eth_dev *eth_dev)
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rte_free(eth_dev->data->mac_addrs);
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eth_dev->data->mac_addrs = NULL;
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/* disable uio intr before callback unregister */
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rte_intr_disable(&pci_dev->intr_handle);
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rte_intr_callback_unregister(&pci_dev->intr_handle,
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eth_igbvf_interrupt_handler,
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(void *)eth_dev);
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return 0;
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}
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@ -2605,6 +2660,69 @@ eth_igb_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
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eth_igb_interrupt_action(dev);
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}
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static int
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eth_igbvf_interrupt_get_status(struct rte_eth_dev *dev)
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{
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uint32_t eicr;
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct e1000_interrupt *intr =
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E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
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igbvf_intr_disable(hw);
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/* read-on-clear nic registers here */
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eicr = E1000_READ_REG(hw, E1000_EICR);
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intr->flags = 0;
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if (eicr == E1000_VTIVAR_MISC_MAILBOX)
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intr->flags |= E1000_FLAG_MAILBOX;
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return 0;
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}
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void igbvf_mbx_process(struct rte_eth_dev *dev)
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{
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struct e1000_hw *hw =
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E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct e1000_mbx_info *mbx = &hw->mbx;
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u32 in_msg = 0;
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if (mbx->ops.read(hw, &in_msg, 1, 0))
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return;
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/* PF reset VF event */
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if (in_msg == E1000_PF_CONTROL_MSG)
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_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET);
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}
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static int
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eth_igbvf_interrupt_action(struct rte_eth_dev *dev)
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{
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struct e1000_interrupt *intr =
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E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
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if (intr->flags & E1000_FLAG_MAILBOX) {
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igbvf_mbx_process(dev);
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intr->flags &= ~E1000_FLAG_MAILBOX;
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}
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igbvf_intr_enable(dev);
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rte_intr_enable(&dev->pci_dev->intr_handle);
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return 0;
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}
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static void
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eth_igbvf_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
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void *param)
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{
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struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
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eth_igbvf_interrupt_get_status(dev);
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eth_igbvf_interrupt_action(dev);
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}
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static int
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eth_igb_led_on(struct rte_eth_dev *dev)
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{
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@ -2876,6 +2994,8 @@ igbvf_dev_start(struct rte_eth_dev *dev)
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struct e1000_adapter *adapter =
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E1000_DEV_PRIVATE(dev->data->dev_private);
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int ret;
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struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
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uint32_t intr_vector = 0;
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PMD_INIT_FUNC_TRACE();
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@ -2895,12 +3015,41 @@ igbvf_dev_start(struct rte_eth_dev *dev)
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return ret;
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}
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/* check and configure queue intr-vector mapping */
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if (dev->data->dev_conf.intr_conf.rxq != 0) {
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intr_vector = dev->data->nb_rx_queues;
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ret = rte_intr_efd_enable(intr_handle, intr_vector);
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if (ret)
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return ret;
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}
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if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
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intr_handle->intr_vec =
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rte_zmalloc("intr_vec",
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dev->data->nb_rx_queues * sizeof(int), 0);
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if (!intr_handle->intr_vec) {
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PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
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" intr_vec\n", dev->data->nb_rx_queues);
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return -ENOMEM;
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}
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}
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eth_igbvf_configure_msix_intr(dev);
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/* enable uio/vfio intr/eventfd mapping */
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rte_intr_enable(intr_handle);
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/* resume enabled intr since hw reset */
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igbvf_intr_enable(dev);
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return 0;
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}
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static void
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igbvf_dev_stop(struct rte_eth_dev *dev)
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{
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struct rte_intr_handle *intr_handle = &dev->pci_dev->intr_handle;
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PMD_INIT_FUNC_TRACE();
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igbvf_stop_adapter(dev);
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@ -2912,6 +3061,16 @@ igbvf_dev_stop(struct rte_eth_dev *dev)
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igbvf_set_vfta_all(dev,0);
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igb_dev_clear_queues(dev);
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/* disable intr eventfd mapping */
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rte_intr_disable(intr_handle);
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/* Clean datapath event and queue/vec mapping */
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rte_intr_efd_disable(intr_handle);
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if (intr_handle->intr_vec) {
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rte_free(intr_handle->intr_vec);
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intr_handle->intr_vec = NULL;
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}
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}
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static void
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