net/mlx5: fix input register for ASO object
Existing code uses the hard-coded value REG_C_5 as input for function
mlx5dv_dr_action_create_flow_hit().
This patch updates function mlx5_flow_get_reg_id() to return the
selected REG_C value for ASO Flow Hit operation.
The returned value is used, after reducing offset REG_C_0, as input
for function mlx5dv_dr_action_create_flow_hit().
Fixes: f935ed4b64 ("net/mlx5: support flow hit action for aging")
Signed-off-by: Dekel Peled <dekelp@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit is contained in:
Dekel Peled
Ferruh Yigit
parent
7ad0b6d91f
commit
31ef2982fa
@ -1133,17 +1133,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
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err = -err;
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goto error;
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}
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#ifdef HAVE_MLX5DV_DR_ACTION_FLOW_HIT
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if (config->hca_attr.flow_hit_aso) {
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sh->flow_hit_aso_en = 1;
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err = mlx5_flow_aso_age_mng_init(sh);
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if (err) {
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err = -err;
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goto error;
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}
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DRV_LOG(DEBUG, "Flow Hit ASO is supported.");
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}
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#endif /* HAVE_MLX5DV_DR_ACTION_FLOW_HIT */
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/* Check relax ordering support. */
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if (!haswell_broadwell_cpu) {
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sh->cmng.relaxed_ordering_write =
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@ -1190,8 +1179,17 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
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DRV_LOG(WARNING, "No available register for"
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" meter.");
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} else {
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priv->mtr_color_reg = ffs(reg_c_mask) - 1 +
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REG_C_0;
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/*
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* The meter color register is used by the
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* flow-hit feature as well.
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* The flow-hit feature must use REG_C_3
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* Prefer REG_C_3 if it is available.
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*/
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if (reg_c_mask & (1 << (REG_C_3 - REG_C_0)))
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priv->mtr_color_reg = REG_C_3;
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else
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priv->mtr_color_reg = ffs(reg_c_mask)
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- 1 + REG_C_0;
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priv->mtr_en = 1;
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priv->mtr_reg_share =
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config->hca_attr.qos.flow_meter_reg_share;
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@ -1200,6 +1198,18 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,
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}
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}
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#endif
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#ifdef HAVE_MLX5DV_DR_ACTION_FLOW_HIT
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if (config->hca_attr.flow_hit_aso &&
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priv->mtr_color_reg == REG_C_3) {
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sh->flow_hit_aso_en = 1;
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err = mlx5_flow_aso_age_mng_init(sh);
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if (err) {
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err = -err;
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goto error;
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}
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DRV_LOG(DEBUG, "Flow Hit ASO is supported.");
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}
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#endif /* HAVE_MLX5DV_DR_ACTION_FLOW_HIT */
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#if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_SAMPLE)
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if (config->hca_attr.log_max_ft_sampler_num > 0 &&
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config->dv_flow_en) {
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@ -777,6 +777,7 @@ mlx5_flow_get_reg_id(struct rte_eth_dev *dev,
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return priv->mtr_color_reg != REG_C_2 ? REG_C_2 :
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REG_C_3;
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case MLX5_MTR_COLOR:
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case MLX5_ASO_FLOW_HIT: /* Both features use the same REG_C. */
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MLX5_ASSERT(priv->mtr_color_reg != REG_NON);
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return priv->mtr_color_reg;
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case MLX5_COPY_MARK:
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@ -80,6 +80,7 @@ enum mlx5_feature_name {
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MLX5_COPY_MARK,
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MLX5_MTR_COLOR,
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MLX5_MTR_SFX,
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MLX5_ASO_FLOW_HIT,
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};
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/* Default queue number. */
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@ -9469,12 +9469,14 @@ flow_dv_age_pool_create(struct rte_eth_dev *dev,
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*
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* @param[in] dev
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* Pointer to the Ethernet device structure.
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* @param[out] error
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* Pointer to the error structure.
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*
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* @return
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* Index to ASO age action on success, 0 otherwise and rte_errno is set.
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*/
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static uint32_t
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flow_dv_aso_age_alloc(struct rte_eth_dev *dev)
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flow_dv_aso_age_alloc(struct rte_eth_dev *dev, struct rte_flow_error *error)
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{
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struct mlx5_priv *priv = dev->data->dev_private;
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const struct mlx5_aso_age_pool *pool;
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@ -9489,7 +9491,9 @@ flow_dv_aso_age_alloc(struct rte_eth_dev *dev)
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LIST_REMOVE(age_free, next);
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} else if (!flow_dv_age_pool_create(dev, &age_free)) {
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rte_spinlock_unlock(&mng->free_sl);
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return 0; /* 0 is an error.*/
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rte_flow_error_set(error, rte_errno, RTE_FLOW_ERROR_TYPE_ACTION,
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NULL, "failed to create ASO age pool");
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return 0; /* 0 is an error. */
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}
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rte_spinlock_unlock(&mng->free_sl);
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pool = container_of
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@ -9497,15 +9501,30 @@ flow_dv_aso_age_alloc(struct rte_eth_dev *dev)
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(age_free - age_free->offset), const struct mlx5_aso_age_pool,
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actions);
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if (!age_free->dr_action) {
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int reg_c = mlx5_flow_get_reg_id(dev, MLX5_ASO_FLOW_HIT, 0,
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error);
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if (reg_c < 0) {
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rte_flow_error_set(error, rte_errno,
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RTE_FLOW_ERROR_TYPE_ACTION,
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NULL, "failed to get reg_c "
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"for ASO flow hit");
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return 0; /* 0 is an error. */
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}
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age_free->dr_action = mlx5_glue->dr_action_create_flow_hit
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(pool->flow_hit_aso_obj->obj,
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age_free->offset, REG_C_5);
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age_free->offset,
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(reg_c - REG_C_0));
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if (!age_free->dr_action) {
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rte_errno = errno;
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rte_spinlock_lock(&mng->free_sl);
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LIST_INSERT_HEAD(&mng->free, age_free, next);
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rte_spinlock_unlock(&mng->free_sl);
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return 0; /* 0 is an error.*/
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rte_flow_error_set(error, rte_errno,
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RTE_FLOW_ERROR_TYPE_ACTION,
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NULL, "failed to create ASO "
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"flow hit action");
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return 0; /* 0 is an error. */
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}
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}
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__atomic_store_n(&age_free->refcnt, 1, __ATOMIC_RELAXED);
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@ -9519,18 +9538,21 @@ flow_dv_aso_age_alloc(struct rte_eth_dev *dev)
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* Pointer to rte_eth_dev structure.
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* @param[in] age
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* Pointer to the aging action configuration.
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* @param[out] error
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* Pointer to the error structure.
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*
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* @return
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* Index to flow counter on success, 0 otherwise.
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*/
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static uint32_t
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flow_dv_translate_create_aso_age(struct rte_eth_dev *dev,
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const struct rte_flow_action_age *age)
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const struct rte_flow_action_age *age,
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struct rte_flow_error *error)
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{
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uint32_t age_idx = 0;
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struct mlx5_aso_age_action *aso_age;
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age_idx = flow_dv_aso_age_alloc(dev);
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age_idx = flow_dv_aso_age_alloc(dev, error);
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if (!age_idx)
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return 0;
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aso_age = flow_aso_age_get_by_idx(dev, age_idx);
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@ -9842,7 +9864,7 @@ flow_dv_translate(struct rte_eth_dev *dev,
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case RTE_FLOW_ACTION_TYPE_AGE:
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if (priv->sh->flow_hit_aso_en && attr->group) {
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flow->age = flow_dv_translate_create_aso_age
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(dev, action->conf);
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(dev, action->conf, error);
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if (!flow->age)
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return rte_flow_error_set
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(error, rte_errno,
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@ -11532,7 +11554,7 @@ flow_dv_action_create(struct rte_eth_dev *dev,
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MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
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break;
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case RTE_FLOW_ACTION_TYPE_AGE:
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ret = flow_dv_translate_create_aso_age(dev, action->conf);
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ret = flow_dv_translate_create_aso_age(dev, action->conf, err);
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idx = (MLX5_SHARED_ACTION_TYPE_AGE <<
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MLX5_SHARED_ACTION_TYPE_OFFSET) | ret;
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if (ret) {
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