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ixgbe/base: minor changes

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Signed-off-by: Jijiang Liu <jijiang.liu@intel.com>
Acked-by: Helin Zhang <helin.zhang@intel.com>
Tested-by: Waterman Cao <waterman.cao@intel.com>
[Thomas: split code drop]
This commit is contained in:
Jijiang Liu 2014-06-18 14:59:54 +02:00 committed by Thomas Monjalon
parent 281543f05d
commit 3211b57388
11 changed files with 144 additions and 112 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/librte_pmd_ixgbe/ixgbe/ixgbe_82598.c
View File

@ -58,7 +58,7 @@ STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
u32 headroom, int strategy);
/**
@ -964,6 +964,7 @@ STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
u32 rar_high;
u32 rar_entries = hw->mac.num_rar_entries;
UNREFERENCED_1PARAMETER(vmdq);
/* Make sure we are using a valid rar index range */
if (rar >= rar_entries) {
@ -1337,11 +1338,12 @@ void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
* @headroom: reserve n KB of headroom
* @strategy: packet buffer allocation strategy
**/
static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
u32 headroom, int strategy)
{
u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
u8 i = 0;
UNREFERENCED_1PARAMETER(headroom);
if (!num_pb)
return;

17
lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c
View File

@ -1076,7 +1076,7 @@ mac_reset_top:
IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
IXGBE_WRITE_FLUSH(hw);
/* Poll for reset bit to self-clear indicating reset is complete */
/* Poll for reset bit to self-clear meaning reset is complete */
for (i = 0; i < 10; i++) {
usec_delay(1);
ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
@ -1093,8 +1093,8 @@ mac_reset_top:
/*
* Double resets are required for recovery from certain error
* conditions. Between resets, it is necessary to stall to allow time
* for any pending HW events to complete.
* conditions. Between resets, it is necessary to stall to
* allow time for any pending HW events to complete.
*/
if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
@ -1359,6 +1359,7 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
(0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
(4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
/* write hashes and fdirctrl register, poll for completion */
ixgbe_fdir_enable_82599(hw, fdirctrl);
@ -1475,6 +1476,7 @@ s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
/*
* Get the flow_type in order to program FDIRCMD properly
* lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
* fifth is FDIRCMD.TUNNEL_FILTER
*/
switch (input.formatted.flow_type) {
case IXGBE_ATR_FLOW_TYPE_TCPV4:
@ -1646,7 +1648,6 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
/* mask IPv6 since it is currently not supported */
u32 fdirm = IXGBE_FDIRM_DIPv6;
u32 fdirtcpm;
DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
/*
@ -1719,6 +1720,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
return IXGBE_ERR_CONFIG;
}
/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
@ -1772,6 +1774,7 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
/* configure FDIRHASH register */
fdirhash = input->formatted.bkt_hash;
fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
@ -1987,7 +1990,7 @@ out:
**/
s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
{
s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
s32 status;
DEBUGFUNC("ixgbe_identify_phy_82599");
@ -2175,11 +2178,11 @@ s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
* Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
* if the FW version is not supported.
**/
s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
{
s32 status = IXGBE_ERR_EEPROM_VERSION;
u16 fw_offset, fw_ptp_cfg_offset;
u16 fw_version = 0;
u16 fw_version;
DEBUGFUNC("ixgbe_verify_fw_version_82599");

8
lib/librte_pmd_ixgbe/ixgbe/ixgbe_api.c
View File

@ -65,13 +65,13 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)
case ixgbe_mac_82599EB:
status = ixgbe_init_ops_82599(hw);
break;
case ixgbe_mac_X540:
status = ixgbe_init_ops_X540(hw);
break;
case ixgbe_mac_82599_vf:
case ixgbe_mac_X540_vf:
status = ixgbe_init_ops_vf(hw);
break;
case ixgbe_mac_X540:
status = ixgbe_init_ops_X540(hw);
break;
default:
status = IXGBE_ERR_DEVICE_NOT_SUPPORTED;
break;
@ -998,6 +998,8 @@ s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,
}
/**
* ixgbe_read_analog_reg8 - Reads 8 bit analog register
* @hw: pointer to hardware structure

90
lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.c
View File

@ -34,28 +34,28 @@ POSSIBILITY OF SUCH DAMAGE.
#include "ixgbe_common.h"
#include "ixgbe_phy.h"
#include "ixgbe_api.h"
#ident "$Id: ixgbe_common.c,v 1.349 2012/11/05 23:08:30 jtkirshe Exp $"
#ident "$Id: ixgbe_common.c,v 1.382 2013/11/22 01:02:01 jtkirshe Exp $"
static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
u16 count);
static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
u16 *san_mac_offset);
static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data);
static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data);
static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
u16 offset);
/**
@ -139,13 +139,13 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
}
/**
* ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
* control
* @hw: pointer to hardware structure
* ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
* of flow control
* @hw: pointer to hardware structure
*
* This function returns true if the device supports flow control
* autonegotiation, and false if it does not.
*
* There are several phys that do not support autoneg flow control. This
* function check the device id to see if the associated phy supports
* autoneg flow control.
**/
s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
{
@ -168,7 +168,7 @@ s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
*
* Called at init time to set up flow control.
**/
static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
{
s32 ret_val = IXGBE_SUCCESS;
u32 reg = 0, reg_bp = 0;
@ -1211,7 +1211,7 @@ out:
* If ixgbe_eeprom_update_checksum is not called after this function, the
* EEPROM will most likely contain an invalid checksum.
**/
static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data)
{
s32 status;
@ -1370,7 +1370,7 @@ out:
*
* Reads 16 bit word(s) from EEPROM through bit-bang method
**/
static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
u16 words, u16 *data)
{
s32 status;
@ -1505,7 +1505,7 @@ out:
* This function is called only when we are writing a new large buffer
* at given offset so the data would be overwritten anyway.
**/
static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
u16 offset)
{
u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
@ -1658,7 +1658,7 @@ s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
* Prepares EEPROM for access using bit-bang method. This function should
* be called before issuing a command to the EEPROM.
**/
static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
u32 eec;
@ -1712,7 +1712,7 @@ static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
*
* Sets the hardware semaphores so EEPROM access can occur for bit-bang method
**/
static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
{
s32 status = IXGBE_ERR_EEPROM;
u32 timeout = 2000;
@ -1802,7 +1802,7 @@ static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
*
* This function clears hardware semaphore bits.
**/
static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
{
u32 swsm;
@ -1820,7 +1820,7 @@ static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
* ixgbe_ready_eeprom - Polls for EEPROM ready
* @hw: pointer to hardware structure
**/
static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
u16 i;
@ -1861,7 +1861,7 @@ static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
* ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
* @hw: pointer to hardware structure
**/
static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
{
u32 eec;
@ -1886,7 +1886,7 @@ static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
* @data: data to send to the EEPROM
* @count: number of bits to shift out
**/
static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
u16 count)
{
u32 eec;
@ -1941,7 +1941,7 @@ static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
* ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
* @hw: pointer to hardware structure
**/
static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
{
u32 eec;
u32 i;
@ -1981,7 +1981,7 @@ static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
* @hw: pointer to hardware structure
* @eec: EEC register's current value
**/
static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
{
DEBUGFUNC("ixgbe_raise_eeprom_clk");
@ -2000,7 +2000,7 @@ static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
* @hw: pointer to hardware structure
* @eecd: EECD's current value
**/
static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
{
DEBUGFUNC("ixgbe_lower_eeprom_clk");
@ -2018,7 +2018,7 @@ static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
* ixgbe_release_eeprom - Release EEPROM, release semaphores
* @hw: pointer to hardware structure
**/
static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
{
u32 eec;
@ -2467,7 +2467,7 @@ s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
* by the MO field of the MCSTCTRL. The MO field is set during initialization
* to mc_filter_type.
**/
static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
{
u32 vector = 0;
@ -2764,7 +2764,7 @@ out:
* Find the intersection between advertised settings and link partner's
* advertised settings
**/
static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
{
if ((!(adv_reg)) || (!(lp_reg)))
@ -2806,7 +2806,7 @@ static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
*
* Enable flow control according on 1 gig fiber.
**/
static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
{
u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
@ -2841,7 +2841,7 @@ out:
*
* Enable flow control according to IEEE clause 37.
**/
static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
{
u32 links2, anlp1_reg, autoc_reg, links;
s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
@ -2881,7 +2881,7 @@ out:
*
* Enable flow control according to IEEE clause 37.
**/
static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
{
u16 technology_ability_reg = 0;
u16 lp_technology_ability_reg = 0;
@ -3278,7 +3278,7 @@ out:
* pointer, and returns the value at that location. This is used in both
* get and set mac_addr routines.
**/
static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
u16 *san_mac_offset)
{
DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
@ -4135,7 +4135,7 @@ void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
* Calculates the checksum for some buffer on a specified length. The
* checksum calculated is returned.
**/
static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
{
u32 i;
u8 sum = 0;
@ -4161,8 +4161,8 @@ static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
* Communicates with the manageability block. On success return IXGBE_SUCCESS
* else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
**/
static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
u32 length)
s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
u32 length)
{
u32 hicr, i, bi;
u32 hdr_size = sizeof(struct ixgbe_hic_hdr);

3
lib/librte_pmd_ixgbe/ixgbe/ixgbe_common.h
View File

@ -148,6 +148,9 @@ void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw);
s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
u8 build, u8 ver);
u8 ixgbe_calculate_checksum(u8 *buffer, u32 length);
s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
u32 length);
void ixgbe_clear_tx_pending(struct ixgbe_hw *hw);
extern s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw);

5
lib/librte_pmd_ixgbe/ixgbe/ixgbe_mbx.c
View File

@ -325,6 +325,7 @@ STATIC s32 ixgbe_check_for_msg_vf(struct ixgbe_hw *hw, u16 mbx_id)
{
s32 ret_val = IXGBE_ERR_MBX;
UNREFERENCED_1PARAMETER(mbx_id);
DEBUGFUNC("ixgbe_check_for_msg_vf");
if (!ixgbe_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFSTS)) {
@ -346,6 +347,7 @@ STATIC s32 ixgbe_check_for_ack_vf(struct ixgbe_hw *hw, u16 mbx_id)
{
s32 ret_val = IXGBE_ERR_MBX;
UNREFERENCED_1PARAMETER(mbx_id);
DEBUGFUNC("ixgbe_check_for_ack_vf");
if (!ixgbe_check_for_bit_vf(hw, IXGBE_VFMAILBOX_PFACK)) {
@ -367,6 +369,7 @@ STATIC s32 ixgbe_check_for_rst_vf(struct ixgbe_hw *hw, u16 mbx_id)
{
s32 ret_val = IXGBE_ERR_MBX;
UNREFERENCED_1PARAMETER(mbx_id);
DEBUGFUNC("ixgbe_check_for_rst_vf");
if (!ixgbe_check_for_bit_vf(hw, (IXGBE_VFMAILBOX_RSTD |
@ -415,6 +418,7 @@ STATIC s32 ixgbe_write_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,
s32 ret_val;
u16 i;
UNREFERENCED_1PARAMETER(mbx_id);
DEBUGFUNC("ixgbe_write_mbx_vf");
@ -468,6 +472,7 @@ STATIC s32 ixgbe_read_mbx_vf(struct ixgbe_hw *hw, u32 *msg, u16 size,
u16 i;
DEBUGFUNC("ixgbe_read_mbx_vf");
UNREFERENCED_1PARAMETER(mbx_id);
/* lock the mailbox to prevent pf/vf race condition */
ret_val = ixgbe_obtain_mbx_lock_vf(hw);

62
lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c
View File

@ -36,17 +36,17 @@ POSSIBILITY OF SUCH DAMAGE.
#include "ixgbe_phy.h"
#ident "$Id: ixgbe_phy.c,v 1.139 2012/05/24 23:36:12 jtkirshe Exp $"
static void ixgbe_i2c_start(struct ixgbe_hw *hw);
static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
static bool ixgbe_get_i2c_data(u32 *i2cctl);
STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
/**
* ixgbe_init_phy_ops_generic - Inits PHY function ptrs
@ -121,9 +121,14 @@ s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
break;
}
}
/* clear value if nothing found */
if (status != IXGBE_SUCCESS)
/* Certain media types do not have a phy so an address will not
* be found and the code will take this path. Caller has to
* decide if it is an error or not.
*/
if (status != IXGBE_SUCCESS) {
hw->phy.addr = 0;
}
} else {
status = IXGBE_SUCCESS;
}
@ -570,6 +575,7 @@ s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
bool autoneg,
bool autoneg_wait_to_complete)
{
UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
@ -606,7 +612,7 @@ s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
ixgbe_link_speed *speed,
bool *autoneg)
{
s32 status = IXGBE_ERR_LINK_SETUP;
s32 status;
u16 speed_ability;
DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
@ -781,7 +787,7 @@ s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
u16 *firmware_version)
{
s32 status = IXGBE_SUCCESS;
s32 status;
DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
@ -800,7 +806,7 @@ s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
u16 *firmware_version)
{
s32 status = IXGBE_SUCCESS;
s32 status;
DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
@ -1521,7 +1527,7 @@ write_byte_out:
*
* Sets I2C start condition (High -> Low on SDA while SCL is High)
**/
static void ixgbe_i2c_start(struct ixgbe_hw *hw)
STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
{
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
@ -1552,7 +1558,7 @@ static void ixgbe_i2c_start(struct ixgbe_hw *hw)
*
* Sets I2C stop condition (Low -> High on SDA while SCL is High)
**/
static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
{
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
@ -1578,7 +1584,7 @@ static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
*
* Clocks in one byte data via I2C data/clock
**/
static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
{
s32 i;
bool bit = 0;
@ -1600,12 +1606,12 @@ static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
*
* Clocks out one byte data via I2C data/clock
**/
static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
{
s32 status = IXGBE_SUCCESS;
s32 i;
u32 i2cctl;
bool bit = 0;
bool bit;
DEBUGFUNC("ixgbe_clock_out_i2c_byte");
@ -1632,7 +1638,7 @@ static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
*
* Clocks in/out one bit via I2C data/clock
**/
static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
{
s32 status = IXGBE_SUCCESS;
u32 i = 0;
@ -1679,7 +1685,7 @@ static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
*
* Clocks in one bit via I2C data/clock
**/
static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
{
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
@ -1708,7 +1714,7 @@ static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
*
* Clocks out one bit via I2C data/clock
**/
static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
{
s32 status;
u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
@ -1742,7 +1748,7 @@ static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
*
* Raises the I2C clock line '0'->'1'
**/
static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
u32 i = 0;
u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
@ -1771,7 +1777,7 @@ static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
*
* Lowers the I2C clock line '1'->'0'
**/
static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
{
DEBUGFUNC("ixgbe_lower_i2c_clk");
@ -1793,7 +1799,7 @@ static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
*
* Sets the I2C data bit
**/
static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
{
s32 status = IXGBE_SUCCESS;
@ -1827,7 +1833,7 @@ static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
*
* Returns the I2C data bit value
**/
static bool ixgbe_get_i2c_data(u32 *i2cctl)
STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
{
bool data;

48
lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h
View File

@ -282,6 +282,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */
#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */
/* Flow Director registers */
#define IXGBE_FDIRCTRL 0x0EE00
#define IXGBE_FDIRHKEY 0x0EE68
@ -362,6 +363,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define IXGBE_WUPL 0x05900
#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
#define IXGBE_FHFT(_n) (0x09000 + (_n * 0x100)) /* Flex host filter table */
/* Ext Flexible Host Filter Table */
#define IXGBE_FHFT_EXT(_n) (0x09800 + (_n * 0x100))
@ -422,7 +424,6 @@ POSSIBILITY OF SUCH DAMAGE.
#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5
#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS
/* Wake Up Packet Length */
#define IXGBE_WUPL_LENGTH_MASK 0xFFFF
/* DCB registers */
@ -439,6 +440,7 @@ POSSIBILITY OF SUCH DAMAGE.
#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
/* Security Control Registers */
#define IXGBE_SECTXCTRL 0x08800
#define IXGBE_SECTXSTAT 0x08804
@ -1779,28 +1781,28 @@ enum {
#define IXGBE_PBANUM_LENGTH 11
/* Checksum and EEPROM pointers */
#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
#define IXGBE_EEPROM_CHECKSUM 0x3F
#define IXGBE_EEPROM_SUM 0xBABA
#define IXGBE_PCIE_ANALOG_PTR 0x03
#define IXGBE_ATLAS0_CONFIG_PTR 0x04
#define IXGBE_PHY_PTR 0x04
#define IXGBE_ATLAS1_CONFIG_PTR 0x05
#define IXGBE_OPTION_ROM_PTR 0x05
#define IXGBE_PCIE_GENERAL_PTR 0x06
#define IXGBE_PCIE_CONFIG0_PTR 0x07
#define IXGBE_PCIE_CONFIG1_PTR 0x08
#define IXGBE_CORE0_PTR 0x09
#define IXGBE_CORE1_PTR 0x0A
#define IXGBE_MAC0_PTR 0x0B
#define IXGBE_MAC1_PTR 0x0C
#define IXGBE_CSR0_CONFIG_PTR 0x0D
#define IXGBE_CSR1_CONFIG_PTR 0x0E
#define IXGBE_FW_PTR 0x0F
#define IXGBE_PBANUM0_PTR 0x15
#define IXGBE_PBANUM1_PTR 0x16
#define IXGBE_ALT_MAC_ADDR_PTR 0x37
#define IXGBE_FREE_SPACE_PTR 0X3E
#define IXGBE_PBANUM_PTR_GUARD 0xFAFA
#define IXGBE_EEPROM_CHECKSUM 0x3F
#define IXGBE_EEPROM_SUM 0xBABA
#define IXGBE_PCIE_ANALOG_PTR 0x03
#define IXGBE_ATLAS0_CONFIG_PTR 0x04
#define IXGBE_PHY_PTR 0x04
#define IXGBE_ATLAS1_CONFIG_PTR 0x05
#define IXGBE_OPTION_ROM_PTR 0x05
#define IXGBE_PCIE_GENERAL_PTR 0x06
#define IXGBE_PCIE_CONFIG0_PTR 0x07
#define IXGBE_PCIE_CONFIG1_PTR 0x08
#define IXGBE_CORE0_PTR 0x09
#define IXGBE_CORE1_PTR 0x0A
#define IXGBE_MAC0_PTR 0x0B
#define IXGBE_MAC1_PTR 0x0C
#define IXGBE_CSR0_CONFIG_PTR 0x0D
#define IXGBE_CSR1_CONFIG_PTR 0x0E
#define IXGBE_FW_PTR 0x0F
#define IXGBE_PBANUM0_PTR 0x15
#define IXGBE_PBANUM1_PTR 0x16
#define IXGBE_ALT_MAC_ADDR_PTR 0x37
#define IXGBE_FREE_SPACE_PTR 0X3E
#define IXGBE_SAN_MAC_ADDR_PTR 0x28
#define IXGBE_DEVICE_CAPS 0x2C

11
lib/librte_pmd_ixgbe/ixgbe/ixgbe_vf.c
View File

@ -247,7 +247,7 @@ s32 ixgbe_stop_adapter_vf(struct ixgbe_hw *hw)
* by the MO field of the MCSTCTRL. The MO field is set during initialization
* to mc_filter_type.
**/
static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
{
u32 vector = 0;
@ -275,7 +275,7 @@ static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
return vector;
}
static void ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw,
STATIC void ixgbevf_write_msg_read_ack(struct ixgbe_hw *hw,
u32 *msg, u16 size)
{
struct ixgbe_mbx_info *mbx = &hw->mbx;
@ -301,6 +301,7 @@ s32 ixgbe_set_rar_vf(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
u32 msgbuf[3];
u8 *msg_addr = (u8 *)(&msgbuf[1]);
s32 ret_val;
UNREFERENCED_3PARAMETER(vmdq, enable_addr, index);
memset(msgbuf, 0, 12);
msgbuf[0] = IXGBE_VF_SET_MAC_ADDR;
@ -340,6 +341,7 @@ s32 ixgbe_update_mc_addr_list_vf(struct ixgbe_hw *hw, u8 *mc_addr_list,
u32 cnt, i;
u32 vmdq;
UNREFERENCED_1PARAMETER(clear);
DEBUGFUNC("ixgbe_update_mc_addr_list_vf");
@ -379,6 +381,7 @@ s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
struct ixgbe_mbx_info *mbx = &hw->mbx;
u32 msgbuf[2];
s32 ret_val;
UNREFERENCED_1PARAMETER(vind);
msgbuf[0] = IXGBE_VF_SET_VLAN;
msgbuf[1] = vlan;
@ -403,6 +406,7 @@ s32 ixgbe_set_vfta_vf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on)
**/
u32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw)
{
UNREFERENCED_1PARAMETER(hw);
return IXGBE_VF_MAX_TX_QUEUES;
}
@ -414,6 +418,7 @@ u32 ixgbe_get_num_of_tx_queues_vf(struct ixgbe_hw *hw)
**/
u32 ixgbe_get_num_of_rx_queues_vf(struct ixgbe_hw *hw)
{
UNREFERENCED_1PARAMETER(hw);
return IXGBE_VF_MAX_RX_QUEUES;
}
@ -476,6 +481,7 @@ s32 ixgbe_setup_mac_link_vf(struct ixgbe_hw *hw,
ixgbe_link_speed speed, bool autoneg,
bool autoneg_wait_to_complete)
{
UNREFERENCED_3PARAMETER(hw, speed, autoneg_wait_to_complete);
return IXGBE_SUCCESS;
}
@ -492,6 +498,7 @@ s32 ixgbe_check_mac_link_vf(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
bool *link_up, bool autoneg_wait_to_complete)
{
u32 links_reg;
UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
if (!(hw->mbx.ops.check_for_rst(hw, 0))) {
*link_up = false;

5
lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.c
View File

@ -169,6 +169,7 @@ s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw,
**/
enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
{
UNREFERENCED_1PARAMETER(hw);
return ixgbe_media_type_copper;
}
@ -650,7 +651,7 @@ s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
STATIC s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
{
u32 flup;
s32 status = IXGBE_ERR_EEPROM;
s32 status;
DEBUGFUNC("ixgbe_update_flash_X540");
@ -775,7 +776,7 @@ s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask)
}
/* If the resource is not released by the FW/HW the SW can assume that
* the FW/HW malfunctions. In that case the SW should sets the SW bit(s)
* the FW/HW malfunctions. In that case the SW should set the SW bit(s)
* of the requested resource(s) while ignoring the corresponding FW/HW
* bits in the SW_FW_SYNC register.
*/

1
lib/librte_pmd_ixgbe/ixgbe/ixgbe_x540.h
View File

@ -63,3 +63,4 @@ void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u16 mask);
s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index);
s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index);
#endif /* _IXGBE_X540_H_ */