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net/bnx2x: update HSI

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Update hardware software common base driver code in preparation to
update the firmware to version 7.13.11.

Signed-off-by: Rasesh Mody <rmody@marvell.com>
This commit is contained in:
Rasesh Mody 2019-10-02 12:14:55 -07:00 committed by Ferruh Yigit
parent da62a28156
commit 38dff79ba7
6 changed files with 1993 additions and 1606 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
drivers/net/bnx2x/bnx2x.c
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@ -2182,8 +2182,10 @@ int bnx2x_tx_encap(struct bnx2x_tx_queue *txq, struct rte_mbuf *m0)
tx_start_bd = &txq->tx_ring[TX_BD(bd_prod, txq)].start_bd;
tx_start_bd->addr =
rte_cpu_to_le_64(rte_mbuf_data_iova(m0));
tx_start_bd->addr_lo =
rte_cpu_to_le_32(U64_LO(rte_mbuf_data_iova(m0)));
tx_start_bd->addr_hi =
rte_cpu_to_le_32(U64_HI(rte_mbuf_data_iova(m0)));
tx_start_bd->nbytes = rte_cpu_to_le_16(m0->data_len);
tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
tx_start_bd->general_data =
@ -5015,13 +5017,14 @@ static void
bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod)
{
union ustorm_eth_rx_producers rx_prods;
struct ustorm_eth_rx_producers rx_prods;
uint32_t i;
memset(&rx_prods, 0, sizeof(rx_prods));
/* update producers */
rx_prods.prod.bd_prod = rx_bd_prod;
rx_prods.prod.cqe_prod = rx_cq_prod;
rx_prods.prod.reserved = 0;
rx_prods.bd_prod = rx_bd_prod;
rx_prods.cqe_prod = rx_cq_prod;
/*
* Make sure that the BD and SGE data is updated before updating the
@ -5034,9 +5037,8 @@ bnx2x_update_rx_prod(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
wmb();
for (i = 0; i < (sizeof(rx_prods) / 4); i++) {
REG_WR(sc,
(fp->ustorm_rx_prods_offset + (i * 4)),
rx_prods.raw_data[i]);
REG_WR(sc, (fp->ustorm_rx_prods_offset + (i * 4)),
((uint32_t *)&rx_prods)[i]);
}
wmb(); /* keep prod updates ordered */

23
drivers/net/bnx2x/bnx2x.h
View File

@ -19,18 +19,7 @@
#include <rte_bus_pci.h>
#include <rte_io.h>
#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
#ifndef __LITTLE_ENDIAN
#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
#endif
#undef __BIG_ENDIAN
#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
#ifndef __BIG_ENDIAN
#define __BIG_ENDIAN RTE_BIG_ENDIAN
#endif
#undef __LITTLE_ENDIAN
#endif
#include "bnx2x_osal.h"
#include "bnx2x_ethdev.h"
#include "ecore_mfw_req.h"
#include "ecore_fw_defs.h"
@ -1911,16 +1900,18 @@ bnx2x_hc_ack_sb(struct bnx2x_softc *sc, uint8_t sb_id, uint8_t storm,
{
uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc) * 32 +
COMMAND_REG_INT_ACK);
union igu_ack_register igu_ack;
struct igu_ack_register igu_ack;
uint32_t *val = NULL;
igu_ack.sb.status_block_index = index;
igu_ack.sb.sb_id_and_flags =
igu_ack.status_block_index = index;
igu_ack.sb_id_and_flags =
((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
(storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
(update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
(op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
REG_WR(sc, hc_addr, igu_ack.raw_data);
val = (uint32_t *)&igu_ack;
REG_WR(sc, hc_addr, *val);
/* Make sure that ACK is written */
mb();

29
drivers/net/bnx2x/bnx2x_osal.h Normal file
View File

@ -0,0 +1,29 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright (c) 2019 Cavium Inc.
*
* All rights reserved.
* www.cavium.com
*/
#ifndef BNX2X_OSAL_H
#define BNX2X_OSAL_H
#include <sys/stat.h>
#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
#ifndef __LITTLE_ENDIAN
#define __LITTLE_ENDIAN RTE_LITTLE_ENDIAN
#endif
#undef __BIG_ENDIAN
#elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
#ifndef __BIG_ENDIAN
#define __BIG_ENDIAN RTE_BIG_ENDIAN
#endif
#undef __LITTLE_ENDIAN
#endif
#define __le16 uint16_t
#define __le32 uint32_t
#define __le64 uint64_t
#endif /* BNX2X_OSAL_H */

10
drivers/net/bnx2x/bnx2x_rxtx.c
View File

@ -321,12 +321,14 @@ static inline void
bnx2x_upd_rx_prod_fast(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,
uint16_t rx_bd_prod, uint16_t rx_cq_prod)
{
union ustorm_eth_rx_producers rx_prods;
struct ustorm_eth_rx_producers rx_prods = { 0 };
uint32_t *val = NULL;
rx_prods.prod.bd_prod = rx_bd_prod;
rx_prods.prod.cqe_prod = rx_cq_prod;
rx_prods.bd_prod = rx_bd_prod;
rx_prods.cqe_prod = rx_cq_prod;
REG_WR(sc, fp->ustorm_rx_prods_offset, rx_prods.raw_data[0]);
val = (uint32_t *)&rx_prods;
REG_WR(sc, fp->ustorm_rx_prods_offset, val[0]);
}
static uint16_t

3506
drivers/net/bnx2x/ecore_hsi.h
View File

File diff suppressed because it is too large Load Diff

11
drivers/net/bnx2x/ecore_sp.c
View File

@ -3524,13 +3524,6 @@ static int ecore_setup_rss(struct bnx2x_softc *sc,
data->capabilities |=
ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
if (ECORE_TEST_BIT(ECORE_RSS_TUNNELING, &p->rss_flags)) {
data->udp_4tuple_dst_port_mask =
ECORE_CPU_TO_LE16(p->tunnel_mask);
data->udp_4tuple_dst_port_value =
ECORE_CPU_TO_LE16(p->tunnel_value);
}
/* Hashing mask */
data->rss_result_mask = p->rss_result_mask;
@ -5088,8 +5081,6 @@ static int ecore_func_send_start(struct bnx2x_softc *sc,
rdata->sd_vlan_tag = ECORE_CPU_TO_LE16(start_params->sd_vlan_tag);
rdata->path_id = ECORE_PATH_ID(sc);
rdata->network_cos_mode = start_params->network_cos_mode;
rdata->gre_tunnel_mode = start_params->gre_tunnel_mode;
rdata->gre_tunnel_rss = start_params->gre_tunnel_rss;
/*
* No need for an explicit memory barrier here as long we would
@ -5229,7 +5220,7 @@ static int ecore_func_send_tx_start(struct bnx2x_softc *sc, struct ecore_func_st
rdata->dcb_enabled = tx_start_params->dcb_enabled;
rdata->dcb_version = tx_start_params->dcb_version;
rdata->dont_add_pri_0 = tx_start_params->dont_add_pri_0;
rdata->dont_add_pri_0_en = tx_start_params->dont_add_pri_0;
for (i = 0; i < ARRAY_SIZE(rdata->traffic_type_to_priority_cos); i++)
rdata->traffic_type_to_priority_cos[i] =