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net/i40e: warn when writing global registers

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Add warnings when writing global registers.

Signed-off-by: Beilei Xing <beilei.xing@intel.com>
Acked-by: Jingjing Wu <jingjing.wu@intel.com>
This commit is contained in:
Beilei Xing 2018-02-02 20:05:49 +08:00 committed by Ferruh Yigit
parent 745d58e0df
commit 399c635c39
5 changed files with 82 additions and 0 deletions
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12
doc/guides/nics/i40e.rst
View File

@ -566,6 +566,18 @@ DCB function
DCB works only when RSS is enabled.
Global configuration warning
~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I40E PMD will set some global registers to enable some function or set some
configure. Then when using different ports of the same NIC with Linux kernel
and DPDK, the port with Linux kernel will be impacted by the port with DPDK.
For example, register I40E_GL_SWT_L2TAGCTRL is used to control L2 tag, i40e
PMD uses I40E_GL_SWT_L2TAGCTRL to set vlan TPID. If setting TPID in port A
with DPDK, then the configuration will also impact port B in the NIC with
kernel driver, which don't want to use the TPID.
So PMD reports warning to clarify what is changed by writing global register.
High Performance of Small Packets on 40G NIC
--------------------------------------------

25
drivers/net/i40e/i40e_ethdev.c
View File

@ -680,6 +680,7 @@ static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
*/
I40E_WRITE_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
I40E_WRITE_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
}
#define I40E_FLOW_CONTROL_ETHERTYPE 0x8808
@ -1133,6 +1134,7 @@ eth_i40e_dev_init(struct rte_eth_dev *dev)
0x00000028, NULL);
if (ret)
PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d", ret);
i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
/* Need the special FW version to support floating VEB */
config_floating_veb(dev);
@ -1413,6 +1415,7 @@ void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
}
static int
@ -3262,6 +3265,7 @@ i40e_vlan_tpid_set(struct rte_eth_dev *dev,
/* If NVM API < 1.7, keep the register setting */
ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
tpid, qinq);
i40e_global_cfg_warning(I40E_WARNING_TPID);
return ret;
}
@ -3504,6 +3508,7 @@ i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
<< I40E_KILOSHIFT);
i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
I40E_WRITE_FLUSH(hw);
@ -7286,6 +7291,8 @@ i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!status)
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
return status;
}
@ -7340,6 +7347,8 @@ i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!status)
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
return status;
}
@ -7407,6 +7416,8 @@ i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!status)
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
return status;
}
@ -7459,6 +7470,8 @@ i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!status)
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
return status;
}
@ -8008,6 +8021,7 @@ i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
reg, NULL);
if (ret != 0)
return ret;
i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
} else {
ret = 0;
}
@ -8267,6 +8281,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
I40E_GLQF_HSYM(j),
reg);
}
i40e_global_cfg_warning(I40E_WARNING_HSYM);
}
}
@ -8292,6 +8307,7 @@ i40e_set_hash_filter_global_config(struct i40e_hw *hw,
goto out;
i40e_write_rx_ctl(hw, I40E_GLQF_CTL, reg);
i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
out:
I40E_WRITE_FLUSH(hw);
@ -8936,6 +8952,10 @@ i40e_filter_input_set_init(struct i40e_pf *pf)
pf->hash_input_set[pctype] = input_set;
pf->fdir.input_set[pctype] = input_set;
}
i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
}
int
@ -8996,6 +9016,7 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
i40e_check_write_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
(uint32_t)((inset_reg >>
I40E_32_BIT_WIDTH) & UINT32_MAX));
i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
for (i = 0; i < num; i++)
i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
@ -9004,6 +9025,7 @@ i40e_hash_filter_inset_select(struct i40e_hw *hw,
for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
i40e_check_write_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
0);
i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
I40E_WRITE_FLUSH(hw);
pf->hash_input_set[pctype] = input_set;
@ -9077,6 +9099,7 @@ i40e_fdir_filter_inset_select(struct i40e_pf *pf,
for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
0);
i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
I40E_WRITE_FLUSH(hw);
pf->fdir.input_set[pctype] = input_set;
@ -11644,6 +11667,8 @@ i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
&filter_replace_buf);
if (!ret)
i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
return ret;
}

43
drivers/net/i40e/i40e_ethdev.h
View File

@ -1069,6 +1069,22 @@ struct i40e_valid_pattern {
parse_filter_t parse_filter;
};
enum I40E_WARNING_IDX {
I40E_WARNING_DIS_FLX_PLD,
I40E_WARNING_ENA_FLX_PLD,
I40E_WARNING_QINQ_PARSER,
I40E_WARNING_QINQ_CLOUD_FILTER,
I40E_WARNING_TPID,
I40E_WARNING_FLOW_CTL,
I40E_WARNING_GRE_KEY_LEN,
I40E_WARNING_QF_CTL,
I40E_WARNING_HASH_INSET,
I40E_WARNING_HSYM,
I40E_WARNING_HASH_MSK,
I40E_WARNING_FD_MSK,
I40E_WARNING_RPL_CLD_FILTER,
};
int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
int i40e_vsi_release(struct i40e_vsi *vsi);
struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
@ -1277,6 +1293,33 @@ i40e_calc_itr_interval(int16_t interval, bool is_pf)
return interval / 2;
}
static inline void
i40e_global_cfg_warning(enum I40E_WARNING_IDX idx)
{
const char *warning;
static const char *const warning_list[] = {
[I40E_WARNING_DIS_FLX_PLD] = "disable FDIR flexible payload",
[I40E_WARNING_ENA_FLX_PLD] = "enable FDIR flexible payload",
[I40E_WARNING_QINQ_PARSER] = "support QinQ parser",
[I40E_WARNING_QINQ_CLOUD_FILTER] = "support QinQ cloud filter",
[I40E_WARNING_TPID] = "support TPID configuration",
[I40E_WARNING_FLOW_CTL] = "configure water marker",
[I40E_WARNING_GRE_KEY_LEN] = "support GRE key length setting",
[I40E_WARNING_QF_CTL] = "support hash function setting",
[I40E_WARNING_HASH_INSET] = "configure hash input set",
[I40E_WARNING_HSYM] = "set symmetric hash",
[I40E_WARNING_HASH_MSK] = "configure hash mask",
[I40E_WARNING_FD_MSK] = "configure fdir mask",
[I40E_WARNING_RPL_CLD_FILTER] = "replace cloud filter",
};
warning = warning_list[idx];
RTE_LOG(WARNING, PMD,
"Global register is changed during %s\n",
warning);
}
#define I40E_VALID_FLOW(flow_type) \
((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
(flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \

1
drivers/net/i40e/i40e_fdir.c
View File

@ -526,6 +526,7 @@ i40e_set_flx_pld_cfg(struct i40e_pf *pf,
(num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
(layer_idx * I40E_MAX_FLXPLD_FIED);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
}
for (i = 0; i < num; i++) {

1
drivers/net/i40e/i40e_flow.c
View File

@ -2260,6 +2260,7 @@ i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
(raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
(layer_idx * I40E_MAX_FLXPLD_FIED);
I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
}
/* Set flex pit */