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net/ena: update HAL to the newer version

Browse Source 
ena_com is the HAL provided by the vendor and it shouldn't be modified
by the driver developers.

The PMD and platform file was adjusted for the new version of the
ena_com:
    * Do not use deprecated meta descriptor fields
    * Add empty AENQ handler structure with unimplemented handlers
    * Add memzone allocations count to ena_ethdev.c file - it was
      removed from ena_com.c file
    * Add new macros used in new ena_com files
    * Use error code ENA_COM_UNSUPPORTED instead of ENA_COM_PERMISSION

Signed-off-by: Michal Krawczyk <mk@semihalf.com>
Signed-off-by: Rafal Kozik <rk@semihalf.com>
This commit is contained in:
Michal Krawczyk 2018-06-11 13:01:23 +02:00 committed by Ferruh Yigit
parent 68a48ef23b
commit 3adcba9a89
13 changed files with 1117 additions and 1865 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

707
drivers/net/ena/base/ena_com.c
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File diff suppressed because it is too large Load Diff

112
drivers/net/ena/base/ena_com.h
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@ -35,15 +35,7 @@
#define ENA_COM
#include "ena_plat.h"
#include "ena_common_defs.h"
#include "ena_admin_defs.h"
#include "ena_eth_io_defs.h"
#include "ena_regs_defs.h"
#if defined(__linux__) && !defined(__KERNEL__)
#include <rte_lcore.h>
#include <rte_spinlock.h>
#define __iomem
#endif
#include "ena_includes.h"
#define ENA_MAX_NUM_IO_QUEUES 128U
/* We need to queues for each IO (on for Tx and one for Rx) */
@ -89,6 +81,11 @@
#define ENA_INTR_DELAY_OLD_VALUE_WEIGHT 6
#define ENA_INTR_DELAY_NEW_VALUE_WEIGHT 4
#define ENA_INTR_MODER_LEVEL_STRIDE 1
#define ENA_INTR_BYTE_COUNT_NOT_SUPPORTED 0xFFFFFF
#define ENA_HW_HINTS_NO_TIMEOUT 0xFFFF
enum ena_intr_moder_level {
ENA_INTR_MODER_LOWEST = 0,
ENA_INTR_MODER_LOW,
@ -120,8 +117,8 @@ struct ena_com_rx_buf_info {
};
struct ena_com_io_desc_addr {
u8 __iomem *pbuf_dev_addr; /* LLQ address */
u8 *virt_addr;
u8 __iomem *pbuf_dev_addr; /* LLQ address */
u8 *virt_addr;
dma_addr_t phys_addr;
ena_mem_handle_t mem_handle;
};
@ -130,13 +127,12 @@ struct ena_com_tx_meta {
u16 mss;
u16 l3_hdr_len;
u16 l3_hdr_offset;
u16 l3_outer_hdr_len; /* In words */
u16 l3_outer_hdr_offset;
u16 l4_hdr_len; /* In words */
};
struct ena_com_io_cq {
struct ena_com_io_desc_addr cdesc_addr;
void *bus;
/* Interrupt unmask register */
u32 __iomem *unmask_reg;
@ -174,6 +170,7 @@ struct ena_com_io_cq {
struct ena_com_io_sq {
struct ena_com_io_desc_addr desc_addr;
void *bus;
u32 __iomem *db_addr;
u8 __iomem *header_addr;
@ -228,8 +225,11 @@ struct ena_com_stats_admin {
struct ena_com_admin_queue {
void *q_dmadev;
void *bus;
ena_spinlock_t q_lock; /* spinlock for the admin queue */
struct ena_comp_ctx *comp_ctx;
u32 completion_timeout;
u16 q_depth;
struct ena_com_admin_cq cq;
struct ena_com_admin_sq sq;
@ -266,6 +266,7 @@ struct ena_com_mmio_read {
struct ena_admin_ena_mmio_req_read_less_resp *read_resp;
dma_addr_t read_resp_dma_addr;
ena_mem_handle_t read_resp_mem_handle;
u32 reg_read_to; /* in us */
u16 seq_num;
bool readless_supported;
/* spin lock to ensure a single outstanding read */
@ -316,6 +317,7 @@ struct ena_com_dev {
u8 __iomem *reg_bar;
void __iomem *mem_bar;
void *dmadev;
void *bus;
enum ena_admin_placement_policy_type tx_mem_queue_type;
u32 tx_max_header_size;
@ -340,6 +342,7 @@ struct ena_com_dev_get_features_ctx {
struct ena_admin_device_attr_feature_desc dev_attr;
struct ena_admin_feature_aenq_desc aenq;
struct ena_admin_feature_offload_desc offload;
struct ena_admin_ena_hw_hints hw_hints;
};
struct ena_com_create_io_ctx {
@ -379,7 +382,7 @@ int ena_com_mmio_reg_read_request_init(struct ena_com_dev *ena_dev);
/* ena_com_set_mmio_read_mode - Enable/disable the mmio reg read mechanism
* @ena_dev: ENA communication layer struct
* @realess_supported: readless mode (enable/disable)
* @readless_supported: readless mode (enable/disable)
*/
void ena_com_set_mmio_read_mode(struct ena_com_dev *ena_dev,
bool readless_supported);
@ -421,14 +424,16 @@ void ena_com_admin_destroy(struct ena_com_dev *ena_dev);
/* ena_com_dev_reset - Perform device FLR to the device.
* @ena_dev: ENA communication layer struct
* @reset_reason: Specify what is the trigger for the reset in case of an error.
*
* @return - 0 on success, negative value on failure.
*/
int ena_com_dev_reset(struct ena_com_dev *ena_dev);
int ena_com_dev_reset(struct ena_com_dev *ena_dev,
enum ena_regs_reset_reason_types reset_reason);
/* ena_com_create_io_queue - Create io queue.
* @ena_dev: ENA communication layer struct
* ena_com_create_io_ctx - create context structure
* @ctx - create context structure
*
* Create the submission and the completion queues.
*
@ -437,8 +442,9 @@ int ena_com_dev_reset(struct ena_com_dev *ena_dev);
int ena_com_create_io_queue(struct ena_com_dev *ena_dev,
struct ena_com_create_io_ctx *ctx);
/* ena_com_admin_destroy - Destroy IO queue with the queue id - qid.
/* ena_com_destroy_io_queue - Destroy IO queue with the queue id - qid.
* @ena_dev: ENA communication layer struct
* @qid - the caller virtual queue id.
*/
void ena_com_destroy_io_queue(struct ena_com_dev *ena_dev, u16 qid);
@ -581,9 +587,8 @@ int ena_com_set_aenq_config(struct ena_com_dev *ena_dev, u32 groups_flag);
*
* @return: 0 on Success and negative value otherwise.
*/
int
ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
struct ena_com_dev_get_features_ctx *get_feat_ctx);
int ena_com_get_dev_attr_feat(struct ena_com_dev *ena_dev,
struct ena_com_dev_get_features_ctx *get_feat_ctx);
/* ena_com_get_dev_basic_stats - Get device basic statistics
* @ena_dev: ENA communication layer struct
@ -608,9 +613,8 @@ int ena_com_set_dev_mtu(struct ena_com_dev *ena_dev, int mtu);
*
* @return: 0 on Success and negative value otherwise.
*/
int
ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
struct ena_admin_feature_offload_desc *offload);
int ena_com_get_offload_settings(struct ena_com_dev *ena_dev,
struct ena_admin_feature_offload_desc *offload);
/* ena_com_rss_init - Init RSS
* @ena_dev: ENA communication layer struct
@ -765,8 +769,8 @@ int ena_com_indirect_table_set(struct ena_com_dev *ena_dev);
*
* Retrieve the RSS indirection table from the device.
*
* @note: If the caller called ena_com_indirect_table_fill_entry but didn't
* flash it to the device, the new configuration will be lost.
* @note: If the caller called ena_com_indirect_table_fill_entry but didn't flash
* it to the device, the new configuration will be lost.
*
* @return: 0 on Success and negative value otherwise.
*/
@ -874,8 +878,7 @@ bool ena_com_interrupt_moderation_supported(struct ena_com_dev *ena_dev);
* moderation table back to the default parameters.
* @ena_dev: ENA communication layer struct
*/
void
ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev);
void ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev);
/* ena_com_update_nonadaptive_moderation_interval_tx - Update the
* non-adaptive interval in Tx direction.
@ -884,9 +887,8 @@ ena_com_config_default_interrupt_moderation_table(struct ena_com_dev *ena_dev);
*
* @return - 0 on success, negative value on failure.
*/
int
ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
u32 tx_coalesce_usecs);
int ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
u32 tx_coalesce_usecs);
/* ena_com_update_nonadaptive_moderation_interval_rx - Update the
* non-adaptive interval in Rx direction.
@ -895,9 +897,8 @@ ena_com_update_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev,
*
* @return - 0 on success, negative value on failure.
*/
int
ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
u32 rx_coalesce_usecs);
int ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
u32 rx_coalesce_usecs);
/* ena_com_get_nonadaptive_moderation_interval_tx - Retrieve the
* non-adaptive interval in Tx direction.
@ -905,8 +906,7 @@ ena_com_update_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev,
*
* @return - interval in usec
*/
unsigned int
ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
unsigned int ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
/* ena_com_get_nonadaptive_moderation_interval_rx - Retrieve the
* non-adaptive interval in Rx direction.
@ -914,8 +914,7 @@ ena_com_get_nonadaptive_moderation_interval_tx(struct ena_com_dev *ena_dev);
*
* @return - interval in usec
*/
unsigned int
ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
unsigned int ena_com_get_nonadaptive_moderation_interval_rx(struct ena_com_dev *ena_dev);
/* ena_com_init_intr_moderation_entry - Update a single entry in the interrupt
* moderation table.
@ -940,20 +939,17 @@ void ena_com_get_intr_moderation_entry(struct ena_com_dev *ena_dev,
enum ena_intr_moder_level level,
struct ena_intr_moder_entry *entry);
static inline bool
ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
static inline bool ena_com_get_adaptive_moderation_enabled(struct ena_com_dev *ena_dev)
{
return ena_dev->adaptive_coalescing;
}
static inline void
ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
static inline void ena_com_enable_adaptive_moderation(struct ena_com_dev *ena_dev)
{
ena_dev->adaptive_coalescing = true;
}
static inline void
ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
static inline void ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
{
ena_dev->adaptive_coalescing = false;
}
@ -966,12 +962,11 @@ ena_com_disable_adaptive_moderation(struct ena_com_dev *ena_dev)
* @moder_tbl_idx: Current table level as input update new level as return
* value.
*/
static inline void
ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,
unsigned int pkts,
unsigned int bytes,
unsigned int *smoothed_interval,
unsigned int *moder_tbl_idx)
static inline void ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,
unsigned int pkts,
unsigned int bytes,
unsigned int *smoothed_interval,
unsigned int *moder_tbl_idx)
{
enum ena_intr_moder_level curr_moder_idx, new_moder_idx;
struct ena_intr_moder_entry *curr_moder_entry;
@ -1001,17 +996,20 @@ ena_com_calculate_interrupt_delay(struct ena_com_dev *ena_dev,
if (curr_moder_idx == ENA_INTR_MODER_LOWEST) {
if ((pkts > curr_moder_entry->pkts_per_interval) ||
(bytes > curr_moder_entry->bytes_per_interval))
new_moder_idx = (enum ena_intr_moder_level)(curr_moder_idx + 1);
new_moder_idx =
(enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);
} else {
pred_moder_entry = &intr_moder_tbl[curr_moder_idx - 1];
pred_moder_entry = &intr_moder_tbl[curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE];
if ((pkts <= pred_moder_entry->pkts_per_interval) ||
(bytes <= pred_moder_entry->bytes_per_interval))
new_moder_idx = (enum ena_intr_moder_level)(curr_moder_idx - 1);
new_moder_idx =
(enum ena_intr_moder_level)(curr_moder_idx - ENA_INTR_MODER_LEVEL_STRIDE);
else if ((pkts > curr_moder_entry->pkts_per_interval) ||
(bytes > curr_moder_entry->bytes_per_interval)) {
if (curr_moder_idx != ENA_INTR_MODER_HIGHEST)
new_moder_idx = (enum ena_intr_moder_level)(curr_moder_idx + 1);
new_moder_idx =
(enum ena_intr_moder_level)(curr_moder_idx + ENA_INTR_MODER_LEVEL_STRIDE);
}
}
new_moder_entry = &intr_moder_tbl[new_moder_idx];
@ -1044,18 +1042,12 @@ static inline void ena_com_update_intr_reg(struct ena_eth_io_intr_reg *intr_reg,
intr_reg->intr_control |=
(tx_delay_interval << ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_SHIFT)
& ENA_ETH_IO_INTR_REG_RX_INTR_DELAY_MASK;
& ENA_ETH_IO_INTR_REG_TX_INTR_DELAY_MASK;
if (unmask)
intr_reg->intr_control |= ENA_ETH_IO_INTR_REG_INTR_UNMASK_MASK;
}
int ena_com_get_dev_extended_stats(struct ena_com_dev *ena_dev, char *buff,
u32 len);
int ena_com_extended_stats_set_func_queue(struct ena_com_dev *ena_dev,
u32 funct_queue);
#if defined(__cplusplus)
}
#endif /* __cplusplus */

1172
drivers/net/ena/base/ena_defs/ena_admin_defs.h
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File diff suppressed because it is too large Load Diff

8
drivers/net/ena/base/ena_defs/ena_common_defs.h
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@ -34,17 +34,13 @@
#ifndef _ENA_COMMON_H_
#define _ENA_COMMON_H_
/* spec version */
#define ENA_COMMON_SPEC_VERSION_MAJOR 0 /* spec version major */
#define ENA_COMMON_SPEC_VERSION_MINOR 10 /* spec version minor */
#define ENA_COMMON_SPEC_VERSION_MAJOR 0 /* */
#define ENA_COMMON_SPEC_VERSION_MINOR 10 /* */
/* ENA operates with 48-bit memory addresses. ena_mem_addr_t */
struct ena_common_mem_addr {
/* word 0 : low 32 bit of the memory address */
uint32_t mem_addr_low;
/* word 1 : */
/* high 16 bits of the memory address */
uint16_t mem_addr_high;
/* MBZ */

758
drivers/net/ena/base/ena_defs/ena_eth_io_defs.h
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File diff suppressed because it is too large Load Diff

4
drivers/net/ena/base/ena_defs/ena_gen_info.h
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@ -31,5 +31,5 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#define ENA_GEN_DATE "Sun Jun 5 10:24:39 IDT 2016"
#define ENA_GEN_COMMIT "17146ed"
#define ENA_GEN_DATE "Sun Oct 23 12:27:32 IDT 2016"
#define ENA_GEN_COMMIT "79d82fa"

2
drivers/net/ena/base/ena_defs/ena_includes.h
View File

@ -35,5 +35,3 @@
#include "ena_regs_defs.h"
#include "ena_admin_defs.h"
#include "ena_eth_io_defs.h"
#include "ena_efa_admin_defs.h"
#include "ena_efa_io_defs.h"

36
drivers/net/ena/base/ena_defs/ena_regs_defs.h
View File

@ -34,6 +34,38 @@
#ifndef _ENA_REGS_H_
#define _ENA_REGS_H_
enum ena_regs_reset_reason_types {
ENA_REGS_RESET_NORMAL = 0,
ENA_REGS_RESET_KEEP_ALIVE_TO = 1,
ENA_REGS_RESET_ADMIN_TO = 2,
ENA_REGS_RESET_MISS_TX_CMPL = 3,
ENA_REGS_RESET_INV_RX_REQ_ID = 4,
ENA_REGS_RESET_INV_TX_REQ_ID = 5,
ENA_REGS_RESET_TOO_MANY_RX_DESCS = 6,
ENA_REGS_RESET_INIT_ERR = 7,
ENA_REGS_RESET_DRIVER_INVALID_STATE = 8,
ENA_REGS_RESET_OS_TRIGGER = 9,
ENA_REGS_RESET_OS_NETDEV_WD = 10,
ENA_REGS_RESET_SHUTDOWN = 11,
ENA_REGS_RESET_USER_TRIGGER = 12,
ENA_REGS_RESET_GENERIC = 13,
ENA_REGS_RESET_MISS_INTERRUPT = 14,
};
/* ena_registers offsets */
#define ENA_REGS_VERSION_OFF 0x0
#define ENA_REGS_CONTROLLER_VERSION_OFF 0x4
@ -80,6 +112,8 @@
#define ENA_REGS_CAPS_RESET_TIMEOUT_MASK 0x3e
#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_SHIFT 8
#define ENA_REGS_CAPS_DMA_ADDR_WIDTH_MASK 0xff00
#define ENA_REGS_CAPS_ADMIN_CMD_TO_SHIFT 16
#define ENA_REGS_CAPS_ADMIN_CMD_TO_MASK 0xf0000
/* aq_caps register */
#define ENA_REGS_AQ_CAPS_AQ_DEPTH_MASK 0xffff
@ -104,6 +138,8 @@
#define ENA_REGS_DEV_CTL_QUIESCENT_MASK 0x4
#define ENA_REGS_DEV_CTL_IO_RESUME_SHIFT 3
#define ENA_REGS_DEV_CTL_IO_RESUME_MASK 0x8
#define ENA_REGS_DEV_CTL_RESET_REASON_SHIFT 28
#define ENA_REGS_DEV_CTL_RESET_REASON_MASK 0xf0000000
/* dev_sts register */
#define ENA_REGS_DEV_STS_READY_MASK 0x1

78
drivers/net/ena/base/ena_eth_com.c
View File

@ -43,11 +43,10 @@ static inline struct ena_eth_io_rx_cdesc_base *ena_com_get_next_rx_cdesc(
head_masked = io_cq->head & (io_cq->q_depth - 1);
expected_phase = io_cq->phase;
cdesc = (struct ena_eth_io_rx_cdesc_base *)
((unsigned char *)io_cq->cdesc_addr.virt_addr
cdesc = (struct ena_eth_io_rx_cdesc_base *)(io_cq->cdesc_addr.virt_addr
+ (head_masked * io_cq->cdesc_entry_size_in_bytes));
desc_phase = (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >>
desc_phase = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_PHASE_MASK) >>
ENA_ETH_IO_RX_CDESC_BASE_PHASE_SHIFT;
if (desc_phase != expected_phase)
@ -74,7 +73,7 @@ static inline void *get_sq_desc(struct ena_com_io_sq *io_sq)
offset = tail_masked * io_sq->desc_entry_size;
return (unsigned char *)io_sq->desc_addr.virt_addr + offset;
return (void *)((uintptr_t)io_sq->desc_addr.virt_addr + offset);
}
static inline void ena_com_copy_curr_sq_desc_to_dev(struct ena_com_io_sq *io_sq)
@ -86,8 +85,8 @@ static inline void ena_com_copy_curr_sq_desc_to_dev(struct ena_com_io_sq *io_sq)
if (io_sq->mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_HOST)
return;
memcpy_toio((unsigned char *)io_sq->desc_addr.pbuf_dev_addr + offset,
(unsigned char *)io_sq->desc_addr.virt_addr + offset,
memcpy_toio(io_sq->desc_addr.pbuf_dev_addr + offset,
io_sq->desc_addr.virt_addr + offset,
io_sq->desc_entry_size);
}
@ -125,11 +124,11 @@ static inline struct ena_eth_io_rx_cdesc_base *
{
idx &= (io_cq->q_depth - 1);
return (struct ena_eth_io_rx_cdesc_base *)
((unsigned char *)io_cq->cdesc_addr.virt_addr +
idx * io_cq->cdesc_entry_size_in_bytes);
((uintptr_t)io_cq->cdesc_addr.virt_addr +
idx * io_cq->cdesc_entry_size_in_bytes);
}
static inline int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
static inline u16 ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
u16 *first_cdesc_idx)
{
struct ena_eth_io_rx_cdesc_base *cdesc;
@ -143,7 +142,7 @@ static inline int ena_com_cdesc_rx_pkt_get(struct ena_com_io_cq *io_cq,
ena_com_cq_inc_head(io_cq);
count++;
last = (cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>
last = (READ_ONCE(cdesc->status) & ENA_ETH_IO_RX_CDESC_BASE_LAST_MASK) >>
ENA_ETH_IO_RX_CDESC_BASE_LAST_SHIFT;
} while (!last);
@ -183,9 +182,8 @@ static inline bool ena_com_meta_desc_changed(struct ena_com_io_sq *io_sq,
return false;
}
static inline void ena_com_create_and_store_tx_meta_desc(
struct ena_com_io_sq *io_sq,
struct ena_com_tx_ctx *ena_tx_ctx)
static inline void ena_com_create_and_store_tx_meta_desc(struct ena_com_io_sq *io_sq,
struct ena_com_tx_ctx *ena_tx_ctx)
{
struct ena_eth_io_tx_meta_desc *meta_desc = NULL;
struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
@ -203,8 +201,8 @@ static inline void ena_com_create_and_store_tx_meta_desc(
ENA_ETH_IO_TX_META_DESC_MSS_LO_MASK;
/* bits 10-13 of the mss */
meta_desc->len_ctrl |= ((ena_meta->mss >> 10) <<
ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_SHIFT) &
ENA_ETH_IO_TX_META_DESC_MSS_HI_PTP_MASK;
ENA_ETH_IO_TX_META_DESC_MSS_HI_SHIFT) &
ENA_ETH_IO_TX_META_DESC_MSS_HI_MASK;
/* Extended meta desc */
meta_desc->len_ctrl |= ENA_ETH_IO_TX_META_DESC_ETH_META_TYPE_MASK;
@ -237,11 +235,11 @@ static inline void ena_com_create_and_store_tx_meta_desc(
static inline void ena_com_rx_set_flags(struct ena_com_rx_ctx *ena_rx_ctx,
struct ena_eth_io_rx_cdesc_base *cdesc)
{
ena_rx_ctx->l3_proto = (enum ena_eth_io_l3_proto_index)(cdesc->status &
ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK);
ena_rx_ctx->l4_proto = (enum ena_eth_io_l4_proto_index)
((cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >>
ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT);
ena_rx_ctx->l3_proto = cdesc->status &
ENA_ETH_IO_RX_CDESC_BASE_L3_PROTO_IDX_MASK;
ena_rx_ctx->l4_proto =
(cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_MASK) >>
ENA_ETH_IO_RX_CDESC_BASE_L4_PROTO_IDX_SHIFT;
ena_rx_ctx->l3_csum_err =
(cdesc->status & ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_MASK) >>
ENA_ETH_IO_RX_CDESC_BASE_L3_CSUM_ERR_SHIFT;
@ -280,8 +278,8 @@ int ena_com_prepare_tx(struct ena_com_io_sq *io_sq,
bool have_meta;
u64 addr_hi;
ENA_ASSERT(io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_TX,
"wrong Q type");
ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_TX,
"wrong Q type");
/* num_bufs +1 for potential meta desc */
if (ena_com_sq_empty_space(io_sq) < (num_bufs + 1)) {
@ -410,8 +408,8 @@ int ena_com_rx_pkt(struct ena_com_io_cq *io_cq,
u16 nb_hw_desc;
u16 i;
ENA_ASSERT(io_cq->direction == ENA_COM_IO_QUEUE_DIRECTION_RX,
"wrong Q type");
ENA_WARN(io_cq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,
"wrong Q type");
nb_hw_desc = ena_com_cdesc_rx_pkt_get(io_cq, &cdesc_idx);
if (nb_hw_desc == 0) {
@ -455,8 +453,8 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
{
struct ena_eth_io_rx_desc *desc;
ENA_ASSERT(io_sq->direction == ENA_COM_IO_QUEUE_DIRECTION_RX,
"wrong Q type");
ENA_WARN(io_sq->direction != ENA_COM_IO_QUEUE_DIRECTION_RX,
"wrong Q type");
if (unlikely(ena_com_sq_empty_space(io_sq) == 0))
return ENA_COM_NO_SPACE;
@ -475,8 +473,7 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
desc->buff_addr_lo = (u32)ena_buf->paddr;
desc->buff_addr_hi =
((ena_buf->paddr &
GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
((ena_buf->paddr & GENMASK_ULL(io_sq->dma_addr_bits - 1, 32)) >> 32);
ena_com_sq_update_tail(io_sq);
@ -493,20 +490,37 @@ int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id)
expected_phase = io_cq->phase;
cdesc = (struct ena_eth_io_tx_cdesc *)
((unsigned char *)io_cq->cdesc_addr.virt_addr
+ (masked_head * io_cq->cdesc_entry_size_in_bytes));
((uintptr_t)io_cq->cdesc_addr.virt_addr +
(masked_head * io_cq->cdesc_entry_size_in_bytes));
/* When the current completion descriptor phase isn't the same as the
* expected, it mean that the device still didn't update
* this completion.
*/
cdesc_phase = cdesc->flags & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
cdesc_phase = READ_ONCE(cdesc->flags) & ENA_ETH_IO_TX_CDESC_PHASE_MASK;
if (cdesc_phase != expected_phase)
return ENA_COM_TRY_AGAIN;
if (unlikely(cdesc->req_id >= io_cq->q_depth)) {
ena_trc_err("Invalid req id %d\n", cdesc->req_id);
return ENA_COM_INVAL;
}
ena_com_cq_inc_head(io_cq);
*req_id = cdesc->req_id;
*req_id = READ_ONCE(cdesc->req_id);
return 0;
}
bool ena_com_cq_empty(struct ena_com_io_cq *io_cq)
{
struct ena_eth_io_rx_cdesc_base *cdesc;
cdesc = ena_com_get_next_rx_cdesc(io_cq);
if (cdesc)
return false;
else
return true;
}

10
drivers/net/ena/base/ena_eth_com.h
View File

@ -92,10 +92,12 @@ int ena_com_add_single_rx_desc(struct ena_com_io_sq *io_sq,
int ena_com_tx_comp_req_id_get(struct ena_com_io_cq *io_cq, u16 *req_id);
bool ena_com_cq_empty(struct ena_com_io_cq *io_cq);
static inline void ena_com_unmask_intr(struct ena_com_io_cq *io_cq,
struct ena_eth_io_intr_reg *intr_reg)
{
ENA_REG_WRITE32(intr_reg->intr_control, io_cq->unmask_reg);
ENA_REG_WRITE32(io_cq->bus, intr_reg->intr_control, io_cq->unmask_reg);
}
static inline int ena_com_sq_empty_space(struct ena_com_io_sq *io_sq)
@ -118,7 +120,7 @@ static inline int ena_com_write_sq_doorbell(struct ena_com_io_sq *io_sq)
ena_trc_dbg("write submission queue doorbell for queue: %d tail: %d\n",
io_sq->qid, tail);
ENA_REG_WRITE32(tail, io_sq->db_addr);
ENA_REG_WRITE32(io_sq->bus, tail, io_sq->db_addr);
return 0;
}
@ -135,7 +137,7 @@ static inline int ena_com_update_dev_comp_head(struct ena_com_io_cq *io_cq)
if (io_cq->cq_head_db_reg && need_update) {
ena_trc_dbg("Write completion queue doorbell for queue %d: head: %d\n",
io_cq->qid, head);
ENA_REG_WRITE32(head, io_cq->cq_head_db_reg);
ENA_REG_WRITE32(io_cq->bus, head, io_cq->cq_head_db_reg);
io_cq->last_head_update = head;
}
@ -153,7 +155,7 @@ static inline void ena_com_update_numa_node(struct ena_com_io_cq *io_cq,
numa_cfg.numa_cfg = (numa_node & ENA_ETH_IO_NUMA_NODE_CFG_REG_NUMA_MASK)
| ENA_ETH_IO_NUMA_NODE_CFG_REG_ENABLED_MASK;
ENA_REG_WRITE32(numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);
ENA_REG_WRITE32(io_cq->bus, numa_cfg.numa_cfg, io_cq->numa_node_cfg_reg);
}
static inline void ena_com_comp_ack(struct ena_com_io_sq *io_sq, u16 elem)

2
drivers/net/ena/base/ena_plat.h
View File

@ -42,8 +42,6 @@
#else
#include "ena_plat_dpdk.h"
#endif
#elif defined(__FreeBSD__)
#include "ena_plat_dpdk.h"
#elif defined(_WIN32)
#include "ena_plat_windows.h"
#else

39
drivers/net/ena/base/ena_plat_dpdk.h
View File

@ -73,10 +73,10 @@ typedef uint64_t dma_addr_t;
#define ENA_COM_INVAL -EINVAL
#define ENA_COM_NO_SPACE -ENOSPC
#define ENA_COM_NO_DEVICE -ENODEV
#define ENA_COM_PERMISSION -EPERM
#define ENA_COM_TIMER_EXPIRED -ETIME
#define ENA_COM_FAULT -EFAULT
#define ENA_COM_TRY_AGAIN -EAGAIN
#define ENA_COM_UNSUPPORTED -EOPNOTSUPP
#define ____cacheline_aligned __rte_cache_aligned
@ -138,6 +138,15 @@ typedef uint64_t dma_addr_t;
#define ena_trc_err(format, arg...) do { } while (0)
#endif /* RTE_LIBRTE_ENA_COM_DEBUG */
#define ENA_WARN(cond, format, arg...) \
do { \
if (unlikely(cond)) { \
ena_trc_err( \
"Warn failed on %s:%s:%d:" format, \
__FILE__, __func__, __LINE__, ##arg); \
} \
} while (0)
/* Spinlock related methods */
#define ena_spinlock_t rte_spinlock_t
#define ENA_SPINLOCK_INIT(spinlock) rte_spinlock_init(&spinlock)
@ -177,10 +186,21 @@ typedef uint64_t dma_addr_t;
#define ENA_WAIT_EVENT_SIGNAL(waitevent) pthread_cond_signal(&waitevent.cond)
/* pthread condition doesn't need to be rearmed after usage */
#define ENA_WAIT_EVENT_CLEAR(...)
#define ENA_WAIT_EVENT_DESTROY(waitqueue) ((void)(waitqueue))
#define ena_wait_event_t ena_wait_queue_t
#define ENA_MIGHT_SLEEP()
#define ENA_TIME_EXPIRE(timeout) (timeout < rte_get_timer_cycles())
#define ENA_GET_SYSTEM_TIMEOUT(timeout_us) \
(timeout_us * rte_get_timer_hz() / 1000000 + rte_get_timer_cycles())
/*
* Each rte_memzone should have unique name.
* To satisfy it, count number of allocations and add it to name.
*/
extern uint32_t ena_alloc_cnt;
#define ENA_MEM_ALLOC_COHERENT(dmadev, size, virt, phys, handle) \
do { \
const struct rte_memzone *mz; \
@ -200,7 +220,8 @@ typedef uint64_t dma_addr_t;
ENA_TOUCH(dmadev); \
rte_memzone_free(handle); })
#define ENA_MEM_ALLOC_COHERENT_NODE(dmadev, size, virt, phys, node, dev_node) \
#define ENA_MEM_ALLOC_COHERENT_NODE( \
dmadev, size, virt, phys, mem_handle, node, dev_node) \
do { \
const struct rte_memzone *mz; \
char z_name[RTE_MEMZONE_NAMESIZE]; \
@ -212,6 +233,7 @@ typedef uint64_t dma_addr_t;
memset(mz->addr, 0, size); \
virt = mz->addr; \
phys = mz->iova; \
(void)mem_handle; \
} while (0)
#define ENA_MEM_ALLOC_NODE(dmadev, size, virt, node, dev_node) \
@ -230,8 +252,10 @@ typedef uint64_t dma_addr_t;
#define ENA_MEM_ALLOC(dmadev, size) rte_zmalloc(NULL, size, 1)
#define ENA_MEM_FREE(dmadev, ptr) ({ENA_TOUCH(dmadev); rte_free(ptr); })
#define ENA_REG_WRITE32(value, reg) rte_write32_relaxed((value), (reg))
#define ENA_REG_READ32(reg) rte_read32_relaxed((reg))
#define ENA_REG_WRITE32(bus, value, reg) \
({ (void)(bus); rte_write32_relaxed((value), (reg)); })
#define ENA_REG_READ32(bus, reg) \
({ (void)(bus); rte_read32_relaxed((reg)); })
#define ATOMIC32_INC(i32_ptr) rte_atomic32_inc(i32_ptr)
#define ATOMIC32_DEC(i32_ptr) rte_atomic32_dec(i32_ptr)
@ -247,4 +271,11 @@ typedef uint64_t dma_addr_t;
#define PTR_ERR(error) ((long)(void *)error)
#define might_sleep()
#define lower_32_bits(x) ((uint32_t)(x))
#define upper_32_bits(x) ((uint32_t)(((x) >> 16) >> 16))
#ifndef READ_ONCE
#define READ_ONCE(var) (*((volatile typeof(var) *)(&(var))))
#endif
#endif /* DPDK_ENA_COM_ENA_PLAT_DPDK_H_ */

54
drivers/net/ena/ena_ethdev.c
View File

@ -114,6 +114,12 @@ struct ena_stats {
#define ENA_STAT_GLOBAL_ENTRY(stat) \
ENA_STAT_ENTRY(stat, dev)
/*
* Each rte_memzone should have unique name.
* To satisfy it, count number of allocation and add it to name.
*/
uint32_t ena_alloc_cnt;
static const struct ena_stats ena_stats_global_strings[] = {
ENA_STAT_GLOBAL_ENTRY(tx_timeout),
ENA_STAT_GLOBAL_ENTRY(io_suspend),
@ -195,6 +201,8 @@ static const struct rte_pci_id pci_id_ena_map[] = {
{ .device_id = 0 },
};
static struct ena_aenq_handlers empty_aenq_handlers;
static int ena_device_init(struct ena_com_dev *ena_dev,
struct ena_com_dev_get_features_ctx *get_feat_ctx);
static int ena_dev_configure(struct rte_eth_dev *dev);
@ -346,9 +354,6 @@ static inline void ena_tx_mbuf_prepare(struct rte_mbuf *mbuf,
ena_meta->mss = mbuf->tso_segsz;
ena_meta->l3_hdr_len = mbuf->l3_len;
ena_meta->l3_hdr_offset = mbuf->l2_len;
/* this param needed only for TSO */
ena_meta->l3_outer_hdr_len = 0;
ena_meta->l3_outer_hdr_offset = 0;
ena_tx_ctx->meta_valid = true;
} else {
@ -388,7 +393,7 @@ static void ena_config_host_info(struct ena_com_dev *ena_dev)
rc = ena_com_set_host_attributes(ena_dev);
if (rc) {
RTE_LOG(ERR, PMD, "Cannot set host attributes\n");
if (rc != -EPERM)
if (rc != -ENA_COM_UNSUPPORTED)
goto err;
}
@ -441,7 +446,7 @@ static void ena_config_debug_area(struct ena_adapter *adapter)
rc = ena_com_set_host_attributes(&adapter->ena_dev);
if (rc) {
RTE_LOG(WARNING, PMD, "Cannot set host attributes\n");
if (rc != -EPERM)
if (rc != -ENA_COM_UNSUPPORTED)
goto err;
}
@ -496,7 +501,7 @@ static int ena_rss_reta_update(struct rte_eth_dev *dev,
ret = ena_com_indirect_table_fill_entry(ena_dev,
i,
entry_value);
if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
RTE_LOG(ERR, PMD,
"Cannot fill indirect table\n");
ret = -ENOTSUP;
@ -506,7 +511,7 @@ static int ena_rss_reta_update(struct rte_eth_dev *dev,
}
ret = ena_com_indirect_table_set(ena_dev);
if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
ret = -ENOTSUP;
goto err;
@ -537,7 +542,7 @@ static int ena_rss_reta_query(struct rte_eth_dev *dev,
return -EINVAL;
ret = ena_com_indirect_table_get(ena_dev, indirect_table);
if (unlikely(ret && (ret != ENA_COM_PERMISSION))) {
if (unlikely(ret && (ret != ENA_COM_UNSUPPORTED))) {
RTE_LOG(ERR, PMD, "cannot get indirect table\n");
ret = -ENOTSUP;
goto err;
@ -571,7 +576,7 @@ static int ena_rss_init_default(struct ena_adapter *adapter)
val = i % nb_rx_queues;
rc = ena_com_indirect_table_fill_entry(ena_dev, i,
ENA_IO_RXQ_IDX(val));
if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
RTE_LOG(ERR, PMD, "Cannot fill indirect table\n");
goto err_fill_indir;
}
@ -579,19 +584,19 @@ static int ena_rss_init_default(struct ena_adapter *adapter)
rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
RTE_LOG(INFO, PMD, "Cannot fill hash function\n");
goto err_fill_indir;
}
rc = ena_com_set_default_hash_ctrl(ena_dev);
if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
RTE_LOG(INFO, PMD, "Cannot fill hash control\n");
goto err_fill_indir;
}
rc = ena_com_indirect_table_set(ena_dev);
if (unlikely(rc && (rc != ENA_COM_PERMISSION))) {
if (unlikely(rc && (rc != ENA_COM_UNSUPPORTED))) {
RTE_LOG(ERR, PMD, "Cannot flush the indirect table\n");
goto err_fill_indir;
}
@ -1236,7 +1241,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev,
ena_com_set_mmio_read_mode(ena_dev, readless_supported);
/* reset device */
rc = ena_com_dev_reset(ena_dev);
rc = ena_com_dev_reset(ena_dev, ENA_REGS_RESET_NORMAL);
if (rc) {
RTE_LOG(ERR, PMD, "cannot reset device\n");
goto err_mmio_read_less;
@ -1252,7 +1257,7 @@ static int ena_device_init(struct ena_com_dev *ena_dev,
ena_dev->dma_addr_bits = ena_com_get_dma_width(ena_dev);
/* ENA device administration layer init */
rc = ena_com_admin_init(ena_dev, NULL, true);
rc = ena_com_admin_init(ena_dev, &empty_aenq_handlers, true);
if (rc) {
RTE_LOG(ERR, PMD,
"cannot initialize ena admin queue with device\n");
@ -1854,3 +1859,24 @@ ena_init_log(void)
if (ena_logtype_driver >= 0)
rte_log_set_level(ena_logtype_driver, RTE_LOG_NOTICE);
}
/******************************************************************************
******************************** AENQ Handlers *******************************
*****************************************************************************/
/**
* This handler will called for unknown event group or unimplemented handlers
**/
static void unimplemented_aenq_handler(__rte_unused void *data,
__rte_unused struct ena_admin_aenq_entry *aenq_e)
{
// Unimplemented handler
}
static struct ena_aenq_handlers empty_aenq_handlers = {
.handlers = {
[ENA_ADMIN_LINK_CHANGE] = unimplemented_aenq_handler,
[ENA_ADMIN_NOTIFICATION] = unimplemented_aenq_handler,
[ENA_ADMIN_KEEP_ALIVE] = unimplemented_aenq_handler
},
.unimplemented_handler = unimplemented_aenq_handler
};