cxgbe/base: add hardware API for Chelsio T5 series adapters
Adds hardware specific api for all the Chelsio T5 adapters under drivers/net/cxgbe/base directory. Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Kumar Sanghvi <kumaras@chelsio.com>
This commit is contained in:
Rahul Lakkireddy
Thomas Monjalon
parent
cca619e459
commit
3bd122eef2
565
drivers/net/cxgbe/base/adapter.h
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565
drivers/net/cxgbe/base/adapter.h
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@ -0,0 +1,565 @@
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/*-
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* BSD LICENSE
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*
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* Copyright(c) 2014-2015 Chelsio Communications.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Chelsio Communications nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* This file should not be included directly. Include common.h instead. */
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#ifndef __T4_ADAPTER_H__
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#define __T4_ADAPTER_H__
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#include <rte_mbuf.h>
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#include "cxgbe_compat.h"
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#include "t4_regs_values.h"
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enum {
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MAX_ETH_QSETS = 64, /* # of Ethernet Tx/Rx queue sets */
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};
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struct adapter;
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struct sge_rspq;
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enum {
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PORT_RSS_DONE = (1 << 0),
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};
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struct port_info {
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struct adapter *adapter; /* adapter that this port belongs to */
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struct rte_eth_dev *eth_dev; /* associated rte eth device */
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struct port_stats stats_base; /* port statistics base */
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struct link_config link_cfg; /* link configuration info */
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unsigned long flags; /* port related flags */
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short int xact_addr_filt; /* index of exact MAC address filter */
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u16 viid; /* associated virtual interface id */
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s8 mdio_addr; /* address of the PHY */
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u8 port_type; /* firmware port type */
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u8 mod_type; /* firmware module type */
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u8 port_id; /* physical port ID */
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u8 tx_chan; /* associated channel */
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u8 n_rx_qsets; /* # of rx qsets */
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u8 n_tx_qsets; /* # of tx qsets */
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u8 first_qset; /* index of first qset */
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u16 *rss; /* rss table */
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u8 rss_mode; /* rss mode */
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u16 rss_size; /* size of VI's RSS table slice */
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};
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/* Enable or disable autonegotiation. If this is set to enable,
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* the forced link modes above are completely ignored.
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*/
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#define AUTONEG_DISABLE 0x00
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#define AUTONEG_ENABLE 0x01
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enum { /* adapter flags */
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FULL_INIT_DONE = (1 << 0),
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USING_MSI = (1 << 1),
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USING_MSIX = (1 << 2),
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FW_QUEUE_BOUND = (1 << 3),
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FW_OK = (1 << 4),
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CFG_QUEUES = (1 << 5),
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MASTER_PF = (1 << 6),
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};
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struct rx_sw_desc { /* SW state per Rx descriptor */
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void *buf; /* struct page or mbuf */
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dma_addr_t dma_addr;
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};
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struct sge_fl { /* SGE free-buffer queue state */
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/* RO fields */
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struct rx_sw_desc *sdesc; /* address of SW Rx descriptor ring */
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dma_addr_t addr; /* bus address of HW ring start */
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__be64 *desc; /* address of HW Rx descriptor ring */
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void __iomem *bar2_addr; /* address of BAR2 Queue registers */
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unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
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unsigned int cntxt_id; /* SGE relative QID for the free list */
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unsigned int size; /* capacity of free list */
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unsigned int avail; /* # of available Rx buffers */
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unsigned int pend_cred; /* new buffers since last FL DB ring */
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unsigned int cidx; /* consumer index */
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unsigned int pidx; /* producer index */
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unsigned long alloc_failed; /* # of times buffer allocation failed */
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unsigned long low; /* # of times momentarily starving */
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};
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#define MAX_MBUF_FRAGS (16384 / 512 + 2)
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/* A packet gather list */
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struct pkt_gl {
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union {
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struct rte_mbuf *mbufs[MAX_MBUF_FRAGS];
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} /* UNNAMED */;
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void *va; /* virtual address of first byte */
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unsigned int nfrags; /* # of fragments */
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unsigned int tot_len; /* total length of fragments */
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bool usembufs; /* use mbufs for fragments */
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};
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typedef int (*rspq_handler_t)(struct sge_rspq *q, const __be64 *rsp,
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const struct pkt_gl *gl);
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struct sge_rspq { /* state for an SGE response queue */
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struct adapter *adapter; /* adapter that this queue belongs to */
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struct rte_eth_dev *eth_dev; /* associated rte eth device */
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struct rte_mempool *mb_pool; /* associated mempool */
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dma_addr_t phys_addr; /* physical address of the ring */
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__be64 *desc; /* address of HW response ring */
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const __be64 *cur_desc; /* current descriptor in queue */
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void __iomem *bar2_addr; /* address of BAR2 Queue registers */
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unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
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unsigned int cidx; /* consumer index */
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unsigned int iqe_len; /* entry size */
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unsigned int size; /* capacity of response queue */
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int offset; /* offset into current Rx buffer */
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u8 gen; /* current generation bit */
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u8 intr_params; /* interrupt holdoff parameters */
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u8 next_intr_params; /* holdoff params for next interrupt */
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u8 pktcnt_idx; /* interrupt packet threshold */
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u8 idx; /* queue index within its group */
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u16 cntxt_id; /* SGE relative QID for the response Q */
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u16 abs_id; /* absolute SGE id for the response q */
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rspq_handler_t handler; /* associated handler for this response q */
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};
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struct sge_eth_rx_stats { /* Ethernet rx queue statistics */
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u64 pkts; /* # of ethernet packets */
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u64 rx_bytes; /* # of ethernet bytes */
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u64 rx_cso; /* # of Rx checksum offloads */
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u64 vlan_ex; /* # of Rx VLAN extractions */
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u64 rx_drops; /* # of packets dropped due to no mem */
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};
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struct sge_eth_rxq { /* a SW Ethernet Rx queue */
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struct sge_rspq rspq;
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struct sge_fl fl;
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struct sge_eth_rx_stats stats;
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bool usembufs; /* one ingress packet per mbuf FL buffer */
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} __rte_cache_aligned;
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/*
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* Currently there are two types of coalesce WR. Type 0 needs 48 bytes per
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* packet (if one sgl is present) and type 1 needs 32 bytes. This means
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* that type 0 can fit a maximum of 10 packets per WR and type 1 can fit
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* 15 packets. We need to keep track of the mbuf pointers in a coalesce WR
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* to be able to free those mbufs when we get completions back from the FW.
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* Allocating the maximum number of pointers in every tx desc is a waste
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* of memory resources so we only store 2 pointers per tx desc which should
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* be enough since a tx desc can only fit 2 packets in the best case
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* scenario where a packet needs 32 bytes.
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*/
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#define ETH_COALESCE_PKT_NUM 15
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#define ETH_COALESCE_PKT_PER_DESC 2
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struct tx_eth_coal_desc {
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struct rte_mbuf *mbuf[ETH_COALESCE_PKT_PER_DESC];
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struct ulptx_sgl *sgl[ETH_COALESCE_PKT_PER_DESC];
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int idx;
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};
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struct tx_desc {
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__be64 flit[8];
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};
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struct tx_sw_desc { /* SW state per Tx descriptor */
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struct rte_mbuf *mbuf;
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struct ulptx_sgl *sgl;
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struct tx_eth_coal_desc coalesce;
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};
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enum {
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EQ_STOPPED = (1 << 0),
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};
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struct eth_coalesce {
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unsigned char *ptr;
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unsigned char type;
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unsigned int idx;
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unsigned int len;
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unsigned int flits;
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unsigned int max;
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};
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struct sge_txq {
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struct tx_desc *desc; /* address of HW Tx descriptor ring */
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struct tx_sw_desc *sdesc; /* address of SW Tx descriptor ring */
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struct sge_qstat *stat; /* queue status entry */
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struct eth_coalesce coalesce; /* coalesce info */
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uint64_t phys_addr; /* physical address of the ring */
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void __iomem *bar2_addr; /* address of BAR2 Queue registers */
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unsigned int bar2_qid; /* Queue ID for BAR2 Queue registers */
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unsigned int cntxt_id; /* SGE relative QID for the Tx Q */
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unsigned int in_use; /* # of in-use Tx descriptors */
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unsigned int size; /* # of descriptors */
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unsigned int cidx; /* SW consumer index */
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unsigned int pidx; /* producer index */
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unsigned int dbidx; /* last idx when db ring was done */
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unsigned int equeidx; /* last sent credit request */
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unsigned int last_pidx; /* last pidx recorded by tx monitor */
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unsigned int last_coal_idx;/* last coal-idx recorded by tx monitor */
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int db_disabled; /* doorbell state */
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unsigned short db_pidx; /* doorbell producer index */
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unsigned short db_pidx_inc; /* doorbell producer increment */
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};
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struct sge_eth_tx_stats { /* Ethernet tx queue statistics */
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u64 pkts; /* # of ethernet packets */
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u64 tx_bytes; /* # of ethernet bytes */
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u64 tso; /* # of TSO requests */
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u64 tx_cso; /* # of Tx checksum offloads */
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u64 vlan_ins; /* # of Tx VLAN insertions */
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u64 mapping_err; /* # of I/O MMU packet mapping errors */
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u64 coal_wr; /* # of coalesced wr */
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u64 coal_pkts; /* # of coalesced packets */
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};
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struct sge_eth_txq { /* state for an SGE Ethernet Tx queue */
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struct sge_txq q;
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struct rte_eth_dev *eth_dev; /* port that this queue belongs to */
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struct sge_eth_tx_stats stats; /* queue statistics */
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rte_spinlock_t txq_lock;
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unsigned int flags; /* flags for state of the queue */
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} __rte_cache_aligned;
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struct sge {
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struct sge_eth_txq ethtxq[MAX_ETH_QSETS];
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struct sge_eth_rxq ethrxq[MAX_ETH_QSETS];
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struct sge_rspq fw_evtq __rte_cache_aligned;
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u16 max_ethqsets; /* # of available Ethernet queue sets */
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u32 stat_len; /* length of status page at ring end */
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u32 pktshift; /* padding between CPL & packet data */
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/* response queue interrupt parameters */
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u16 timer_val[SGE_NTIMERS];
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u8 counter_val[SGE_NCOUNTERS];
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u32 fl_align; /* response queue message alignment */
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u32 fl_pg_order; /* large page allocation size */
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u32 fl_starve_thres; /* Free List starvation threshold */
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};
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#define T4_OS_NEEDS_MBOX_LOCKING 1
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/*
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* OS Lock/List primitives for those interfaces in the Common Code which
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* need this.
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*/
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struct mbox_entry {
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TAILQ_ENTRY(mbox_entry) next;
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};
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TAILQ_HEAD(mbox_list, mbox_entry);
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struct adapter {
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struct rte_pci_device *pdev; /* associated rte pci device */
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struct rte_eth_dev *eth_dev; /* first port's rte eth device */
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struct adapter_params params; /* adapter parameters */
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struct port_info port[MAX_NPORTS]; /* ports belonging to this adapter */
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struct sge sge; /* associated SGE */
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/* support for single-threading access to adapter mailbox registers */
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struct mbox_list mbox_list;
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rte_spinlock_t mbox_lock;
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u8 *regs; /* pointer to registers region */
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u8 *bar2; /* pointer to bar2 region */
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unsigned long flags; /* adapter flags */
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unsigned int mbox; /* associated mailbox */
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unsigned int pf; /* associated physical function id */
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int use_unpacked_mode; /* unpacked rx mode state */
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};
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#define CXGBE_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
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static inline uint64_t cxgbe_read_addr64(volatile void *addr)
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{
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uint64_t val = CXGBE_PCI_REG(addr);
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uint64_t val2 = CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4));
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val2 = (uint64_t)(val2 << 32);
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val += val2;
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return val;
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}
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static inline uint32_t cxgbe_read_addr(volatile void *addr)
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{
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return CXGBE_PCI_REG(addr);
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}
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#define CXGBE_PCI_REG_ADDR(adap, reg) \
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((volatile uint32_t *)((char *)(adap)->regs + (reg)))
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#define CXGBE_READ_REG(adap, reg) \
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cxgbe_read_addr(CXGBE_PCI_REG_ADDR((adap), (reg)))
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#define CXGBE_READ_REG64(adap, reg) \
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cxgbe_read_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)))
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#define CXGBE_PCI_REG_WRITE(reg, value) ({ \
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CXGBE_PCI_REG((reg)) = (value); })
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#define CXGBE_WRITE_REG(adap, reg, value) \
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CXGBE_PCI_REG_WRITE(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
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static inline uint64_t cxgbe_write_addr64(volatile void *addr, uint64_t val)
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{
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CXGBE_PCI_REG(addr) = val;
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CXGBE_PCI_REG(((volatile uint8_t *)(addr) + 4)) = (val >> 32);
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return val;
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}
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#define CXGBE_WRITE_REG64(adap, reg, value) \
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cxgbe_write_addr64(CXGBE_PCI_REG_ADDR((adap), (reg)), (value))
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/**
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* t4_read_reg - read a HW register
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* @adapter: the adapter
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* @reg_addr: the register address
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*
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* Returns the 32-bit value of the given HW register.
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*/
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static inline u32 t4_read_reg(struct adapter *adapter, u32 reg_addr)
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{
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u32 val = CXGBE_READ_REG(adapter, reg_addr);
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CXGBE_DEBUG_REG(adapter, "read register 0x%x value 0x%x\n", reg_addr,
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val);
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return val;
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}
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/**
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* t4_write_reg - write a HW register
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* @adapter: the adapter
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* @reg_addr: the register address
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* @val: the value to write
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*
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* Write a 32-bit value into the given HW register.
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*/
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static inline void t4_write_reg(struct adapter *adapter, u32 reg_addr, u32 val)
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{
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CXGBE_DEBUG_REG(adapter, "setting register 0x%x to 0x%x\n", reg_addr,
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val);
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CXGBE_WRITE_REG(adapter, reg_addr, val);
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}
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/**
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* t4_read_reg64 - read a 64-bit HW register
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* @adapter: the adapter
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* @reg_addr: the register address
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*
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* Returns the 64-bit value of the given HW register.
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*/
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static inline u64 t4_read_reg64(struct adapter *adapter, u32 reg_addr)
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{
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u64 val = CXGBE_READ_REG64(adapter, reg_addr);
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CXGBE_DEBUG_REG(adapter, "64-bit read register %#x value %#llx\n",
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reg_addr, (unsigned long long)val);
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return val;
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}
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/**
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* t4_write_reg64 - write a 64-bit HW register
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* @adapter: the adapter
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* @reg_addr: the register address
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* @val: the value to write
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*
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* Write a 64-bit value into the given HW register.
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*/
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static inline void t4_write_reg64(struct adapter *adapter, u32 reg_addr,
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u64 val)
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{
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CXGBE_DEBUG_REG(adapter, "setting register %#x to %#llx\n", reg_addr,
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(unsigned long long)val);
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CXGBE_WRITE_REG64(adapter, reg_addr, val);
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}
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/**
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* t4_os_set_hw_addr - store a port's MAC address in SW
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* @adapter: the adapter
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* @port_idx: the port index
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* @hw_addr: the Ethernet address
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*
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* Store the Ethernet address of the given port in SW. Called by the
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* common code when it retrieves a port's Ethernet address from EEPROM.
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*/
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static inline void t4_os_set_hw_addr(struct adapter *adapter, int port_idx,
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u8 hw_addr[])
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{
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struct port_info *pi = &adapter->port[port_idx];
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ether_addr_copy((struct ether_addr *)hw_addr,
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&pi->eth_dev->data->mac_addrs[0]);
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}
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/**
|
||||
* t4_os_lock_init - initialize spinlock
|
||||
* @lock: the spinlock
|
||||
*/
|
||||
static inline void t4_os_lock_init(rte_spinlock_t *lock)
|
||||
{
|
||||
rte_spinlock_init(lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* t4_os_lock - spin until lock is acquired
|
||||
* @lock: the spinlock
|
||||
*/
|
||||
static inline void t4_os_lock(rte_spinlock_t *lock)
|
||||
{
|
||||
rte_spinlock_lock(lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* t4_os_unlock - unlock a spinlock
|
||||
* @lock: the spinlock
|
||||
*/
|
||||
static inline void t4_os_unlock(rte_spinlock_t *lock)
|
||||
{
|
||||
rte_spinlock_unlock(lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* t4_os_init_list_head - initialize
|
||||
* @head: head of list to initialize [to empty]
|
||||
*/
|
||||
static inline void t4_os_init_list_head(struct mbox_list *head)
|
||||
{
|
||||
TAILQ_INIT(head);
|
||||
}
|
||||
|
||||
static inline struct mbox_entry *t4_os_list_first_entry(struct mbox_list *head)
|
||||
{
|
||||
return TAILQ_FIRST(head);
|
||||
}
|
||||
|
||||
/**
|
||||
* t4_os_atomic_add_tail - Enqueue list element atomically onto list
|
||||
* @new: the entry to be addded to the queue
|
||||
* @head: current head of the linked list
|
||||
* @lock: lock to use to guarantee atomicity
|
||||
*/
|
||||
static inline void t4_os_atomic_add_tail(struct mbox_entry *entry,
|
||||
struct mbox_list *head,
|
||||
rte_spinlock_t *lock)
|
||||
{
|
||||
t4_os_lock(lock);
|
||||
TAILQ_INSERT_TAIL(head, entry, next);
|
||||
t4_os_unlock(lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* t4_os_atomic_list_del - Dequeue list element atomically from list
|
||||
* @entry: the entry to be remove/dequeued from the list.
|
||||
* @lock: the spinlock
|
||||
*/
|
||||
static inline void t4_os_atomic_list_del(struct mbox_entry *entry,
|
||||
struct mbox_list *head,
|
||||
rte_spinlock_t *lock)
|
||||
{
|
||||
t4_os_lock(lock);
|
||||
TAILQ_REMOVE(head, entry, next);
|
||||
t4_os_unlock(lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* adap2pinfo - return the port_info of a port
|
||||
* @adap: the adapter
|
||||
* @idx: the port index
|
||||
*
|
||||
* Return the port_info structure for the port of the given index.
|
||||
*/
|
||||
static inline struct port_info *adap2pinfo(struct adapter *adap, int idx)
|
||||
{
|
||||
return &adap->port[idx];
|
||||
}
|
||||
|
||||
void *t4_alloc_mem(size_t size);
|
||||
void t4_free_mem(void *addr);
|
||||
#define t4_os_alloc(_size) t4_alloc_mem((_size))
|
||||
#define t4_os_free(_ptr) t4_free_mem((_ptr))
|
||||
|
||||
void t4_os_portmod_changed(const struct adapter *adap, int port_id);
|
||||
void t4_os_link_changed(struct adapter *adap, int port_id, int link_stat);
|
||||
|
||||
void reclaim_completed_tx(struct sge_txq *q);
|
||||
void t4_free_sge_resources(struct adapter *adap);
|
||||
void t4_sge_tx_monitor_start(struct adapter *adap);
|
||||
void t4_sge_tx_monitor_stop(struct adapter *adap);
|
||||
int t4_eth_xmit(struct sge_eth_txq *txq, struct rte_mbuf *mbuf);
|
||||
int t4_ethrx_handler(struct sge_rspq *q, const __be64 *rsp,
|
||||
const struct pkt_gl *gl);
|
||||
int t4_sge_init(struct adapter *adap);
|
||||
int t4_sge_alloc_eth_txq(struct adapter *adap, struct sge_eth_txq *txq,
|
||||
struct rte_eth_dev *eth_dev, uint16_t queue_id,
|
||||
unsigned int iqid, int socket_id);
|
||||
int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *rspq, bool fwevtq,
|
||||
struct rte_eth_dev *eth_dev, int intr_idx,
|
||||
struct sge_fl *fl, rspq_handler_t handler,
|
||||
int cong, struct rte_mempool *mp, int queue_id,
|
||||
int socket_id);
|
||||
int t4_sge_eth_txq_start(struct sge_eth_txq *txq);
|
||||
int t4_sge_eth_txq_stop(struct sge_eth_txq *txq);
|
||||
void t4_sge_eth_txq_release(struct adapter *adap, struct sge_eth_txq *txq);
|
||||
int t4_sge_eth_rxq_start(struct adapter *adap, struct sge_rspq *rq);
|
||||
int t4_sge_eth_rxq_stop(struct adapter *adap, struct sge_rspq *rq);
|
||||
void t4_sge_eth_rxq_release(struct adapter *adap, struct sge_eth_rxq *rxq);
|
||||
void t4_sge_eth_clear_queues(struct port_info *pi);
|
||||
int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us,
|
||||
unsigned int cnt);
|
||||
int cxgbe_poll(struct sge_rspq *q, struct rte_mbuf **rx_pkts,
|
||||
unsigned int budget, unsigned int *work_done);
|
||||
int cxgb4_write_rss(const struct port_info *pi, const u16 *queues);
|
||||
|
||||
#endif /* __T4_ADAPTER_H__ */
|
||||
401
drivers/net/cxgbe/base/common.h
Normal file
401
drivers/net/cxgbe/base/common.h
Normal file
@ -0,0 +1,401 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2014-2015 Chelsio Communications.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Chelsio Communications nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __CHELSIO_COMMON_H
|
||||
#define __CHELSIO_COMMON_H
|
||||
|
||||
#include "cxgbe_compat.h"
|
||||
#include "t4_hw.h"
|
||||
#include "t4_chip_type.h"
|
||||
#include "t4fw_interface.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PAGE_SIZE RTE_PGSIZE_4K
|
||||
|
||||
enum {
|
||||
MAX_NPORTS = 4, /* max # of ports */
|
||||
};
|
||||
|
||||
enum {
|
||||
MEMWIN0_APERTURE = 2048,
|
||||
MEMWIN0_BASE = 0x1b800,
|
||||
};
|
||||
|
||||
enum dev_master { MASTER_CANT, MASTER_MAY, MASTER_MUST };
|
||||
|
||||
enum dev_state { DEV_STATE_UNINIT, DEV_STATE_INIT, DEV_STATE_ERR };
|
||||
|
||||
enum {
|
||||
PAUSE_RX = 1 << 0,
|
||||
PAUSE_TX = 1 << 1,
|
||||
PAUSE_AUTONEG = 1 << 2
|
||||
};
|
||||
|
||||
struct port_stats {
|
||||
u64 tx_octets; /* total # of octets in good frames */
|
||||
u64 tx_frames; /* all good frames */
|
||||
u64 tx_bcast_frames; /* all broadcast frames */
|
||||
u64 tx_mcast_frames; /* all multicast frames */
|
||||
u64 tx_ucast_frames; /* all unicast frames */
|
||||
u64 tx_error_frames; /* all error frames */
|
||||
|
||||
u64 tx_frames_64; /* # of Tx frames in a particular range */
|
||||
u64 tx_frames_65_127;
|
||||
u64 tx_frames_128_255;
|
||||
u64 tx_frames_256_511;
|
||||
u64 tx_frames_512_1023;
|
||||
u64 tx_frames_1024_1518;
|
||||
u64 tx_frames_1519_max;
|
||||
|
||||
u64 tx_drop; /* # of dropped Tx frames */
|
||||
u64 tx_pause; /* # of transmitted pause frames */
|
||||
u64 tx_ppp0; /* # of transmitted PPP prio 0 frames */
|
||||
u64 tx_ppp1; /* # of transmitted PPP prio 1 frames */
|
||||
u64 tx_ppp2; /* # of transmitted PPP prio 2 frames */
|
||||
u64 tx_ppp3; /* # of transmitted PPP prio 3 frames */
|
||||
u64 tx_ppp4; /* # of transmitted PPP prio 4 frames */
|
||||
u64 tx_ppp5; /* # of transmitted PPP prio 5 frames */
|
||||
u64 tx_ppp6; /* # of transmitted PPP prio 6 frames */
|
||||
u64 tx_ppp7; /* # of transmitted PPP prio 7 frames */
|
||||
|
||||
u64 rx_octets; /* total # of octets in good frames */
|
||||
u64 rx_frames; /* all good frames */
|
||||
u64 rx_bcast_frames; /* all broadcast frames */
|
||||
u64 rx_mcast_frames; /* all multicast frames */
|
||||
u64 rx_ucast_frames; /* all unicast frames */
|
||||
u64 rx_too_long; /* # of frames exceeding MTU */
|
||||
u64 rx_jabber; /* # of jabber frames */
|
||||
u64 rx_fcs_err; /* # of received frames with bad FCS */
|
||||
u64 rx_len_err; /* # of received frames with length error */
|
||||
u64 rx_symbol_err; /* symbol errors */
|
||||
u64 rx_runt; /* # of short frames */
|
||||
|
||||
u64 rx_frames_64; /* # of Rx frames in a particular range */
|
||||
u64 rx_frames_65_127;
|
||||
u64 rx_frames_128_255;
|
||||
u64 rx_frames_256_511;
|
||||
u64 rx_frames_512_1023;
|
||||
u64 rx_frames_1024_1518;
|
||||
u64 rx_frames_1519_max;
|
||||
|
||||
u64 rx_pause; /* # of received pause frames */
|
||||
u64 rx_ppp0; /* # of received PPP prio 0 frames */
|
||||
u64 rx_ppp1; /* # of received PPP prio 1 frames */
|
||||
u64 rx_ppp2; /* # of received PPP prio 2 frames */
|
||||
u64 rx_ppp3; /* # of received PPP prio 3 frames */
|
||||
u64 rx_ppp4; /* # of received PPP prio 4 frames */
|
||||
u64 rx_ppp5; /* # of received PPP prio 5 frames */
|
||||
u64 rx_ppp6; /* # of received PPP prio 6 frames */
|
||||
u64 rx_ppp7; /* # of received PPP prio 7 frames */
|
||||
|
||||
u64 rx_ovflow0; /* drops due to buffer-group 0 overflows */
|
||||
u64 rx_ovflow1; /* drops due to buffer-group 1 overflows */
|
||||
u64 rx_ovflow2; /* drops due to buffer-group 2 overflows */
|
||||
u64 rx_ovflow3; /* drops due to buffer-group 3 overflows */
|
||||
u64 rx_trunc0; /* buffer-group 0 truncated packets */
|
||||
u64 rx_trunc1; /* buffer-group 1 truncated packets */
|
||||
u64 rx_trunc2; /* buffer-group 2 truncated packets */
|
||||
u64 rx_trunc3; /* buffer-group 3 truncated packets */
|
||||
};
|
||||
|
||||
struct sge_params {
|
||||
u32 hps; /* host page size for our PF/VF */
|
||||
u32 eq_qpp; /* egress queues/page for our PF/VF */
|
||||
u32 iq_qpp; /* egress queues/page for our PF/VF */
|
||||
};
|
||||
|
||||
struct tp_params {
|
||||
unsigned int ntxchan; /* # of Tx channels */
|
||||
unsigned int tre; /* log2 of core clocks per TP tick */
|
||||
unsigned int dack_re; /* DACK timer resolution */
|
||||
unsigned int la_mask; /* what events are recorded by TP LA */
|
||||
unsigned short tx_modq[NCHAN]; /* channel to modulation queue map */
|
||||
|
||||
u32 vlan_pri_map; /* cached TP_VLAN_PRI_MAP */
|
||||
u32 ingress_config; /* cached TP_INGRESS_CONFIG */
|
||||
|
||||
/*
|
||||
* TP_VLAN_PRI_MAP Compressed Filter Tuple field offsets. This is a
|
||||
* subset of the set of fields which may be present in the Compressed
|
||||
* Filter Tuple portion of filters and TCP TCB connections. The
|
||||
* fields which are present are controlled by the TP_VLAN_PRI_MAP.
|
||||
* Since a variable number of fields may or may not be present, their
|
||||
* shifted field positions within the Compressed Filter Tuple may
|
||||
* vary, or not even be present if the field isn't selected in
|
||||
* TP_VLAN_PRI_MAP. Since some of these fields are needed in various
|
||||
* places we store their offsets here, or a -1 if the field isn't
|
||||
* present.
|
||||
*/
|
||||
int vlan_shift;
|
||||
int vnic_shift;
|
||||
int port_shift;
|
||||
int protocol_shift;
|
||||
};
|
||||
|
||||
struct vpd_params {
|
||||
unsigned int cclk;
|
||||
};
|
||||
|
||||
struct pci_params {
|
||||
uint16_t vendor_id;
|
||||
uint16_t device_id;
|
||||
uint32_t vpd_cap_addr;
|
||||
uint16_t speed;
|
||||
uint8_t width;
|
||||
};
|
||||
|
||||
/*
|
||||
* Firmware device log.
|
||||
*/
|
||||
struct devlog_params {
|
||||
u32 memtype; /* which memory (EDC0, EDC1, MC) */
|
||||
u32 start; /* start of log in firmware memory */
|
||||
u32 size; /* size of log */
|
||||
};
|
||||
|
||||
struct arch_specific_params {
|
||||
u8 nchan;
|
||||
u16 mps_rplc_size;
|
||||
u16 vfcount;
|
||||
u32 sge_fl_db;
|
||||
u16 mps_tcam_size;
|
||||
};
|
||||
|
||||
struct adapter_params {
|
||||
struct sge_params sge;
|
||||
struct tp_params tp;
|
||||
struct vpd_params vpd;
|
||||
struct pci_params pci;
|
||||
struct devlog_params devlog;
|
||||
enum pcie_memwin drv_memwin;
|
||||
|
||||
unsigned int sf_size; /* serial flash size in bytes */
|
||||
unsigned int sf_nsec; /* # of flash sectors */
|
||||
|
||||
unsigned int fw_vers;
|
||||
unsigned int tp_vers;
|
||||
|
||||
unsigned short mtus[NMTUS];
|
||||
unsigned short a_wnd[NCCTRL_WIN];
|
||||
unsigned short b_wnd[NCCTRL_WIN];
|
||||
|
||||
unsigned int mc_size; /* MC memory size */
|
||||
unsigned int cim_la_size;
|
||||
|
||||
unsigned char nports; /* # of ethernet ports */
|
||||
unsigned char portvec;
|
||||
|
||||
enum chip_type chip; /* chip code */
|
||||
struct arch_specific_params arch; /* chip specific params */
|
||||
|
||||
bool ulptx_memwrite_dsgl; /* use of T5 DSGL allowed */
|
||||
};
|
||||
|
||||
struct link_config {
|
||||
unsigned short supported; /* link capabilities */
|
||||
unsigned short advertising; /* advertised capabilities */
|
||||
unsigned short requested_speed; /* speed user has requested */
|
||||
unsigned short speed; /* actual link speed */
|
||||
unsigned char requested_fc; /* flow control user has requested */
|
||||
unsigned char fc; /* actual link flow control */
|
||||
unsigned char autoneg; /* autonegotiating? */
|
||||
unsigned char link_ok; /* link up? */
|
||||
};
|
||||
|
||||
#include "adapter.h"
|
||||
|
||||
void t4_set_reg_field(struct adapter *adap, unsigned int addr, u32 mask,
|
||||
u32 val);
|
||||
int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
|
||||
int polarity,
|
||||
int attempts, int delay, u32 *valp);
|
||||
|
||||
static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
|
||||
int polarity, int attempts, int delay)
|
||||
{
|
||||
return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
|
||||
delay, NULL);
|
||||
}
|
||||
|
||||
#define for_each_port(adapter, iter) \
|
||||
for (iter = 0; iter < (adapter)->params.nports; ++iter)
|
||||
|
||||
void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log);
|
||||
void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
|
||||
unsigned int mask, unsigned int val);
|
||||
void t4_intr_enable(struct adapter *adapter);
|
||||
void t4_intr_disable(struct adapter *adapter);
|
||||
int t4_link_l1cfg(struct adapter *adap, unsigned int mbox, unsigned int port,
|
||||
struct link_config *lc);
|
||||
void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
|
||||
const unsigned short *alpha, const unsigned short *beta);
|
||||
int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
|
||||
enum dev_master master, enum dev_state *state);
|
||||
int t4_fw_bye(struct adapter *adap, unsigned int mbox);
|
||||
int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset);
|
||||
int t4_fw_halt(struct adapter *adap, unsigned int mbox, int reset);
|
||||
int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset);
|
||||
int t4_fixup_host_params_compat(struct adapter *adap, unsigned int page_size,
|
||||
unsigned int cache_line_size,
|
||||
enum chip_type chip_compat);
|
||||
int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
|
||||
unsigned int cache_line_size);
|
||||
int t4_fw_initialize(struct adapter *adap, unsigned int mbox);
|
||||
int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int nparams, const u32 *params,
|
||||
u32 *val);
|
||||
int t4_set_params_timeout(struct adapter *adap, unsigned int mbox,
|
||||
unsigned int pf, unsigned int vf,
|
||||
unsigned int nparams, const u32 *params,
|
||||
const u32 *val, int timeout);
|
||||
int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int nparams, const u32 *params,
|
||||
const u32 *val);
|
||||
int t4_alloc_vi_func(struct adapter *adap, unsigned int mbox,
|
||||
unsigned int port, unsigned int pf, unsigned int vf,
|
||||
unsigned int nmac, u8 *mac, unsigned int *rss_size,
|
||||
unsigned int portfunc, unsigned int idstype);
|
||||
int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
|
||||
unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
|
||||
unsigned int *rss_size);
|
||||
int t4_free_vi(struct adapter *adap, unsigned int mbox,
|
||||
unsigned int pf, unsigned int vf,
|
||||
unsigned int viid);
|
||||
int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
||||
int mtu, int promisc, int all_multi, int bcast, int vlanex,
|
||||
bool sleep_ok);
|
||||
int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
||||
int idx, const u8 *addr, bool persist, bool add_smt);
|
||||
int t4_enable_vi_params(struct adapter *adap, unsigned int mbox,
|
||||
unsigned int viid, bool rx_en, bool tx_en, bool dcb_en);
|
||||
int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
|
||||
bool rx_en, bool tx_en);
|
||||
int t4_iq_start_stop(struct adapter *adap, unsigned int mbox, bool start,
|
||||
unsigned int pf, unsigned int vf, unsigned int iqid,
|
||||
unsigned int fl0id, unsigned int fl1id);
|
||||
int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int iqtype, unsigned int iqid,
|
||||
unsigned int fl0id, unsigned int fl1id);
|
||||
int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
|
||||
unsigned int vf, unsigned int eqid);
|
||||
|
||||
static inline unsigned int core_ticks_per_usec(const struct adapter *adap)
|
||||
{
|
||||
return adap->params.vpd.cclk / 1000;
|
||||
}
|
||||
|
||||
static inline unsigned int us_to_core_ticks(const struct adapter *adap,
|
||||
unsigned int us)
|
||||
{
|
||||
return (us * adap->params.vpd.cclk) / 1000;
|
||||
}
|
||||
|
||||
static inline unsigned int core_ticks_to_us(const struct adapter *adapter,
|
||||
unsigned int ticks)
|
||||
{
|
||||
/* add Core Clock / 2 to round ticks to nearest uS */
|
||||
return ((ticks * 1000 + adapter->params.vpd.cclk / 2) /
|
||||
adapter->params.vpd.cclk);
|
||||
}
|
||||
|
||||
int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
|
||||
int size, void *rpl, bool sleep_ok, int timeout);
|
||||
int t4_wr_mbox_meat(struct adapter *adap, int mbox,
|
||||
const void __attribute__((__may_alias__)) *cmd, int size,
|
||||
void *rpl, bool sleep_ok);
|
||||
|
||||
static inline int t4_wr_mbox_timeout(struct adapter *adap, int mbox,
|
||||
const void *cmd, int size, void *rpl,
|
||||
int timeout)
|
||||
{
|
||||
return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, true,
|
||||
timeout);
|
||||
}
|
||||
|
||||
int t4_get_core_clock(struct adapter *adapter, struct vpd_params *p);
|
||||
|
||||
static inline int t4_wr_mbox(struct adapter *adap, int mbox, const void *cmd,
|
||||
int size, void *rpl)
|
||||
{
|
||||
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, true);
|
||||
}
|
||||
|
||||
static inline int t4_wr_mbox_ns(struct adapter *adap, int mbox, const void *cmd,
|
||||
int size, void *rpl)
|
||||
{
|
||||
return t4_wr_mbox_meat(adap, mbox, cmd, size, rpl, false);
|
||||
}
|
||||
|
||||
void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
|
||||
unsigned int data_reg, u32 *vals, unsigned int nregs,
|
||||
unsigned int start_idx);
|
||||
void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
|
||||
unsigned int data_reg, const u32 *vals,
|
||||
unsigned int nregs, unsigned int start_idx);
|
||||
|
||||
int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p);
|
||||
int t4_read_flash(struct adapter *adapter, unsigned int addr,
|
||||
unsigned int nwords, u32 *data, int byte_oriented);
|
||||
int t4_flash_cfg_addr(struct adapter *adapter);
|
||||
unsigned int t4_get_mps_bg_map(struct adapter *adapter, int idx);
|
||||
const char *t4_get_port_type_description(enum fw_port_type port_type);
|
||||
void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p);
|
||||
void t4_get_port_stats_offset(struct adapter *adap, int idx,
|
||||
struct port_stats *stats,
|
||||
struct port_stats *offset);
|
||||
void t4_clr_port_stats(struct adapter *adap, int idx);
|
||||
void t4_reset_link_config(struct adapter *adap, int idx);
|
||||
int t4_get_fw_version(struct adapter *adapter, u32 *vers);
|
||||
int t4_get_tp_version(struct adapter *adapter, u32 *vers);
|
||||
int t4_get_flash_params(struct adapter *adapter);
|
||||
int t4_prep_adapter(struct adapter *adapter);
|
||||
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
|
||||
int t4_init_rss_mode(struct adapter *adap, int mbox);
|
||||
int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
|
||||
int start, int n, const u16 *rspq, unsigned int nrspq);
|
||||
int t4_config_vi_rss(struct adapter *adapter, int mbox, unsigned int viid,
|
||||
unsigned int flags, unsigned int defq);
|
||||
|
||||
enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
|
||||
int t4_bar2_sge_qregs(struct adapter *adapter, unsigned int qid,
|
||||
unsigned int qtype, u64 *pbar2_qoffset,
|
||||
unsigned int *pbar2_qid);
|
||||
|
||||
int t4_init_sge_params(struct adapter *adapter);
|
||||
int t4_init_tp_params(struct adapter *adap);
|
||||
int t4_filter_field_shift(const struct adapter *adap, unsigned int filter_sel);
|
||||
int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl);
|
||||
#endif /* __CHELSIO_COMMON_H */
|
||||
79
drivers/net/cxgbe/base/t4_chip_type.h
Normal file
79
drivers/net/cxgbe/base/t4_chip_type.h
Normal file
@ -0,0 +1,79 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2014-2015 Chelsio Communications.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Chelsio Communications nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __T4_CHIP_TYPE_H__
|
||||
#define __T4_CHIP_TYPE_H__
|
||||
|
||||
/*
|
||||
* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
|
||||
*
|
||||
* V = "4" for T4; "5" for T5, etc. or
|
||||
* F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
|
||||
* PP = adapter product designation
|
||||
*
|
||||
* We use the "version" (V) of the adpater to code the Chip Version above.
|
||||
*/
|
||||
#define CHELSIO_PCI_ID_VER(devid) ((devid) >> 12)
|
||||
#define CHELSIO_PCI_ID_FUNC(devid) (((devid) >> 8) & 0xf)
|
||||
#define CHELSIO_PCI_ID_PROD(devid) ((devid) & 0xff)
|
||||
|
||||
#define CHELSIO_T4 0x4
|
||||
#define CHELSIO_T5 0x5
|
||||
|
||||
#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
|
||||
#define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
|
||||
#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
|
||||
|
||||
enum chip_type {
|
||||
T4_A1 = CHELSIO_CHIP_CODE(CHELSIO_T4, 1),
|
||||
T4_A2 = CHELSIO_CHIP_CODE(CHELSIO_T4, 2),
|
||||
T4_FIRST_REV = T4_A1,
|
||||
T4_LAST_REV = T4_A2,
|
||||
|
||||
T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
|
||||
T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
|
||||
T5_FIRST_REV = T5_A0,
|
||||
T5_LAST_REV = T5_A1,
|
||||
};
|
||||
|
||||
static inline int is_t4(enum chip_type chip)
|
||||
{
|
||||
return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T4);
|
||||
}
|
||||
|
||||
static inline int is_t5(enum chip_type chip)
|
||||
{
|
||||
return (CHELSIO_CHIP_VERSION(chip) == CHELSIO_T5);
|
||||
}
|
||||
|
||||
#endif /* __T4_CHIP_TYPE_H__ */
|
||||
2686
drivers/net/cxgbe/base/t4_hw.c
Normal file
2686
drivers/net/cxgbe/base/t4_hw.c
Normal file
File diff suppressed because it is too large
Load Diff
149
drivers/net/cxgbe/base/t4_hw.h
Normal file
149
drivers/net/cxgbe/base/t4_hw.h
Normal file
@ -0,0 +1,149 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2014-2015 Chelsio Communications.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Chelsio Communications nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __T4_HW_H
|
||||
#define __T4_HW_H
|
||||
|
||||
enum {
|
||||
NCHAN = 4, /* # of HW channels */
|
||||
NMTUS = 16, /* size of MTU table */
|
||||
NCCTRL_WIN = 32, /* # of congestion control windows */
|
||||
MBOX_LEN = 64, /* mailbox size in bytes */
|
||||
UDBS_SEG_SIZE = 128, /* segment size for BAR2 user doorbells */
|
||||
};
|
||||
|
||||
enum {
|
||||
CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
|
||||
};
|
||||
|
||||
enum {
|
||||
SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
|
||||
};
|
||||
|
||||
enum {
|
||||
SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
|
||||
SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
|
||||
};
|
||||
|
||||
/* PCI-e memory window access */
|
||||
enum pcie_memwin {
|
||||
MEMWIN_NIC = 0,
|
||||
};
|
||||
|
||||
enum {
|
||||
SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
|
||||
SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */
|
||||
/* max no. of desc allowed in WR */
|
||||
SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / SGE_EQ_IDXSIZE,
|
||||
};
|
||||
|
||||
struct sge_qstat { /* data written to SGE queue status entries */
|
||||
__be32 qid;
|
||||
__be16 cidx;
|
||||
__be16 pidx;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure for last 128 bits of response descriptors
|
||||
*/
|
||||
struct rsp_ctrl {
|
||||
__be32 hdrbuflen_pidx;
|
||||
__be32 pldbuflen_qid;
|
||||
union {
|
||||
u8 type_gen;
|
||||
__be64 last_flit;
|
||||
} u;
|
||||
};
|
||||
|
||||
#define S_RSPD_NEWBUF 31
|
||||
#define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
|
||||
#define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
|
||||
|
||||
#define S_RSPD_LEN 0
|
||||
#define M_RSPD_LEN 0x7fffffff
|
||||
#define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
|
||||
#define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
|
||||
|
||||
#define S_RSPD_GEN 7
|
||||
#define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
|
||||
#define F_RSPD_GEN V_RSPD_GEN(1U)
|
||||
|
||||
#define S_RSPD_TYPE 4
|
||||
#define M_RSPD_TYPE 0x3
|
||||
#define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
|
||||
#define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
|
||||
|
||||
/* Rx queue interrupt deferral field: timer index */
|
||||
#define S_QINTR_CNT_EN 0
|
||||
#define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
|
||||
#define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
|
||||
|
||||
#define S_QINTR_TIMER_IDX 1
|
||||
#define M_QINTR_TIMER_IDX 0x7
|
||||
#define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
|
||||
#define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
|
||||
|
||||
/*
|
||||
* Flash layout.
|
||||
*/
|
||||
#define FLASH_START(start) ((start) * SF_SEC_SIZE)
|
||||
#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
|
||||
|
||||
enum {
|
||||
/*
|
||||
* Location of firmware image in FLASH.
|
||||
*/
|
||||
FLASH_FW_START_SEC = 8,
|
||||
FLASH_FW_NSECS = 16,
|
||||
FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
|
||||
FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
|
||||
|
||||
/*
|
||||
* Location of Firmware Configuration File in FLASH.
|
||||
*/
|
||||
FLASH_CFG_START_SEC = 31,
|
||||
FLASH_CFG_NSECS = 1,
|
||||
FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
|
||||
FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
|
||||
|
||||
/*
|
||||
* We don't support FLASH devices which can't support the full
|
||||
* standard set of sections which we need for normal operations.
|
||||
*/
|
||||
FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
|
||||
};
|
||||
|
||||
#undef FLASH_START
|
||||
#undef FLASH_MAX_SIZE
|
||||
|
||||
#endif /* __T4_HW_H */
|
||||
345
drivers/net/cxgbe/base/t4_msg.h
Normal file
345
drivers/net/cxgbe/base/t4_msg.h
Normal file
@ -0,0 +1,345 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2014-2015 Chelsio Communications.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Chelsio Communications nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef T4_MSG_H
|
||||
#define T4_MSG_H
|
||||
|
||||
enum {
|
||||
CPL_SGE_EGR_UPDATE = 0xA5,
|
||||
CPL_FW4_MSG = 0xC0,
|
||||
CPL_FW6_MSG = 0xE0,
|
||||
CPL_TX_PKT_LSO = 0xED,
|
||||
CPL_TX_PKT_XT = 0xEE,
|
||||
};
|
||||
|
||||
enum { /* TX_PKT_XT checksum types */
|
||||
TX_CSUM_TCPIP = 8,
|
||||
TX_CSUM_UDPIP = 9,
|
||||
TX_CSUM_TCPIP6 = 10,
|
||||
};
|
||||
|
||||
union opcode_tid {
|
||||
__be32 opcode_tid;
|
||||
__u8 opcode;
|
||||
};
|
||||
|
||||
struct rss_header {
|
||||
__u8 opcode;
|
||||
#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
|
||||
__u8 channel:2;
|
||||
__u8 filter_hit:1;
|
||||
__u8 filter_tid:1;
|
||||
__u8 hash_type:2;
|
||||
__u8 ipv6:1;
|
||||
__u8 send2fw:1;
|
||||
#else
|
||||
__u8 send2fw:1;
|
||||
__u8 ipv6:1;
|
||||
__u8 hash_type:2;
|
||||
__u8 filter_tid:1;
|
||||
__u8 filter_hit:1;
|
||||
__u8 channel:2;
|
||||
#endif
|
||||
__be16 qid;
|
||||
__be32 hash_val;
|
||||
};
|
||||
|
||||
#if defined(RSS_HDR_VLD) || defined(CHELSIO_FW)
|
||||
#define RSS_HDR struct rss_header rss_hdr
|
||||
#else
|
||||
#define RSS_HDR
|
||||
#endif
|
||||
|
||||
#ifndef CHELSIO_FW
|
||||
struct work_request_hdr {
|
||||
__be32 wr_hi;
|
||||
__be32 wr_mid;
|
||||
__be64 wr_lo;
|
||||
};
|
||||
|
||||
#define WR_HDR struct work_request_hdr wr
|
||||
#define WR_HDR_SIZE sizeof(struct work_request_hdr)
|
||||
#else
|
||||
#define WR_HDR
|
||||
#define WR_HDR_SIZE 0
|
||||
#endif
|
||||
|
||||
struct cpl_tx_data {
|
||||
union opcode_tid ot;
|
||||
__be32 len;
|
||||
__be32 rsvd;
|
||||
__be32 flags;
|
||||
};
|
||||
|
||||
struct cpl_tx_pkt_core {
|
||||
__be32 ctrl0;
|
||||
__be16 pack;
|
||||
__be16 len;
|
||||
__be64 ctrl1;
|
||||
};
|
||||
|
||||
struct cpl_tx_pkt {
|
||||
WR_HDR;
|
||||
struct cpl_tx_pkt_core c;
|
||||
};
|
||||
|
||||
/* cpl_tx_pkt_core.ctrl0 fields */
|
||||
#define S_TXPKT_PF 8
|
||||
#define M_TXPKT_PF 0x7
|
||||
#define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
|
||||
#define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
|
||||
|
||||
#define S_TXPKT_INTF 16
|
||||
#define M_TXPKT_INTF 0xF
|
||||
#define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
|
||||
#define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
|
||||
|
||||
#define S_TXPKT_OPCODE 24
|
||||
#define M_TXPKT_OPCODE 0xFF
|
||||
#define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
|
||||
#define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
|
||||
|
||||
/* cpl_tx_pkt_core.ctrl1 fields */
|
||||
#define S_TXPKT_IPHDR_LEN 20
|
||||
#define M_TXPKT_IPHDR_LEN 0x3FFF
|
||||
#define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
|
||||
#define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
|
||||
|
||||
#define S_TXPKT_ETHHDR_LEN 34
|
||||
#define M_TXPKT_ETHHDR_LEN 0x3F
|
||||
#define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
|
||||
#define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
|
||||
|
||||
#define S_T6_TXPKT_ETHHDR_LEN 32
|
||||
#define M_T6_TXPKT_ETHHDR_LEN 0xFF
|
||||
#define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
|
||||
#define G_T6_TXPKT_ETHHDR_LEN(x) \
|
||||
(((x) >> S_T6_TXPKT_ETHHDR_LEN) & M_T6_TXPKT_ETHHDR_LEN)
|
||||
|
||||
#define S_TXPKT_CSUM_TYPE 40
|
||||
#define M_TXPKT_CSUM_TYPE 0xF
|
||||
#define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
|
||||
#define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
|
||||
|
||||
#define S_TXPKT_VLAN 44
|
||||
#define M_TXPKT_VLAN 0xFFFF
|
||||
#define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
|
||||
#define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
|
||||
|
||||
#define S_TXPKT_VLAN_VLD 60
|
||||
#define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
|
||||
#define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
|
||||
|
||||
#define S_TXPKT_IPCSUM_DIS 62
|
||||
#define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
|
||||
#define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
|
||||
|
||||
#define S_TXPKT_L4CSUM_DIS 63
|
||||
#define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
|
||||
#define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
|
||||
|
||||
struct cpl_tx_pkt_lso_core {
|
||||
__be32 lso_ctrl;
|
||||
__be16 ipid_ofst;
|
||||
__be16 mss;
|
||||
__be32 seqno_offset;
|
||||
__be32 len;
|
||||
/* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
|
||||
};
|
||||
|
||||
struct cpl_tx_pkt_lso {
|
||||
WR_HDR;
|
||||
struct cpl_tx_pkt_lso_core c;
|
||||
/* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
|
||||
};
|
||||
|
||||
/* cpl_tx_pkt_lso_core.lso_ctrl fields */
|
||||
#define S_LSO_TCPHDR_LEN 0
|
||||
#define M_LSO_TCPHDR_LEN 0xF
|
||||
#define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
|
||||
#define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
|
||||
|
||||
#define S_LSO_IPHDR_LEN 4
|
||||
#define M_LSO_IPHDR_LEN 0xFFF
|
||||
#define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
|
||||
#define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
|
||||
|
||||
#define S_LSO_ETHHDR_LEN 16
|
||||
#define M_LSO_ETHHDR_LEN 0xF
|
||||
#define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
|
||||
#define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
|
||||
|
||||
#define S_LSO_IPV6 20
|
||||
#define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
|
||||
#define F_LSO_IPV6 V_LSO_IPV6(1U)
|
||||
|
||||
#define S_LSO_LAST_SLICE 22
|
||||
#define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
|
||||
#define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
|
||||
|
||||
#define S_LSO_FIRST_SLICE 23
|
||||
#define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
|
||||
#define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
|
||||
|
||||
#define S_LSO_OPCODE 24
|
||||
#define M_LSO_OPCODE 0xFF
|
||||
#define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
|
||||
#define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
|
||||
|
||||
#define S_LSO_T5_XFER_SIZE 0
|
||||
#define M_LSO_T5_XFER_SIZE 0xFFFFFFF
|
||||
#define V_LSO_T5_XFER_SIZE(x) ((x) << S_LSO_T5_XFER_SIZE)
|
||||
#define G_LSO_T5_XFER_SIZE(x) (((x) >> S_LSO_T5_XFER_SIZE) & M_LSO_T5_XFER_SIZE)
|
||||
|
||||
struct cpl_rx_pkt {
|
||||
RSS_HDR;
|
||||
__u8 opcode;
|
||||
#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
|
||||
__u8 iff:4;
|
||||
__u8 csum_calc:1;
|
||||
__u8 ipmi_pkt:1;
|
||||
__u8 vlan_ex:1;
|
||||
__u8 ip_frag:1;
|
||||
#else
|
||||
__u8 ip_frag:1;
|
||||
__u8 vlan_ex:1;
|
||||
__u8 ipmi_pkt:1;
|
||||
__u8 csum_calc:1;
|
||||
__u8 iff:4;
|
||||
#endif
|
||||
__be16 csum;
|
||||
__be16 vlan;
|
||||
__be16 len;
|
||||
__be32 l2info;
|
||||
__be16 hdr_len;
|
||||
__be16 err_vec;
|
||||
};
|
||||
|
||||
/* rx_pkt.l2info fields */
|
||||
#define S_RXF_UDP 22
|
||||
#define V_RXF_UDP(x) ((x) << S_RXF_UDP)
|
||||
#define F_RXF_UDP V_RXF_UDP(1U)
|
||||
|
||||
#define S_RXF_TCP 23
|
||||
#define V_RXF_TCP(x) ((x) << S_RXF_TCP)
|
||||
#define F_RXF_TCP V_RXF_TCP(1U)
|
||||
|
||||
#define S_RXF_IP 24
|
||||
#define V_RXF_IP(x) ((x) << S_RXF_IP)
|
||||
#define F_RXF_IP V_RXF_IP(1U)
|
||||
|
||||
#define S_RXF_IP6 25
|
||||
#define V_RXF_IP6(x) ((x) << S_RXF_IP6)
|
||||
#define F_RXF_IP6 V_RXF_IP6(1U)
|
||||
|
||||
/* cpl_fw*.type values */
|
||||
enum {
|
||||
FW_TYPE_RSSCPL = 4,
|
||||
};
|
||||
|
||||
struct cpl_fw4_msg {
|
||||
RSS_HDR;
|
||||
u8 opcode;
|
||||
u8 type;
|
||||
__be16 rsvd0;
|
||||
__be32 rsvd1;
|
||||
__be64 data[2];
|
||||
};
|
||||
|
||||
struct cpl_fw6_msg {
|
||||
RSS_HDR;
|
||||
u8 opcode;
|
||||
u8 type;
|
||||
__be16 rsvd0;
|
||||
__be32 rsvd1;
|
||||
__be64 data[4];
|
||||
};
|
||||
|
||||
enum {
|
||||
ULP_TX_SC_IMM = 0x81,
|
||||
ULP_TX_SC_DSGL = 0x82,
|
||||
ULP_TX_SC_ISGL = 0x83
|
||||
};
|
||||
|
||||
#define S_ULPTX_CMD 24
|
||||
#define M_ULPTX_CMD 0xFF
|
||||
#define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
|
||||
|
||||
#define S_ULP_TX_SC_MORE 23
|
||||
#define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
|
||||
#define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
|
||||
|
||||
struct ulptx_sge_pair {
|
||||
__be32 len[2];
|
||||
__be64 addr[2];
|
||||
};
|
||||
|
||||
struct ulptx_sgl {
|
||||
__be32 cmd_nsge;
|
||||
__be32 len0;
|
||||
__be64 addr0;
|
||||
|
||||
#if !(defined C99_NOT_SUPPORTED)
|
||||
struct ulptx_sge_pair sge[0];
|
||||
#endif
|
||||
|
||||
};
|
||||
|
||||
struct ulptx_idata {
|
||||
__be32 cmd_more;
|
||||
__be32 len;
|
||||
};
|
||||
|
||||
#define S_ULPTX_NSGE 0
|
||||
#define M_ULPTX_NSGE 0xFFFF
|
||||
#define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
|
||||
|
||||
struct ulp_txpkt {
|
||||
__be32 cmd_dest;
|
||||
__be32 len;
|
||||
};
|
||||
|
||||
/* ulp_txpkt.cmd_dest fields */
|
||||
#define S_ULP_TXPKT_DEST 16
|
||||
#define M_ULP_TXPKT_DEST 0x3
|
||||
#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
|
||||
|
||||
#define S_ULP_TXPKT_FID 4
|
||||
#define M_ULP_TXPKT_FID 0x7ff
|
||||
#define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
|
||||
|
||||
#define S_ULP_TXPKT_RO 3
|
||||
#define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
|
||||
#define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
|
||||
|
||||
#endif /* T4_MSG_H */
|
||||
148
drivers/net/cxgbe/base/t4_pci_id_tbl.h
Normal file
148
drivers/net/cxgbe/base/t4_pci_id_tbl.h
Normal file
@ -0,0 +1,148 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2014-2015 Chelsio Communications.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Chelsio Communications nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __T4_PCI_ID_TBL_H__
|
||||
#define __T4_PCI_ID_TBL_H__
|
||||
|
||||
/*
|
||||
* The Os-Dependent code can defined cpp macros for creating a PCI Device ID
|
||||
* Table. This is useful because it allows the PCI ID Table to be maintained
|
||||
* in a single place and all supporting OSes to get new PCI Device IDs
|
||||
* automatically.
|
||||
*
|
||||
* The macros are:
|
||||
*
|
||||
* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
|
||||
* -- Used to start the definition of the PCI ID Table.
|
||||
*
|
||||
* CH_PCI_DEVICE_ID_FUNCTION
|
||||
* -- The PCI Function Number to use in the PCI Device ID Table. "0"
|
||||
* -- for drivers attaching to PF0-3, "4" for drivers attaching to PF4,
|
||||
* -- "8" for drivers attaching to SR-IOV Virtual Functions, etc.
|
||||
*
|
||||
* CH_PCI_DEVICE_ID_FUNCTION2 [optional]
|
||||
* -- If defined, create a PCI Device ID Table with both
|
||||
* -- CH_PCI_DEVICE_ID_FUNCTION and CH_PCI_DEVICE_ID_FUNCTION2 populated.
|
||||
*
|
||||
* CH_PCI_ID_TABLE_ENTRY(DeviceID)
|
||||
* -- Used for the individual PCI Device ID entries. Note that we will
|
||||
* -- be adding a trailing comma (",") after all of the entries (and
|
||||
* -- between the pairs of entries if CH_PCI_DEVICE_ID_FUNCTION2 is defined).
|
||||
*
|
||||
* CH_PCI_DEVICE_ID_TABLE_DEFINE_END
|
||||
* -- Used to finish the definition of the PCI ID Table. Note that we
|
||||
* -- will be adding a trailing semi-colon (";") here.
|
||||
*
|
||||
* CH_PCI_DEVICE_ID_BYPASS_SUPPORTED [optional]
|
||||
* -- If defined, indicates that the OS Driver has support for Bypass
|
||||
* -- Adapters.
|
||||
*/
|
||||
#ifdef CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
|
||||
|
||||
/*
|
||||
* Some sanity checks ...
|
||||
*/
|
||||
#ifndef CH_PCI_DEVICE_ID_FUNCTION
|
||||
#error CH_PCI_DEVICE_ID_FUNCTION not defined!
|
||||
#endif
|
||||
#ifndef CH_PCI_ID_TABLE_ENTRY
|
||||
#error CH_PCI_ID_TABLE_ENTRY not defined!
|
||||
#endif
|
||||
#ifndef CH_PCI_DEVICE_ID_TABLE_DEFINE_END
|
||||
#error CH_PCI_DEVICE_ID_TABLE_DEFINE_END not defined!
|
||||
#endif
|
||||
|
||||
/*
|
||||
* T4 and later ASICs use a PCI Device ID scheme of 0xVFPP where:
|
||||
*
|
||||
* V = "4" for T4; "5" for T5, etc.
|
||||
* F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
|
||||
* PP = adapter product designation
|
||||
*
|
||||
* We use this consistency in order to create the proper PCI Device IDs
|
||||
* for the specified CH_PCI_DEVICE_ID_FUNCTION.
|
||||
*/
|
||||
#ifndef CH_PCI_DEVICE_ID_FUNCTION2
|
||||
#define CH_PCI_ID_TABLE_FENTRY(devid) \
|
||||
CH_PCI_ID_TABLE_ENTRY((devid) | \
|
||||
((CH_PCI_DEVICE_ID_FUNCTION) << 8))
|
||||
#else
|
||||
#define CH_PCI_ID_TABLE_FENTRY(devid) \
|
||||
CH_PCI_ID_TABLE_ENTRY((devid) | \
|
||||
((CH_PCI_DEVICE_ID_FUNCTION) << 8)), \
|
||||
CH_PCI_ID_TABLE_ENTRY((devid) | \
|
||||
((CH_PCI_DEVICE_ID_FUNCTION2) << 8))
|
||||
#endif
|
||||
|
||||
CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN
|
||||
/*
|
||||
* T5 adapters:
|
||||
*/
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5000), /* T580-dbg */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5001), /* T520-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5002), /* T522-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5003), /* T540-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5004), /* T520-bch */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5005), /* T540-bch */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5006), /* T540-ch */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5007), /* T520-so */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5008), /* T520-cx */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5009), /* T520-bt */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x500a), /* T504-bt */
|
||||
#ifdef CH_PCI_DEVICE_ID_BYPASS_SUPPORTED
|
||||
CH_PCI_ID_TABLE_FENTRY(0x500b), /* B520-sr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x500c), /* B504-bt */
|
||||
#endif
|
||||
CH_PCI_ID_TABLE_FENTRY(0x500d), /* T580-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x500e), /* T540-LP-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5010), /* T580-LP-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5011), /* T520-LL-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5012), /* T560-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5013), /* T580-chr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5014), /* T580-so */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5015), /* T502-bt */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5080), /* Custom T540-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5081), /* Custom T540-LL-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5082), /* Custom T504-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5083), /* Custom T540-LP-CR */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5084), /* Custom T580-cr */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5085), /* Custom 3x T580-CR */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5086), /* Custom 2x T580-CR */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5087), /* Custom T580-CR */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5088), /* Custom T570-CR */
|
||||
CH_PCI_ID_TABLE_FENTRY(0x5089), /* Custom T520-CR */
|
||||
CH_PCI_DEVICE_ID_TABLE_DEFINE_END;
|
||||
|
||||
#endif /* CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN */
|
||||
|
||||
#endif /* __T4_PCI_ID_TBL_H__ */
|
||||
779
drivers/net/cxgbe/base/t4_regs.h
Normal file
779
drivers/net/cxgbe/base/t4_regs.h
Normal file
@ -0,0 +1,779 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2014-2015 Chelsio Communications.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Chelsio Communications nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#define MYPF_BASE 0x1b000
|
||||
#define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
|
||||
|
||||
#define PF0_BASE 0x1e000
|
||||
#define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
|
||||
|
||||
#define PF_STRIDE 0x400
|
||||
#define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
|
||||
#define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
|
||||
|
||||
#define MYPORT_BASE 0x1c000
|
||||
#define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
|
||||
|
||||
#define PORT0_BASE 0x20000
|
||||
#define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
|
||||
|
||||
#define PORT_STRIDE 0x2000
|
||||
#define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
|
||||
#define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
|
||||
|
||||
#define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
|
||||
#define NUM_PCIE_MEM_ACCESS_INSTANCES 8
|
||||
|
||||
#define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
|
||||
#define NUM_PCIE_FW_INSTANCES 8
|
||||
|
||||
#define T5_MYPORT_BASE 0x2c000
|
||||
#define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
|
||||
|
||||
#define T5_PORT0_BASE 0x30000
|
||||
#define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
|
||||
|
||||
#define T5_PORT_STRIDE 0x4000
|
||||
#define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
|
||||
#define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
|
||||
|
||||
#define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
|
||||
#define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
|
||||
|
||||
#define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
|
||||
#define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
|
||||
|
||||
/* registers for module SGE */
|
||||
#define SGE_BASE_ADDR 0x1000
|
||||
|
||||
#define A_SGE_PF_KDOORBELL 0x0
|
||||
|
||||
#define S_QID 15
|
||||
#define M_QID 0x1ffffU
|
||||
#define V_QID(x) ((x) << S_QID)
|
||||
#define G_QID(x) (((x) >> S_QID) & M_QID)
|
||||
|
||||
#define S_DBPRIO 14
|
||||
#define V_DBPRIO(x) ((x) << S_DBPRIO)
|
||||
#define F_DBPRIO V_DBPRIO(1U)
|
||||
|
||||
#define S_PIDX 0
|
||||
#define M_PIDX 0x3fffU
|
||||
#define V_PIDX(x) ((x) << S_PIDX)
|
||||
#define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
|
||||
|
||||
#define S_DBTYPE 13
|
||||
#define V_DBTYPE(x) ((x) << S_DBTYPE)
|
||||
#define F_DBTYPE V_DBTYPE(1U)
|
||||
|
||||
#define S_PIDX_T5 0
|
||||
#define M_PIDX_T5 0x1fffU
|
||||
#define V_PIDX_T5(x) ((x) << S_PIDX_T5)
|
||||
#define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
|
||||
|
||||
#define A_SGE_PF_GTS 0x4
|
||||
|
||||
#define S_INGRESSQID 16
|
||||
#define M_INGRESSQID 0xffffU
|
||||
#define V_INGRESSQID(x) ((x) << S_INGRESSQID)
|
||||
#define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
|
||||
|
||||
#define S_SEINTARM 12
|
||||
#define V_SEINTARM(x) ((x) << S_SEINTARM)
|
||||
#define F_SEINTARM V_SEINTARM(1U)
|
||||
|
||||
#define S_CIDXINC 0
|
||||
#define M_CIDXINC 0xfffU
|
||||
#define V_CIDXINC(x) ((x) << S_CIDXINC)
|
||||
#define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
|
||||
|
||||
#define A_SGE_CONTROL 0x1008
|
||||
|
||||
#define S_RXPKTCPLMODE 18
|
||||
#define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
|
||||
#define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U)
|
||||
|
||||
#define S_EGRSTATUSPAGESIZE 17
|
||||
#define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
|
||||
#define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U)
|
||||
|
||||
#define S_PKTSHIFT 10
|
||||
#define M_PKTSHIFT 0x7U
|
||||
#define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
|
||||
#define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
|
||||
|
||||
#define S_INGPADBOUNDARY 4
|
||||
#define M_INGPADBOUNDARY 0x7U
|
||||
#define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
|
||||
#define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
|
||||
|
||||
#define A_SGE_HOST_PAGE_SIZE 0x100c
|
||||
|
||||
#define S_HOSTPAGESIZEPF7 28
|
||||
#define M_HOSTPAGESIZEPF7 0xfU
|
||||
#define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
|
||||
#define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
|
||||
|
||||
#define S_HOSTPAGESIZEPF6 24
|
||||
#define M_HOSTPAGESIZEPF6 0xfU
|
||||
#define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
|
||||
#define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
|
||||
|
||||
#define S_HOSTPAGESIZEPF5 20
|
||||
#define M_HOSTPAGESIZEPF5 0xfU
|
||||
#define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
|
||||
#define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
|
||||
|
||||
#define S_HOSTPAGESIZEPF4 16
|
||||
#define M_HOSTPAGESIZEPF4 0xfU
|
||||
#define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
|
||||
#define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
|
||||
|
||||
#define S_HOSTPAGESIZEPF3 12
|
||||
#define M_HOSTPAGESIZEPF3 0xfU
|
||||
#define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
|
||||
#define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
|
||||
|
||||
#define S_HOSTPAGESIZEPF2 8
|
||||
#define M_HOSTPAGESIZEPF2 0xfU
|
||||
#define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
|
||||
#define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
|
||||
|
||||
#define S_HOSTPAGESIZEPF1 4
|
||||
#define M_HOSTPAGESIZEPF1 0xfU
|
||||
#define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
|
||||
#define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
|
||||
|
||||
#define S_HOSTPAGESIZEPF0 0
|
||||
#define M_HOSTPAGESIZEPF0 0xfU
|
||||
#define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
|
||||
#define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
|
||||
|
||||
#define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
|
||||
|
||||
#define S_QUEUESPERPAGEPF1 4
|
||||
#define M_QUEUESPERPAGEPF1 0xfU
|
||||
#define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
|
||||
#define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
|
||||
|
||||
#define S_QUEUESPERPAGEPF0 0
|
||||
#define M_QUEUESPERPAGEPF0 0xfU
|
||||
#define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
|
||||
#define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
|
||||
|
||||
#define S_ERR_CPL_EXCEED_IQE_SIZE 22
|
||||
#define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
|
||||
#define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U)
|
||||
|
||||
#define S_ERR_INVALID_CIDX_INC 21
|
||||
#define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
|
||||
#define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U)
|
||||
|
||||
#define S_ERR_CPL_OPCODE_0 19
|
||||
#define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
|
||||
#define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U)
|
||||
|
||||
#define S_ERR_DROPPED_DB 18
|
||||
#define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
|
||||
#define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)
|
||||
|
||||
#define S_ERR_DATA_CPL_ON_HIGH_QID1 17
|
||||
#define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
|
||||
#define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
|
||||
|
||||
#define S_ERR_DATA_CPL_ON_HIGH_QID0 16
|
||||
#define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
|
||||
#define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
|
||||
|
||||
#define S_ERR_BAD_DB_PIDX3 15
|
||||
#define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
|
||||
#define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U)
|
||||
|
||||
#define S_ERR_BAD_DB_PIDX2 14
|
||||
#define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
|
||||
#define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U)
|
||||
|
||||
#define S_ERR_BAD_DB_PIDX1 13
|
||||
#define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
|
||||
#define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U)
|
||||
|
||||
#define S_ERR_BAD_DB_PIDX0 12
|
||||
#define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
|
||||
#define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U)
|
||||
|
||||
#define S_ERR_ING_PCIE_CHAN 11
|
||||
#define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
|
||||
#define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U)
|
||||
|
||||
#define S_ERR_ING_CTXT_PRIO 10
|
||||
#define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
|
||||
#define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U)
|
||||
|
||||
#define S_ERR_EGR_CTXT_PRIO 9
|
||||
#define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
|
||||
#define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U)
|
||||
|
||||
#define S_DBFIFO_HP_INT 8
|
||||
#define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
|
||||
#define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)
|
||||
|
||||
#define S_DBFIFO_LP_INT 7
|
||||
#define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
|
||||
#define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)
|
||||
|
||||
#define S_INGRESS_SIZE_ERR 5
|
||||
#define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
|
||||
#define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U)
|
||||
|
||||
#define S_EGRESS_SIZE_ERR 4
|
||||
#define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
|
||||
#define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U)
|
||||
|
||||
#define A_SGE_INT_ENABLE3 0x1040
|
||||
|
||||
#define A_SGE_FL_BUFFER_SIZE0 0x1044
|
||||
#define A_SGE_FL_BUFFER_SIZE1 0x1048
|
||||
#define A_SGE_FL_BUFFER_SIZE2 0x104c
|
||||
#define A_SGE_FL_BUFFER_SIZE3 0x1050
|
||||
|
||||
#define A_SGE_CONM_CTRL 0x1094
|
||||
|
||||
#define S_EGRTHRESHOLD 8
|
||||
#define M_EGRTHRESHOLD 0x3fU
|
||||
#define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
|
||||
#define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
|
||||
|
||||
#define S_EGRTHRESHOLDPACKING 14
|
||||
#define M_EGRTHRESHOLDPACKING 0x3fU
|
||||
#define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
|
||||
#define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & \
|
||||
M_EGRTHRESHOLDPACKING)
|
||||
|
||||
#define S_INGTHRESHOLD 2
|
||||
#define M_INGTHRESHOLD 0x3fU
|
||||
#define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
|
||||
#define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
|
||||
|
||||
#define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
|
||||
|
||||
#define S_THRESHOLD_0 24
|
||||
#define M_THRESHOLD_0 0x3fU
|
||||
#define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
|
||||
#define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
|
||||
|
||||
#define S_THRESHOLD_1 16
|
||||
#define M_THRESHOLD_1 0x3fU
|
||||
#define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
|
||||
#define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
|
||||
|
||||
#define S_THRESHOLD_2 8
|
||||
#define M_THRESHOLD_2 0x3fU
|
||||
#define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
|
||||
#define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
|
||||
|
||||
#define S_THRESHOLD_3 0
|
||||
#define M_THRESHOLD_3 0x3fU
|
||||
#define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
|
||||
#define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
|
||||
|
||||
#define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
|
||||
|
||||
#define S_TIMERVALUE0 16
|
||||
#define M_TIMERVALUE0 0xffffU
|
||||
#define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
|
||||
#define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
|
||||
|
||||
#define S_TIMERVALUE1 0
|
||||
#define M_TIMERVALUE1 0xffffU
|
||||
#define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
|
||||
#define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
|
||||
|
||||
#define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
|
||||
|
||||
#define S_TIMERVALUE2 16
|
||||
#define M_TIMERVALUE2 0xffffU
|
||||
#define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
|
||||
#define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
|
||||
|
||||
#define S_TIMERVALUE3 0
|
||||
#define M_TIMERVALUE3 0xffffU
|
||||
#define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
|
||||
#define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
|
||||
|
||||
#define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
|
||||
|
||||
#define S_TIMERVALUE4 16
|
||||
#define M_TIMERVALUE4 0xffffU
|
||||
#define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
|
||||
#define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
|
||||
|
||||
#define S_TIMERVALUE5 0
|
||||
#define M_TIMERVALUE5 0xffffU
|
||||
#define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
|
||||
#define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
|
||||
|
||||
#define A_SGE_DEBUG_INDEX 0x10cc
|
||||
#define A_SGE_DEBUG_DATA_HIGH 0x10d0
|
||||
#define A_SGE_DEBUG_DATA_LOW 0x10d4
|
||||
#define A_SGE_STAT_CFG 0x10ec
|
||||
|
||||
#define S_STATMODE 2
|
||||
#define M_STATMODE 0x3U
|
||||
#define V_STATMODE(x) ((x) << S_STATMODE)
|
||||
#define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
|
||||
|
||||
#define S_STATSOURCE_T5 9
|
||||
#define M_STATSOURCE_T5 0xfU
|
||||
#define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
|
||||
#define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
|
||||
|
||||
#define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
|
||||
|
||||
#define A_SGE_CONTROL2 0x1124
|
||||
|
||||
#define S_INGPACKBOUNDARY 16
|
||||
#define M_INGPACKBOUNDARY 0x7U
|
||||
#define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
|
||||
#define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
|
||||
|
||||
#define S_BUSY 31
|
||||
#define V_BUSY(x) ((x) << S_BUSY)
|
||||
#define F_BUSY V_BUSY(1U)
|
||||
|
||||
#define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
|
||||
#define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
|
||||
#define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
|
||||
|
||||
/* registers for module PCIE */
|
||||
#define PCIE_BASE_ADDR 0x3000
|
||||
|
||||
#define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
|
||||
|
||||
#define S_PCIEOFST 10
|
||||
#define M_PCIEOFST 0x3fffffU
|
||||
#define V_PCIEOFST(x) ((x) << S_PCIEOFST)
|
||||
#define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
|
||||
|
||||
#define S_BIR 8
|
||||
#define M_BIR 0x3U
|
||||
#define V_BIR(x) ((x) << S_BIR)
|
||||
#define G_BIR(x) (((x) >> S_BIR) & M_BIR)
|
||||
|
||||
#define S_WINDOW 0
|
||||
#define M_WINDOW 0xffU
|
||||
#define V_WINDOW(x) ((x) << S_WINDOW)
|
||||
#define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
|
||||
|
||||
#define A_PCIE_MEM_ACCESS_OFFSET 0x306c
|
||||
|
||||
#define S_PFNUM 0
|
||||
#define M_PFNUM 0x7U
|
||||
#define V_PFNUM(x) ((x) << S_PFNUM)
|
||||
#define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
|
||||
|
||||
#define A_PCIE_FW 0x30b8
|
||||
#define A_PCIE_FW_PF 0x30bc
|
||||
|
||||
/* registers for module CIM */
|
||||
#define CIM_BASE_ADDR 0x7b00
|
||||
|
||||
#define A_CIM_PF_MAILBOX_DATA 0x240
|
||||
#define A_CIM_PF_MAILBOX_CTRL 0x280
|
||||
|
||||
#define S_MBMSGVALID 3
|
||||
#define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
|
||||
#define F_MBMSGVALID V_MBMSGVALID(1U)
|
||||
|
||||
#define S_MBOWNER 0
|
||||
#define M_MBOWNER 0x3U
|
||||
#define V_MBOWNER(x) ((x) << S_MBOWNER)
|
||||
#define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
|
||||
|
||||
#define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
|
||||
#define A_CIM_BOOT_CFG 0x7b00
|
||||
|
||||
#define S_UPCRST 0
|
||||
#define V_UPCRST(x) ((x) << S_UPCRST)
|
||||
#define F_UPCRST V_UPCRST(1U)
|
||||
|
||||
/* registers for module TP */
|
||||
#define TP_BASE_ADDR 0x7d00
|
||||
|
||||
#define A_TP_TIMER_RESOLUTION 0x7d90
|
||||
|
||||
#define S_TIMERRESOLUTION 16
|
||||
#define M_TIMERRESOLUTION 0xffU
|
||||
#define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
|
||||
#define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
|
||||
|
||||
#define S_DELAYEDACKRESOLUTION 0
|
||||
#define M_DELAYEDACKRESOLUTION 0xffU
|
||||
#define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
|
||||
#define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & \
|
||||
M_DELAYEDACKRESOLUTION)
|
||||
|
||||
#define A_TP_CCTRL_TABLE 0x7ddc
|
||||
|
||||
#define A_TP_MTU_TABLE 0x7de4
|
||||
|
||||
#define S_MTUINDEX 24
|
||||
#define M_MTUINDEX 0xffU
|
||||
#define V_MTUINDEX(x) ((x) << S_MTUINDEX)
|
||||
#define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
|
||||
|
||||
#define S_MTUWIDTH 16
|
||||
#define M_MTUWIDTH 0xfU
|
||||
#define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
|
||||
#define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
|
||||
|
||||
#define S_MTUVALUE 0
|
||||
#define M_MTUVALUE 0x3fffU
|
||||
#define V_MTUVALUE(x) ((x) << S_MTUVALUE)
|
||||
#define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
|
||||
|
||||
#define A_TP_PIO_ADDR 0x7e40
|
||||
#define A_TP_PIO_DATA 0x7e44
|
||||
|
||||
#define A_TP_VLAN_PRI_MAP 0x140
|
||||
|
||||
#define S_FRAGMENTATION 9
|
||||
#define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
|
||||
#define F_FRAGMENTATION V_FRAGMENTATION(1U)
|
||||
|
||||
#define S_MPSHITTYPE 8
|
||||
#define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
|
||||
#define F_MPSHITTYPE V_MPSHITTYPE(1U)
|
||||
|
||||
#define S_MACMATCH 7
|
||||
#define V_MACMATCH(x) ((x) << S_MACMATCH)
|
||||
#define F_MACMATCH V_MACMATCH(1U)
|
||||
|
||||
#define S_ETHERTYPE 6
|
||||
#define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
|
||||
#define F_ETHERTYPE V_ETHERTYPE(1U)
|
||||
|
||||
#define S_PROTOCOL 5
|
||||
#define V_PROTOCOL(x) ((x) << S_PROTOCOL)
|
||||
#define F_PROTOCOL V_PROTOCOL(1U)
|
||||
|
||||
#define S_TOS 4
|
||||
#define V_TOS(x) ((x) << S_TOS)
|
||||
#define F_TOS V_TOS(1U)
|
||||
|
||||
#define S_VLAN 3
|
||||
#define V_VLAN(x) ((x) << S_VLAN)
|
||||
#define F_VLAN V_VLAN(1U)
|
||||
|
||||
#define S_VNIC_ID 2
|
||||
#define V_VNIC_ID(x) ((x) << S_VNIC_ID)
|
||||
#define F_VNIC_ID V_VNIC_ID(1U)
|
||||
|
||||
#define S_PORT 1
|
||||
#define V_PORT(x) ((x) << S_PORT)
|
||||
#define F_PORT V_PORT(1U)
|
||||
|
||||
#define S_FCOE 0
|
||||
#define V_FCOE(x) ((x) << S_FCOE)
|
||||
#define F_FCOE V_FCOE(1U)
|
||||
|
||||
#define A_TP_INGRESS_CONFIG 0x141
|
||||
|
||||
#define S_VNIC 11
|
||||
#define V_VNIC(x) ((x) << S_VNIC)
|
||||
#define F_VNIC V_VNIC(1U)
|
||||
|
||||
#define S_CSUM_HAS_PSEUDO_HDR 10
|
||||
#define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
|
||||
#define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U)
|
||||
|
||||
/* registers for module MPS */
|
||||
#define MPS_BASE_ADDR 0x9000
|
||||
|
||||
#define S_REPLICATE 11
|
||||
#define V_REPLICATE(x) ((x) << S_REPLICATE)
|
||||
#define F_REPLICATE V_REPLICATE(1U)
|
||||
|
||||
#define S_PF 8
|
||||
#define M_PF 0x7U
|
||||
#define V_PF(x) ((x) << S_PF)
|
||||
#define G_PF(x) (((x) >> S_PF) & M_PF)
|
||||
|
||||
#define S_VF_VALID 7
|
||||
#define V_VF_VALID(x) ((x) << S_VF_VALID)
|
||||
#define F_VF_VALID V_VF_VALID(1U)
|
||||
|
||||
#define S_VF 0
|
||||
#define M_VF 0x7fU
|
||||
#define V_VF(x) ((x) << S_VF)
|
||||
#define G_VF(x) (((x) >> S_VF) & M_VF)
|
||||
|
||||
#define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
|
||||
#define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
|
||||
#define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
|
||||
#define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
|
||||
#define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
|
||||
#define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
|
||||
#define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
|
||||
#define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
|
||||
#define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
|
||||
#define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
|
||||
#define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
|
||||
#define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
|
||||
#define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
|
||||
#define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
|
||||
#define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
|
||||
#define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
|
||||
#define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
|
||||
#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
|
||||
#define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
|
||||
#define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
|
||||
#define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
|
||||
#define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
|
||||
#define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
|
||||
#define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
|
||||
#define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
|
||||
#define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
|
||||
#define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
|
||||
#define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
|
||||
#define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
|
||||
#define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
|
||||
#define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
|
||||
#define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
|
||||
#define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
|
||||
#define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
|
||||
#define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
|
||||
#define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
|
||||
#define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
|
||||
#define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
|
||||
#define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
|
||||
#define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
|
||||
#define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
|
||||
#define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
|
||||
#define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
|
||||
#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
|
||||
#define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
|
||||
#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
|
||||
#define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
|
||||
#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
|
||||
#define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
|
||||
#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
|
||||
#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
|
||||
#define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
|
||||
#define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
|
||||
#define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
|
||||
#define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
|
||||
#define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
|
||||
#define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
|
||||
#define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
|
||||
#define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
|
||||
#define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
|
||||
#define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
|
||||
#define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
|
||||
#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
|
||||
#define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
|
||||
#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
|
||||
#define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
|
||||
#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
|
||||
#define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
|
||||
#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
|
||||
#define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
|
||||
#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
|
||||
#define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
|
||||
#define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
|
||||
#define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
|
||||
#define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
|
||||
#define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
|
||||
#define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
|
||||
#define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
|
||||
#define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
|
||||
#define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
|
||||
#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
|
||||
#define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
|
||||
#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
|
||||
#define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
|
||||
#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
|
||||
#define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
|
||||
#define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
|
||||
#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
|
||||
#define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
|
||||
#define A_MPS_CMN_CTL 0x9000
|
||||
|
||||
#define S_NUMPORTS 0
|
||||
#define M_NUMPORTS 0x3U
|
||||
#define V_NUMPORTS(x) ((x) << S_NUMPORTS)
|
||||
#define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
|
||||
|
||||
#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
|
||||
#define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
|
||||
#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
|
||||
#define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
|
||||
#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
|
||||
#define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
|
||||
#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
|
||||
#define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
|
||||
#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
|
||||
#define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
|
||||
#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
|
||||
#define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
|
||||
#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
|
||||
#define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
|
||||
#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
|
||||
#define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
|
||||
#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
|
||||
#define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
|
||||
#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
|
||||
#define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
|
||||
#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
|
||||
#define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
|
||||
#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
|
||||
#define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
|
||||
#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
|
||||
#define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
|
||||
#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
|
||||
#define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
|
||||
#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
|
||||
#define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
|
||||
#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
|
||||
#define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
|
||||
|
||||
/* registers for module ULP_RX */
|
||||
#define ULP_RX_BASE_ADDR 0x19150
|
||||
|
||||
#define S_HPZ0 0
|
||||
#define M_HPZ0 0xfU
|
||||
#define V_HPZ0(x) ((x) << S_HPZ0)
|
||||
#define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
|
||||
|
||||
#define A_ULP_RX_TDDP_PSZ 0x19178
|
||||
|
||||
/* registers for module SF */
|
||||
#define SF_BASE_ADDR 0x193f8
|
||||
|
||||
#define A_SF_DATA 0x193f8
|
||||
#define A_SF_OP 0x193fc
|
||||
|
||||
#define S_SF_LOCK 4
|
||||
#define V_SF_LOCK(x) ((x) << S_SF_LOCK)
|
||||
#define F_SF_LOCK V_SF_LOCK(1U)
|
||||
|
||||
#define S_CONT 3
|
||||
#define V_CONT(x) ((x) << S_CONT)
|
||||
#define F_CONT V_CONT(1U)
|
||||
|
||||
#define S_BYTECNT 1
|
||||
#define M_BYTECNT 0x3U
|
||||
#define V_BYTECNT(x) ((x) << S_BYTECNT)
|
||||
#define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
|
||||
|
||||
#define S_OP 0
|
||||
#define V_OP(x) ((x) << S_OP)
|
||||
#define F_OP V_OP(1U)
|
||||
|
||||
/* registers for module PL */
|
||||
#define PL_BASE_ADDR 0x19400
|
||||
|
||||
#define S_SOURCEPF 8
|
||||
#define M_SOURCEPF 0x7U
|
||||
#define V_SOURCEPF(x) ((x) << S_SOURCEPF)
|
||||
#define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
|
||||
|
||||
#define A_PL_PF_INT_ENABLE 0x3c4
|
||||
|
||||
#define S_PFSW 3
|
||||
#define V_PFSW(x) ((x) << S_PFSW)
|
||||
#define F_PFSW V_PFSW(1U)
|
||||
|
||||
#define S_PFCIM 1
|
||||
#define V_PFCIM(x) ((x) << S_PFCIM)
|
||||
#define F_PFCIM V_PFCIM(1U)
|
||||
|
||||
#define A_PL_WHOAMI 0x19400
|
||||
|
||||
#define A_PL_RST 0x19428
|
||||
|
||||
#define A_PL_INT_MAP0 0x19414
|
||||
|
||||
#define S_PIORST 1
|
||||
#define V_PIORST(x) ((x) << S_PIORST)
|
||||
#define F_PIORST V_PIORST(1U)
|
||||
|
||||
#define S_PIORSTMODE 0
|
||||
#define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
|
||||
#define F_PIORSTMODE V_PIORSTMODE(1U)
|
||||
|
||||
#define A_PL_REV 0x1943c
|
||||
|
||||
#define S_REV 0
|
||||
#define M_REV 0xfU
|
||||
#define V_REV(x) ((x) << S_REV)
|
||||
#define G_REV(x) (((x) >> S_REV) & M_REV)
|
||||
168
drivers/net/cxgbe/base/t4_regs_values.h
Normal file
168
drivers/net/cxgbe/base/t4_regs_values.h
Normal file
@ -0,0 +1,168 @@
|
||||
/*-
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2014-2015 Chelsio Communications.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Chelsio Communications nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef __T4_REGS_VALUES_H__
|
||||
#define __T4_REGS_VALUES_H__
|
||||
|
||||
/*
|
||||
* This file contains definitions for various T4 register value hardware
|
||||
* constants. The types of values encoded here are predominantly those for
|
||||
* register fields which control "modal" behavior. For the most part, we do
|
||||
* not include definitions for register fields which are simple numeric
|
||||
* metrics, etc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* SGE definitions.
|
||||
* ================
|
||||
*/
|
||||
|
||||
/*
|
||||
* SGE register field values.
|
||||
*/
|
||||
|
||||
/* CONTROL register */
|
||||
#define X_RXPKTCPLMODE_SPLIT 1
|
||||
#define X_INGPCIEBOUNDARY_32B 0
|
||||
#define X_INGPADBOUNDARY_SHIFT 5
|
||||
|
||||
/* CONTROL2 register */
|
||||
#define X_INGPACKBOUNDARY_SHIFT 5
|
||||
#define X_INGPACKBOUNDARY_16B 0
|
||||
|
||||
/* GTS register */
|
||||
#define X_TIMERREG_RESTART_COUNTER 6
|
||||
#define X_TIMERREG_UPDATE_CIDX 7
|
||||
|
||||
/*
|
||||
* Egress Context field values
|
||||
*/
|
||||
#define X_FETCHBURSTMIN_64B 2
|
||||
#define X_FETCHBURSTMAX_256B 2
|
||||
#define X_FETCHBURSTMAX_512B 3
|
||||
|
||||
#define X_HOSTFCMODE_NONE 0
|
||||
|
||||
/*
|
||||
* Ingress Context field values
|
||||
*/
|
||||
#define X_UPDATEDELIVERY_INTERRUPT 1
|
||||
|
||||
#define X_RSPD_TYPE_FLBUF 0
|
||||
#define X_RSPD_TYPE_CPL 1
|
||||
|
||||
/*
|
||||
* Context field definitions. This is by no means a complete list of SGE
|
||||
* Context fields. In the vast majority of cases the firmware initializes
|
||||
* things the way they need to be set up. But in a few small cases, we need
|
||||
* to compute new values and ship them off to the firmware to be applied to
|
||||
* the SGE Conexts ...
|
||||
*/
|
||||
|
||||
/*
|
||||
* Congestion Manager Definitions.
|
||||
*/
|
||||
#define S_CONMCTXT_CNGTPMODE 19
|
||||
#define M_CONMCTXT_CNGTPMODE 0x3
|
||||
#define V_CONMCTXT_CNGTPMODE(x) ((x) << S_CONMCTXT_CNGTPMODE)
|
||||
#define G_CONMCTXT_CNGTPMODE(x) \
|
||||
(((x) >> S_CONMCTXT_CNGTPMODE) & M_CONMCTXT_CNGTPMODE)
|
||||
#define S_CONMCTXT_CNGCHMAP 0
|
||||
#define M_CONMCTXT_CNGCHMAP 0xffff
|
||||
#define V_CONMCTXT_CNGCHMAP(x) ((x) << S_CONMCTXT_CNGCHMAP)
|
||||
#define G_CONMCTXT_CNGCHMAP(x) \
|
||||
(((x) >> S_CONMCTXT_CNGCHMAP) & M_CONMCTXT_CNGCHMAP)
|
||||
|
||||
#define X_CONMCTXT_CNGTPMODE_QUEUE 1
|
||||
#define X_CONMCTXT_CNGTPMODE_CHANNEL 2
|
||||
|
||||
/*
|
||||
* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
|
||||
* The User Doorbells are each 128 bytes in length with a Simple Doorbell at
|
||||
* offsets 8x and a Write Combining single 64-byte Egress Queue Unit
|
||||
* (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64. For Ingress Queues,
|
||||
* we have a Going To Sleep register at offsets 8x+4.
|
||||
*
|
||||
* As noted above, we have many instances of the Simple Doorbell and Going To
|
||||
* Sleep registers at offsets 8x and 8x+4, respectively. We want to use a
|
||||
* non-64-byte aligned offset for the Simple Doorbell in order to attempt to
|
||||
* avoid buffering of the writes to the Simple Doorbell and we want to use a
|
||||
* non-contiguous offset for the Going To Sleep writes in order to avoid
|
||||
* possible combining between them.
|
||||
*/
|
||||
#define SGE_UDB_SIZE 128
|
||||
#define SGE_UDB_KDOORBELL 8
|
||||
#define SGE_UDB_GTS 20
|
||||
|
||||
/*
|
||||
* CIM definitions.
|
||||
* ================
|
||||
*/
|
||||
|
||||
/*
|
||||
* CIM register field values.
|
||||
*/
|
||||
#define X_MBOWNER_NONE 0
|
||||
#define X_MBOWNER_FW 1
|
||||
#define X_MBOWNER_PL 2
|
||||
|
||||
/*
|
||||
* PCI-E definitions.
|
||||
* ==================
|
||||
*/
|
||||
#define X_WINDOW_SHIFT 10
|
||||
#define X_PCIEOFST_SHIFT 10
|
||||
|
||||
/*
|
||||
* TP definitions.
|
||||
* ===============
|
||||
*/
|
||||
|
||||
/*
|
||||
* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
|
||||
* Compressed Filter Tuple for LE filters. Each bit set in TP_VLAN_PRI_MAP
|
||||
* selects for a particular field being present. These fields, when present
|
||||
* in the Compressed Filter Tuple, have the following widths in bits.
|
||||
*/
|
||||
#define W_FT_FCOE 1
|
||||
#define W_FT_PORT 3
|
||||
#define W_FT_VNIC_ID 17
|
||||
#define W_FT_VLAN 17
|
||||
#define W_FT_TOS 8
|
||||
#define W_FT_PROTOCOL 8
|
||||
#define W_FT_ETHERTYPE 16
|
||||
#define W_FT_MACMATCH 9
|
||||
#define W_FT_MPSHITTYPE 3
|
||||
#define W_FT_FRAGMENTATION 1
|
||||
|
||||
#endif /* __T4_REGS_VALUES_H__ */
|
||||
1730
drivers/net/cxgbe/base/t4fw_interface.h
Normal file
1730
drivers/net/cxgbe/base/t4fw_interface.h
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user