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net/ice: use write combining store for tail on AVX512

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Performance improvement: use a write combining store
instead of a regular mmio write to update queue tail
registers.

Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: Qi Zhang <qi.z.zhang@intel.com>
This commit is contained in:
Radu Nicolau 2021-04-09 10:09:03 +00:00 committed by Qi Zhang
parent 2ee14c8905
commit 3dc4a4d7e9
1 changed files with 2 additions and 2 deletions
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4
drivers/net/ice/ice_rxtx_vec_avx512.c
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@ -125,7 +125,7 @@ ice_rxq_rearm(struct ice_rx_queue *rxq)
(rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
/* Update the tail pointer on the NIC */
ICE_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
ICE_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
}
static inline __m256i
@ -1111,7 +1111,7 @@ ice_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
txq->tx_tail = tx_id;
ICE_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
ICE_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
return nb_pkts;
}