regex/mlx5: move DevX CQ creation to common
Using common function for DevX CQ creation. Signed-off-by: Michael Baum <michaelba@nvidia.com> Acked-by: Matan Azrad <matan@nvidia.com>
This commit is contained in:
Michael Baum
Ferruh Yigit
parent
9dab4d62b4
commit
3ddf57069b
@ -170,12 +170,6 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
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rte_errno = rte_errno ? rte_errno : EINVAL;
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goto error;
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}
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ret = mlx5_glue->devx_query_eqn(ctx, 0, &priv->eqn);
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if (ret) {
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DRV_LOG(ERR, "can't query event queue number.");
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rte_errno = ENOMEM;
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goto error;
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}
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/*
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* This PMD always claims the write memory barrier on UAR
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* registers writings, it is safe to allocate UAR with any
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@ -12,6 +12,7 @@
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#include <mlx5_common.h>
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#include <mlx5_common_mr.h>
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#include <mlx5_common_devx.h>
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#include "mlx5_rxp.h"
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@ -30,13 +31,8 @@ struct mlx5_regex_sq {
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struct mlx5_regex_cq {
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uint32_t log_nb_desc; /* Log 2 number of desc for this object. */
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struct mlx5_devx_obj *obj; /* The CQ DevX object. */
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int64_t dbr_offset; /* Door bell record offset. */
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uint32_t dbr_umem; /* Door bell record umem id. */
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volatile struct mlx5_cqe *cqe; /* The CQ ring buffer. */
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struct mlx5dv_devx_umem *cqe_umem; /* CQ buffer umem. */
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struct mlx5_devx_cq cq_obj; /* The CQ DevX object. */
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size_t ci;
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uint32_t *dbr;
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};
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struct mlx5_regex_qp {
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@ -75,7 +71,6 @@ struct mlx5_regex_priv {
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struct mlx5_regex_db db[MLX5_RXP_MAX_ENGINES +
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MLX5_RXP_EM_COUNT];
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uint32_t nb_engines; /* Number of RegEx engines. */
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uint32_t eqn; /* EQ number. */
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struct mlx5dv_devx_uar *uar; /* UAR object. */
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struct ibv_pd *pd;
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struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */
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@ -6,6 +6,7 @@
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#include <rte_log.h>
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#include <rte_errno.h>
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#include <rte_memory.h>
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#include <rte_malloc.h>
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#include <rte_regexdev.h>
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#include <rte_regexdev_core.h>
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@ -17,6 +18,7 @@
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#include <mlx5_devx_cmds.h>
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#include <mlx5_prm.h>
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#include <mlx5_common_os.h>
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#include <mlx5_common_devx.h>
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#include "mlx5_regex.h"
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#include "mlx5_regex_utils.h"
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@ -44,8 +46,6 @@ regex_ctrl_get_nb_obj(uint16_t nb_desc)
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/**
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* destroy CQ.
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*
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* @param priv
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* Pointer to the priv object.
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* @param cp
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* Pointer to the CQ to be destroyed.
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*
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@ -53,24 +53,10 @@ regex_ctrl_get_nb_obj(uint16_t nb_desc)
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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*/
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static int
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regex_ctrl_destroy_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)
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regex_ctrl_destroy_cq(struct mlx5_regex_cq *cq)
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{
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if (cq->cqe_umem) {
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mlx5_glue->devx_umem_dereg(cq->cqe_umem);
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cq->cqe_umem = NULL;
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}
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if (cq->cqe) {
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rte_free((void *)(uintptr_t)cq->cqe);
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cq->cqe = NULL;
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}
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if (cq->dbr_offset) {
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mlx5_release_dbr(&priv->dbrpgs, cq->dbr_umem, cq->dbr_offset);
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cq->dbr_offset = -1;
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}
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if (cq->obj) {
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mlx5_devx_cmd_destroy(cq->obj);
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cq->obj = NULL;
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}
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mlx5_devx_cq_destroy(&cq->cq_obj);
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memset(cq, 0, sizeof(*cq));
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return 0;
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}
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@ -89,65 +75,20 @@ static int
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regex_ctrl_create_cq(struct mlx5_regex_priv *priv, struct mlx5_regex_cq *cq)
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{
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struct mlx5_devx_cq_attr attr = {
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.q_umem_valid = 1,
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.db_umem_valid = 1,
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.eqn = priv->eqn,
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.uar_page_id = priv->uar->page_id,
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};
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struct mlx5_devx_dbr_page *dbr_page = NULL;
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void *buf = NULL;
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size_t pgsize = sysconf(_SC_PAGESIZE);
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uint32_t cq_size = 1 << cq->log_nb_desc;
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uint32_t i;
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int ret;
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cq->dbr_offset = mlx5_get_dbr(priv->ctx, &priv->dbrpgs, &dbr_page);
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if (cq->dbr_offset < 0) {
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DRV_LOG(ERR, "Can't allocate cq door bell record.");
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rte_errno = ENOMEM;
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goto error;
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}
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cq->dbr_umem = mlx5_os_get_umem_id(dbr_page->umem);
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cq->dbr = (uint32_t *)((uintptr_t)dbr_page->dbrs +
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(uintptr_t)cq->dbr_offset);
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buf = rte_calloc(NULL, 1, sizeof(struct mlx5_cqe) * cq_size, 4096);
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if (!buf) {
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DRV_LOG(ERR, "Can't allocate cqe buffer.");
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rte_errno = ENOMEM;
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goto error;
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}
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cq->cqe = buf;
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for (i = 0; i < cq_size; i++)
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cq->cqe[i].op_own = 0xff;
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cq->cqe_umem = mlx5_glue->devx_umem_reg(priv->ctx, buf,
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sizeof(struct mlx5_cqe) *
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cq_size, 7);
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cq->ci = 0;
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if (!cq->cqe_umem) {
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DRV_LOG(ERR, "Can't register cqe mem.");
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rte_errno = ENOMEM;
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goto error;
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}
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attr.db_umem_offset = cq->dbr_offset;
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attr.db_umem_id = cq->dbr_umem;
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attr.q_umem_id = mlx5_os_get_umem_id(cq->cqe_umem);
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attr.log_cq_size = cq->log_nb_desc;
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attr.uar_page_id = priv->uar->page_id;
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attr.log_page_size = rte_log2_u32(pgsize);
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cq->obj = mlx5_devx_cmd_create_cq(priv->ctx, &attr);
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if (!cq->obj) {
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DRV_LOG(ERR, "Can't create cq object.");
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rte_errno = ENOMEM;
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goto error;
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ret = mlx5_devx_cq_create(priv->ctx, &cq->cq_obj, cq->log_nb_desc,
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&attr, SOCKET_ID_ANY);
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if (ret) {
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DRV_LOG(ERR, "Can't create CQ object.");
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memset(cq, 0, sizeof(*cq));
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rte_errno = ENOMEM;
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return -rte_errno;
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}
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return 0;
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error:
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if (cq->cqe_umem)
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mlx5_glue->devx_umem_dereg(cq->cqe_umem);
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if (buf)
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rte_free(buf);
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if (cq->dbr_offset)
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mlx5_release_dbr(&priv->dbrpgs, cq->dbr_umem, cq->dbr_offset);
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return -rte_errno;
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}
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#ifdef HAVE_IBV_FLOW_DV_SUPPORT
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@ -232,7 +173,7 @@ regex_ctrl_create_sq(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,
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attr.tis_lst_sz = 0;
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attr.tis_num = 0;
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attr.user_index = q_ind;
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attr.cqn = qp->cq.obj->id;
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attr.cqn = qp->cq.cq_obj.cq->id;
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wq_attr->uar_page = priv->uar->page_id;
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regex_get_pdn(priv->pd, &pd_num);
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wq_attr->pd = pd_num;
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@ -389,7 +330,7 @@ err_fp:
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err_btree:
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for (i = 0; i < nb_sq_config; i++)
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regex_ctrl_destroy_sq(priv, qp, i);
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regex_ctrl_destroy_cq(priv, &qp->cq);
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regex_ctrl_destroy_cq(&qp->cq);
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err_cq:
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rte_free(qp->sqs);
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return ret;
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@ -245,7 +245,7 @@ poll_one(struct mlx5_regex_cq *cq)
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size_t next_cqe_offset;
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next_cqe_offset = (cq->ci & (cq_size_get(cq) - 1));
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cqe = (volatile struct mlx5_cqe *)(cq->cqe + next_cqe_offset);
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cqe = (volatile struct mlx5_cqe *)(cq->cq_obj.cqes + next_cqe_offset);
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rte_io_wmb();
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int ret = check_cqe(cqe, cq_size_get(cq), cq->ci);
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@ -306,7 +306,7 @@ mlx5_regexdev_dequeue(struct rte_regexdev *dev, uint16_t qp_id,
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}
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cq->ci = (cq->ci + 1) & 0xffffff;
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rte_wmb();
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cq->dbr[0] = rte_cpu_to_be_32(cq->ci);
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cq->cq_obj.db_rec[0] = rte_cpu_to_be_32(cq->ci);
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queue->free_sqs |= (1 << sqid);
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}
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