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net/qede/base: changes for 100G

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Change details:

 - Get engine affinity from the management FW and configure accordingly
 - Add an LLH filter with the primary MAC address in QPAR/NPAR
 - Move some of the LLH APIs around
 - Add PPFID APIs
 - Update all allocated ppfids with the same value for the
   following PORT_PF registers:
   NIG_REG_DSCP_TO_TC_MAP_ENABLE
 - Add port_id, src_pfid and dst_pfid to DMA engine params

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
This commit is contained in:
Rasesh Mody 2018-09-29 08:14:35 +00:00 committed by Ferruh Yigit
parent ab67e837be
commit 3eed444a96
15 changed files with 1684 additions and 558 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
drivers/net/qede/base/ecore.h
View File

@ -19,6 +19,7 @@
#include <zlib.h>
#endif
#include "ecore_status.h"
#include "ecore_hsi_common.h"
#include "ecore_hsi_debug_tools.h"
#include "ecore_hsi_init_func.h"
@ -207,6 +208,7 @@ struct ecore_l2_info;
struct ecore_igu_info;
struct ecore_mcp_info;
struct ecore_dcbx_info;
struct ecore_llh_info;
struct ecore_rt_data {
u32 *init_val;
@ -743,6 +745,7 @@ struct ecore_dev {
#endif
#define ECORE_IS_AH(dev) ((dev)->type == ECORE_DEV_TYPE_AH)
#define ECORE_IS_K2(dev) ECORE_IS_AH(dev)
#define ECORE_IS_E4(dev) (ECORE_IS_BB(dev) || ECORE_IS_AH(dev))
u16 vendor_id;
u16 device_id;
@ -837,8 +840,26 @@ struct ecore_dev {
/* HW functions */
u8 num_hwfns;
struct ecore_hwfn hwfns[MAX_HWFNS_PER_DEVICE];
#define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
#define ECORE_IS_CMT(dev) ((dev)->num_hwfns > 1)
/* Engine affinity */
u8 l2_affin_hint;
u8 fir_affin;
u8 iwarp_affin;
/* Macro for getting the engine-affinitized hwfn for FCoE/iSCSI/RoCE */
#define ECORE_FIR_AFFIN_HWFN(dev) (&dev->hwfns[dev->fir_affin])
/* Macro for getting the engine-affinitized hwfn for iWARP */
#define ECORE_IWARP_AFFIN_HWFN(dev) (&dev->hwfns[dev->iwarp_affin])
/* Generic macro for getting the engine-affinitized hwfn */
#define ECORE_AFFIN_HWFN(dev) \
(ECORE_IS_IWARP_PERSONALITY(ECORE_LEADING_HWFN(dev)) ? \
ECORE_IWARP_AFFIN_HWFN(dev) : \
ECORE_FIR_AFFIN_HWFN(dev))
/* Macro for getting the index (0/1) of the engine-affinitized hwfn */
#define ECORE_AFFIN_HWFN_IDX(dev) \
(IS_LEAD_HWFN(ECORE_AFFIN_HWFN(dev)) ? 0 : 1)
/* SRIOV */
struct ecore_hw_sriov_info *p_iov_info;
#define IS_ECORE_SRIOV(p_dev) (!!(p_dev)->p_iov_info)
@ -873,6 +894,9 @@ struct ecore_dev {
#ifndef ASIC_ONLY
bool b_is_emul_full;
#endif
/* LLH info */
u8 ppfid_bitmap;
struct ecore_llh_info *p_llh_info;
/* Indicates whether this PF serves a storage target */
bool b_is_target;
@ -974,6 +998,29 @@ u16 ecore_init_qm_get_num_pf_rls(struct ecore_hwfn *p_hwfn);
u16 ecore_init_qm_get_num_vports(struct ecore_hwfn *p_hwfn);
u16 ecore_init_qm_get_num_pqs(struct ecore_hwfn *p_hwfn);
#define ECORE_LEADING_HWFN(dev) (&dev->hwfns[0])
#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
ecore_device_num_ports((_p_hwfn)->p_dev))
/* The PFID<->PPFID calculation is based on the relative index of a PF on its
* port. In BB there is a bug in the LLH in which the PPFID is actually engine
* based, and thus it equals the PFID.
*/
#define ECORE_PFID_BY_PPFID(_p_hwfn, abs_ppfid) \
(ECORE_IS_BB((_p_hwfn)->p_dev) ? \
(abs_ppfid) : \
(abs_ppfid) * (_p_hwfn)->p_dev->num_ports_in_engine + \
MFW_PORT(_p_hwfn))
#define ECORE_PPFID_BY_PFID(_p_hwfn) \
(ECORE_IS_BB((_p_hwfn)->p_dev) ? \
(_p_hwfn)->rel_pf_id : \
(_p_hwfn)->rel_pf_id / (_p_hwfn)->p_dev->num_ports_in_engine)
enum _ecore_status_t ecore_all_ppfids_wr(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u32 addr,
u32 val);
/* Utility functions for dumping the content of the NIG LLH filters */
enum _ecore_status_t ecore_llh_dump_ppfid(struct ecore_dev *p_dev, u8 ppfid);
enum _ecore_status_t ecore_llh_dump_all(struct ecore_dev *p_dev);
#endif /* __ECORE_H */

4
drivers/net/qede/base/ecore_cxt.c
View File

@ -2114,7 +2114,7 @@ ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
0 /* no flags */);
OSAL_NULL /* default parameters */);
if (elem_type == ECORE_ELEM_CXT) {
u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
@ -2221,7 +2221,7 @@ ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
(u64)(osal_uintptr_t)&ilt_hw_entry,
reg_offset,
sizeof(ilt_hw_entry) / sizeof(u32),
0 /* no flags */);
OSAL_NULL /* default parameters */);
}
ecore_ptt_release(p_hwfn, p_ptt);

11
drivers/net/qede/base/ecore_dcbx.c
View File

@ -893,12 +893,19 @@ ecore_dcbx_mib_update_event(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
ecore_dcbx_get_params(p_hwfn, &p_hwfn->p_dcbx_info->get, type);
/* Update the DSCP to TC mapping bit if required */
/* Update the DSCP to TC mapping enable bit if required */
if ((type == ECORE_DCBX_OPERATIONAL_MIB) &&
p_hwfn->p_dcbx_info->dscp_nig_update) {
u8 val = !!p_hwfn->p_dcbx_info->get.dscp.enabled;
u32 addr = NIG_REG_DSCP_TO_TC_MAP_ENABLE;
rc = ecore_all_ppfids_wr(p_hwfn, p_ptt, addr, val);
if (rc != ECORE_SUCCESS) {
DP_NOTICE(p_hwfn, false,
"Failed to update the DSCP to TC mapping enable bit\n");
return rc;
}
ecore_wr(p_hwfn, p_ptt, NIG_REG_DSCP_TO_TC_MAP_ENABLE, val);
p_hwfn->p_dcbx_info->dscp_nig_update = false;
}

1740
drivers/net/qede/base/ecore_dev.c
View File

File diff suppressed because it is too large Load Diff

161
drivers/net/qede/base/ecore_dev_api.h
View File

@ -114,6 +114,9 @@ struct ecore_hw_init_params {
/* Driver load parameters */
struct ecore_drv_load_params *p_drv_load_params;
/* Avoid engine affinity for RoCE/storage in case of CMT mode */
bool avoid_eng_affin;
/* SPQ block timeout in msec */
u32 spq_timeout_ms;
};
@ -428,11 +431,17 @@ enum ecore_dmae_address_type_t {
#define ECORE_DMAE_FLAG_VF_SRC 0x00000002
#define ECORE_DMAE_FLAG_VF_DST 0x00000004
#define ECORE_DMAE_FLAG_COMPLETION_DST 0x00000008
#define ECORE_DMAE_FLAG_PORT 0x00000010
#define ECORE_DMAE_FLAG_PF_SRC 0x00000020
#define ECORE_DMAE_FLAG_PF_DST 0x00000040
struct ecore_dmae_params {
u32 flags; /* consists of ECORE_DMAE_FLAG_* values */
u8 src_vfid;
u8 dst_vfid;
u8 port_id;
u8 src_pfid;
u8 dst_pfid;
};
/**
@ -444,7 +453,9 @@ struct ecore_dmae_params {
* @param source_addr
* @param grc_addr (dmae_data_offset)
* @param size_in_dwords
* @param flags (one of the flags defined above)
* @param p_params (default parameters will be used in case of OSAL_NULL)
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t
ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
@ -452,7 +463,7 @@ ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
u64 source_addr,
u32 grc_addr,
u32 size_in_dwords,
u32 flags);
struct ecore_dmae_params *p_params);
/**
* @brief ecore_dmae_grc2host - Read data from dmae data offset
@ -462,7 +473,9 @@ ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
* @param grc_addr (dmae_data_offset)
* @param dest_addr
* @param size_in_dwords
* @param flags - one of the flags defined above
* @param p_params (default parameters will be used in case of OSAL_NULL)
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t
ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
@ -470,7 +483,7 @@ ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
u32 grc_addr,
dma_addr_t dest_addr,
u32 size_in_dwords,
u32 flags);
struct ecore_dmae_params *p_params);
/**
* @brief ecore_dmae_host2host - copy data from to source address
@ -481,7 +494,9 @@ ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
* @param source_addr
* @param dest_addr
* @param size_in_dwords
* @param params
* @param p_params (default parameters will be used in case of OSAL_NULL)
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t
ecore_dmae_host2host(struct ecore_hwfn *p_hwfn,
@ -562,28 +577,79 @@ enum _ecore_status_t ecore_fw_rss_eng(struct ecore_hwfn *p_hwfn,
u8 *dst_id);
/**
* @brief ecore_llh_add_mac_filter - configures a MAC filter in llh
* @brief ecore_llh_get_num_ppfid - Return the allocated number of LLH filter
* banks that are allocated to the PF.
*
* @param p_hwfn
* @param p_ptt
* @param p_filter - MAC to add
* @param p_dev
*
* @return u8 - Number of LLH filter banks
*/
enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u8 *p_filter);
u8 ecore_llh_get_num_ppfid(struct ecore_dev *p_dev);
enum ecore_eng {
ECORE_ENG0,
ECORE_ENG1,
ECORE_BOTH_ENG,
};
/**
* @brief ecore_llh_remove_mac_filter - removes a MAC filtre from llh
* @brief ecore_llh_get_l2_affinity_hint - Return the hint for the L2 affinity
*
* @param p_hwfn
* @param p_ptt
* @param p_filter - MAC to remove
* @param p_dev
*
* @return enum ecore_eng - L2 affintiy hint
*/
void ecore_llh_remove_mac_filter(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u8 *p_filter);
enum ecore_eng ecore_llh_get_l2_affinity_hint(struct ecore_dev *p_dev);
enum ecore_llh_port_filter_type_t {
/**
* @brief ecore_llh_set_ppfid_affinity - Set the engine affinity for the given
* LLH filter bank.
*
* @param p_dev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
* @param eng
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_llh_set_ppfid_affinity(struct ecore_dev *p_dev,
u8 ppfid, enum ecore_eng eng);
/**
* @brief ecore_llh_set_roce_affinity - Set the RoCE engine affinity
*
* @param p_dev
* @param eng
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_llh_set_roce_affinity(struct ecore_dev *p_dev,
enum ecore_eng eng);
/**
* @brief ecore_llh_add_mac_filter - Add a LLH MAC filter into the given filter
* bank.
*
* @param p_dev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
* @param mac_addr - MAC to add
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
u8 mac_addr[ETH_ALEN]);
/**
* @brief ecore_llh_remove_mac_filter - Remove a LLH MAC filter from the given
* filter bank.
*
* @param p_dev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
* @param mac_addr - MAC to remove
*/
void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
u8 mac_addr[ETH_ALEN]);
enum ecore_llh_prot_filter_type_t {
ECORE_LLH_FILTER_ETHERTYPE,
ECORE_LLH_FILTER_TCP_SRC_PORT,
ECORE_LLH_FILTER_TCP_DEST_PORT,
@ -594,45 +660,52 @@ enum ecore_llh_port_filter_type_t {
};
/**
* @brief ecore_llh_add_protocol_filter - configures a protocol filter in llh
* @brief ecore_llh_add_protocol_filter - Add a LLH protocol filter into the
* given filter bank.
*
* @param p_hwfn
* @param p_ptt
* @param p_dev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
* @param type - type of filters and comparing
* @param source_port_or_eth_type - source port or ethertype to add
* @param dest_port - destination port to add
* @param type - type of filters and comparing
*
* @return enum _ecore_status_t
*/
enum _ecore_status_t
ecore_llh_add_protocol_filter(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 source_port_or_eth_type,
u16 dest_port,
enum ecore_llh_port_filter_type_t type);
ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
enum ecore_llh_prot_filter_type_t type,
u16 source_port_or_eth_type, u16 dest_port);
/**
* @brief ecore_llh_remove_protocol_filter - remove a protocol filter in llh
* @brief ecore_llh_remove_protocol_filter - Remove a LLH protocol filter from
* the given filter bank.
*
* @param p_hwfn
* @param p_ptt
* @param p_dev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
* @param type - type of filters and comparing
* @param source_port_or_eth_type - source port or ethertype to add
* @param dest_port - destination port to add
* @param type - type of filters and comparing
*/
void
ecore_llh_remove_protocol_filter(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 source_port_or_eth_type,
u16 dest_port,
enum ecore_llh_port_filter_type_t type);
void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
enum ecore_llh_prot_filter_type_t type,
u16 source_port_or_eth_type,
u16 dest_port);
/**
* @brief ecore_llh_clear_all_filters - removes all MAC filters from llh
* @brief ecore_llh_clear_ppfid_filters - Remove all LLH filters from the given
* filter bank.
*
* @param p_hwfn
* @param p_ptt
* @param p_dev
* @param ppfid - relative within the allocated ppfids ('0' is the default one).
*/
void ecore_llh_clear_all_filters(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid);
/**
* @brief ecore_llh_clear_all_filters - Remove all LLH filters
*
* @param p_dev
*/
void ecore_llh_clear_all_filters(struct ecore_dev *p_dev);
/**
* @brief ecore_llh_set_function_as_default - set function as default per port

103
drivers/net/qede/base/ecore_hw.c
View File

@ -450,14 +450,17 @@ u32 ecore_vfid_to_concrete(struct ecore_hwfn *p_hwfn, u8 vfid)
* If this changes, this needs to be revisted.
*/
/* Ecore DMAE
* =============
*/
/* DMAE */
#define ECORE_DMAE_FLAGS_IS_SET(params, flag) \
((params) != OSAL_NULL && ((params)->flags & ECORE_DMAE_FLAG_##flag))
static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
const u8 is_src_type_grc,
const u8 is_dst_type_grc,
struct ecore_dmae_params *p_params)
{
u8 src_pfid, dst_pfid, port_id;
u16 opcode_b = 0;
u32 opcode = 0;
@ -467,16 +470,20 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
*/
opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC
: DMAE_CMD_SRC_MASK_PCIE) << DMAE_CMD_SRC_SHIFT;
opcode |= (p_hwfn->rel_pf_id & DMAE_CMD_SRC_PF_ID_MASK) <<
DMAE_CMD_SRC_PF_ID_SHIFT;
src_pfid = ECORE_DMAE_FLAGS_IS_SET(p_params, PF_SRC) ?
p_params->src_pfid : p_hwfn->rel_pf_id;
opcode |= (src_pfid & DMAE_CMD_SRC_PF_ID_MASK) <<
DMAE_CMD_SRC_PF_ID_SHIFT;
/* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC
: DMAE_CMD_DST_MASK_PCIE) << DMAE_CMD_DST_SHIFT;
opcode |= (p_hwfn->rel_pf_id & DMAE_CMD_DST_PF_ID_MASK) <<
DMAE_CMD_DST_PF_ID_SHIFT;
dst_pfid = ECORE_DMAE_FLAGS_IS_SET(p_params, PF_DST) ?
p_params->dst_pfid : p_hwfn->rel_pf_id;
opcode |= (dst_pfid & DMAE_CMD_DST_PF_ID_MASK) <<
DMAE_CMD_DST_PF_ID_SHIFT;
/* DMAE_E4_TODO need to check which value to specifiy here. */
/* DMAE_E4_TODO need to check which value to specify here. */
/* opcode |= (!b_complete_to_host)<< DMAE_CMD_C_DST_SHIFT; */
/* Whether to write a completion word to the completion destination:
@ -486,7 +493,7 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
opcode |= DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT;
opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
if (p_params->flags & ECORE_DMAE_FLAG_COMPLETION_DST)
if (ECORE_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST))
opcode |= 1 << DMAE_CMD_COMP_FUNC_SHIFT;
/* swapping mode 3 - big endian there should be a define ifdefed in
@ -494,7 +501,9 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
*/
opcode |= DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT;
opcode |= p_hwfn->port_id << DMAE_CMD_PORT_ID_SHIFT;
port_id = (ECORE_DMAE_FLAGS_IS_SET(p_params, PORT)) ?
p_params->port_id : p_hwfn->port_id;
opcode |= port_id << DMAE_CMD_PORT_ID_SHIFT;
/* reset source address in next go */
opcode |= DMAE_CMD_SRC_ADDR_RESET_MASK << DMAE_CMD_SRC_ADDR_RESET_SHIFT;
@ -503,14 +512,14 @@ static void ecore_dmae_opcode(struct ecore_hwfn *p_hwfn,
opcode |= DMAE_CMD_DST_ADDR_RESET_MASK << DMAE_CMD_DST_ADDR_RESET_SHIFT;
/* SRC/DST VFID: all 1's - pf, otherwise VF id */
if (p_params->flags & ECORE_DMAE_FLAG_VF_SRC) {
if (ECORE_DMAE_FLAGS_IS_SET(p_params, VF_SRC)) {
opcode |= (1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT);
opcode_b |= (p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT);
} else {
opcode_b |= (DMAE_CMD_SRC_VF_ID_MASK <<
DMAE_CMD_SRC_VF_ID_SHIFT);
}
if (p_params->flags & ECORE_DMAE_FLAG_VF_DST) {
if (ECORE_DMAE_FLAGS_IS_SET(p_params, VF_DST)) {
opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT;
opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT;
} else {
@ -855,7 +864,7 @@ ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
for (i = 0; i <= cnt_split; i++) {
offset = length_limit * i;
if (!(p_params->flags & ECORE_DMAE_FLAG_RW_REPL_SRC)) {
if (!ECORE_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) {
if (src_type == ECORE_DMAE_ADDRESS_GRC)
src_addr_split = src_addr + offset;
else
@ -896,51 +905,45 @@ ecore_dmae_execute_command(struct ecore_hwfn *p_hwfn,
return ecore_status;
}
enum _ecore_status_t
ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u64 source_addr,
u32 grc_addr, u32 size_in_dwords, u32 flags)
enum _ecore_status_t ecore_dmae_host2grc(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u64 source_addr,
u32 grc_addr,
u32 size_in_dwords,
struct ecore_dmae_params *p_params)
{
u32 grc_addr_in_dw = grc_addr / sizeof(u32);
struct ecore_dmae_params params;
enum _ecore_status_t rc;
OSAL_MEMSET(&params, 0, sizeof(struct ecore_dmae_params));
params.flags = flags;
OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
rc = ecore_dmae_execute_command(p_hwfn, p_ptt, source_addr,
grc_addr_in_dw,
ECORE_DMAE_ADDRESS_HOST_VIRT,
ECORE_DMAE_ADDRESS_GRC,
size_in_dwords, &params);
size_in_dwords, p_params);
OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
return rc;
}
enum _ecore_status_t
ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 grc_addr,
dma_addr_t dest_addr, u32 size_in_dwords, u32 flags)
enum _ecore_status_t ecore_dmae_grc2host(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 grc_addr,
dma_addr_t dest_addr,
u32 size_in_dwords,
struct ecore_dmae_params *p_params)
{
u32 grc_addr_in_dw = grc_addr / sizeof(u32);
struct ecore_dmae_params params;
enum _ecore_status_t rc;
OSAL_MEMSET(&params, 0, sizeof(struct ecore_dmae_params));
params.flags = flags;
OSAL_SPIN_LOCK(&p_hwfn->dmae_info.lock);
rc = ecore_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw,
dest_addr, ECORE_DMAE_ADDRESS_GRC,
ECORE_DMAE_ADDRESS_HOST_VIRT,
size_in_dwords, &params);
size_in_dwords, p_params);
OSAL_SPIN_UNLOCK(&p_hwfn->dmae_info.lock);
@ -989,7 +992,6 @@ enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
const char *phase)
{
u32 size = OSAL_PAGE_SIZE / 2, val;
struct ecore_dmae_params params;
enum _ecore_status_t rc = ECORE_SUCCESS;
dma_addr_t p_phys;
void *p_virt;
@ -1021,9 +1023,9 @@ enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
(unsigned long)(p_phys + size),
(u8 *)p_virt + size, size);
OSAL_MEMSET(&params, 0, sizeof(params));
rc = ecore_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size,
size / 4 /* size_in_dwords */, &params);
size / 4 /* size_in_dwords */,
OSAL_NULL /* default parameters */);
if (rc != ECORE_SUCCESS) {
DP_NOTICE(p_hwfn, false,
"DMAE sanity [%s]: ecore_dmae_host2host() failed. rc = %d.\n",
@ -1054,3 +1056,32 @@ enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev, p_virt, p_phys, 2 * size);
return rc;
}
void ecore_ppfid_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
u8 abs_ppfid, u32 hw_addr, u32 val)
{
u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
ecore_fid_pretend(p_hwfn, p_ptt,
pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
ecore_wr(p_hwfn, p_ptt, hw_addr, val);
ecore_fid_pretend(p_hwfn, p_ptt,
p_hwfn->rel_pf_id <<
PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
}
u32 ecore_ppfid_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
u8 abs_ppfid, u32 hw_addr)
{
u8 pfid = ECORE_PFID_BY_PPFID(p_hwfn, abs_ppfid);
u32 val;
ecore_fid_pretend(p_hwfn, p_ptt,
pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
val = ecore_rd(p_hwfn, p_ptt, hw_addr);
ecore_fid_pretend(p_hwfn, p_ptt,
p_hwfn->rel_pf_id <<
PXP_PRETEND_CONCRETE_FID_PFID_SHIFT);
return val;
}

28
drivers/net/qede/base/ecore_hw.h
View File

@ -134,8 +134,8 @@ struct ecore_ptt *ecore_get_reserved_ptt(struct ecore_hwfn *p_hwfn,
*
* @param p_hwfn
* @param p_ptt
* @param val
* @param hw_addr
* @param val
*/
void ecore_wr(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
@ -147,7 +147,6 @@ void ecore_wr(struct ecore_hwfn *p_hwfn,
*
* @param p_hwfn
* @param p_ptt
* @param val
* @param hw_addr
*/
u32 ecore_rd(struct ecore_hwfn *p_hwfn,
@ -269,4 +268,29 @@ enum _ecore_status_t ecore_dmae_sanity(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
const char *phase);
/**
* @brief ecore_ppfid_wr - Write value to BAR using the given ptt while
* pretending to a PF to which the given PPFID pertains.
*
* @param p_hwfn
* @param p_ptt
* @param abs_ppfid
* @param hw_addr
* @param val
*/
void ecore_ppfid_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
u8 abs_ppfid, u32 hw_addr, u32 val);
/**
* @brief ecore_ppfid_rd - Read value from BAR using the given ptt while
* pretending to a PF to which the given PPFID pertains.
*
* @param p_hwfn
* @param p_ptt
* @param abs_ppfid
* @param hw_addr
*/
u32 ecore_ppfid_rd(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
u8 abs_ppfid, u32 hw_addr);
#endif /* __ECORE_HW_H__ */

14
drivers/net/qede/base/ecore_init_ops.c
View File

@ -101,7 +101,8 @@ static enum _ecore_status_t ecore_init_rt(struct ecore_hwfn *p_hwfn,
rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
(osal_uintptr_t)(p_init_val + i),
addr + (i << 2), segment, 0);
addr + (i << 2), segment,
OSAL_NULL /* default parameters */);
if (rc != ECORE_SUCCESS)
return rc;
@ -165,8 +166,9 @@ static enum _ecore_status_t ecore_init_array_dmae(struct ecore_hwfn *p_hwfn,
} else {
rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
(osal_uintptr_t)(p_buf +
dmae_data_offset),
addr, size, 0);
dmae_data_offset),
addr, size,
OSAL_NULL /* default parameters */);
}
return rc;
@ -177,13 +179,15 @@ static enum _ecore_status_t ecore_init_fill_dmae(struct ecore_hwfn *p_hwfn,
u32 addr, u32 fill_count)
{
static u32 zero_buffer[DMAE_MAX_RW_SIZE];
struct ecore_dmae_params params;
OSAL_MEMSET(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE);
OSAL_MEMSET(&params, 0, sizeof(params));
params.flags = ECORE_DMAE_FLAG_RW_REPL_SRC;
return ecore_dmae_host2grc(p_hwfn, p_ptt,
(osal_uintptr_t)&zero_buffer[0],
addr, fill_count,
ECORE_DMAE_FLAG_RW_REPL_SRC);
addr, fill_count, &params);
}
static void ecore_init_fill(struct ecore_hwfn *p_hwfn,

13
drivers/net/qede/base/ecore_int.c
View File

@ -1561,11 +1561,13 @@ void ecore_int_cau_conf_sb(struct ecore_hwfn *p_hwfn,
ecore_dmae_host2grc(p_hwfn, p_ptt,
(u64)(osal_uintptr_t)&phys_addr,
CAU_REG_SB_ADDR_MEMORY +
igu_sb_id * sizeof(u64), 2, 0);
igu_sb_id * sizeof(u64), 2,
OSAL_NULL /* default parameters */);
ecore_dmae_host2grc(p_hwfn, p_ptt,
(u64)(osal_uintptr_t)&sb_entry,
CAU_REG_SB_VAR_MEMORY +
igu_sb_id * sizeof(u64), 2, 0);
igu_sb_id * sizeof(u64), 2,
OSAL_NULL /* default parameters */);
} else {
/* Initialize Status Block Address */
STORE_RT_REG_AGG(p_hwfn,
@ -2646,7 +2648,8 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
sb_id * sizeof(u64),
(u64)(osal_uintptr_t)&sb_entry, 2, 0);
(u64)(osal_uintptr_t)&sb_entry, 2,
OSAL_NULL /* default parameters */);
if (rc != ECORE_SUCCESS) {
DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
return rc;
@ -2659,8 +2662,8 @@ enum _ecore_status_t ecore_int_set_timer_res(struct ecore_hwfn *p_hwfn,
rc = ecore_dmae_host2grc(p_hwfn, p_ptt,
(u64)(osal_uintptr_t)&sb_entry,
CAU_REG_SB_VAR_MEMORY +
sb_id * sizeof(u64), 2, 0);
CAU_REG_SB_VAR_MEMORY + sb_id * sizeof(u64), 2,
OSAL_NULL /* default parameters */);
if (rc != ECORE_SUCCESS) {
DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
return rc;

6
drivers/net/qede/base/ecore_l2.c
View File

@ -2217,7 +2217,8 @@ int ecore_get_rxq_coalesce(struct ecore_hwfn *p_hwfn,
rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
p_cid->sb_igu_id * sizeof(u64),
(u64)(osal_uintptr_t)&sb_entry, 2, 0);
(u64)(osal_uintptr_t)&sb_entry, 2,
OSAL_NULL /* default parameters */);
if (rc != ECORE_SUCCESS) {
DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
return rc;
@ -2251,7 +2252,8 @@ int ecore_get_txq_coalesce(struct ecore_hwfn *p_hwfn,
rc = ecore_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
p_cid->sb_igu_id * sizeof(u64),
(u64)(osal_uintptr_t)&sb_entry, 2, 0);
(u64)(osal_uintptr_t)&sb_entry, 2,
OSAL_NULL /* default parameters */);
if (rc != ECORE_SUCCESS) {
DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
return rc;

69
drivers/net/qede/base/ecore_mcp.c
View File

@ -4144,6 +4144,75 @@ ecore_mcp_drv_attribute(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
return ECORE_SUCCESS;
}
enum _ecore_status_t ecore_mcp_get_engine_config(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
struct ecore_dev *p_dev = p_hwfn->p_dev;
struct ecore_mcp_mb_params mb_params;
u8 fir_valid, l2_valid;
enum _ecore_status_t rc;
OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
mb_params.cmd = DRV_MSG_CODE_GET_ENGINE_CONFIG;
rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
if (rc != ECORE_SUCCESS)
return rc;
if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
DP_INFO(p_hwfn,
"The get_engine_config command is unsupported by the MFW\n");
return ECORE_NOTIMPL;
}
fir_valid = GET_MFW_FIELD(mb_params.mcp_param,
FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID);
if (fir_valid)
p_dev->fir_affin =
GET_MFW_FIELD(mb_params.mcp_param,
FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE);
l2_valid = GET_MFW_FIELD(mb_params.mcp_param,
FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID);
if (l2_valid)
p_dev->l2_affin_hint =
GET_MFW_FIELD(mb_params.mcp_param,
FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE);
DP_INFO(p_hwfn,
"Engine affinity config: FIR={valid %hhd, value %hhd}, L2_hint={valid %hhd, value %hhd}\n",
fir_valid, p_dev->fir_affin, l2_valid, p_dev->l2_affin_hint);
return ECORE_SUCCESS;
}
enum _ecore_status_t ecore_mcp_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
struct ecore_dev *p_dev = p_hwfn->p_dev;
struct ecore_mcp_mb_params mb_params;
enum _ecore_status_t rc;
OSAL_MEM_ZERO(&mb_params, sizeof(mb_params));
mb_params.cmd = DRV_MSG_CODE_GET_PPFID_BITMAP;
rc = ecore_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
if (rc != ECORE_SUCCESS)
return rc;
if (mb_params.mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
DP_INFO(p_hwfn,
"The get_ppfid_bitmap command is unsupported by the MFW\n");
return ECORE_NOTIMPL;
}
p_dev->ppfid_bitmap = GET_MFW_FIELD(mb_params.mcp_param,
FW_MB_PARAM_PPFID_BITMAP);
DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "PPFID bitmap 0x%hhx\n",
p_dev->ppfid_bitmap);
return ECORE_SUCCESS;
}
void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
u32 offset, u32 val)
{

21
drivers/net/qede/base/ecore_mcp.h
View File

@ -25,9 +25,6 @@
rel_pfid)
#define MCP_PF_ID(p_hwfn) MCP_PF_ID_BY_REL(p_hwfn, (p_hwfn)->rel_pf_id)
#define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \
ecore_device_num_ports((_p_hwfn)->p_dev))
struct ecore_mcp_info {
/* List for mailbox commands which were sent and wait for a response */
osal_list_t cmd_list;
@ -566,4 +563,22 @@ ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
void ecore_mcp_wol_wr(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
u32 offset, u32 val);
/**
* @brief Get the engine affinity configuration.
*
* @param p_hwfn
* @param p_ptt
*/
enum _ecore_status_t ecore_mcp_get_engine_config(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
/**
* @brief Get the PPFID bitmap.
*
* @param p_hwfn
* @param p_ptt
*/
enum _ecore_status_t ecore_mcp_get_ppfid_bitmap(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
#endif /* __ECORE_MCP_H__ */

4
drivers/net/qede/base/ecore_sriov.c
View File

@ -979,10 +979,12 @@ static u8 ecore_iov_alloc_vf_igu_sbs(struct ecore_hwfn *p_hwfn,
ecore_init_cau_sb_entry(p_hwfn, &sb_entry,
p_hwfn->rel_pf_id,
vf->abs_vf_id, 1);
ecore_dmae_host2grc(p_hwfn, p_ptt,
(u64)(osal_uintptr_t)&sb_entry,
CAU_REG_SB_VAR_MEMORY +
p_block->igu_sb_id * sizeof(u64), 2, 0);
p_block->igu_sb_id * sizeof(u64), 2,
OSAL_NULL /* default parameters */);
}
vf->num_sbs = (u8)num_rx_queues;

15
drivers/net/qede/base/mcp_public.h
View File

@ -1267,6 +1267,8 @@ struct public_drv_mb {
#define DRV_MSG_CODE_OEM_RESET_TO_DEFAULT 0x3f000000
#define DRV_MSG_CODE_OV_GET_CURR_CFG 0x40000000
#define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000
/* params [31:8] - reserved, [7:0] - bitmap */
#define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000
/*deprecated don't use*/
#define DRV_MSG_CODE_INITIATE_FLR_DEPRECATED 0x02000000
@ -1476,6 +1478,7 @@ struct public_drv_mb {
/* Param: Password len. Union: Plain Password */
#define DRV_MSG_CODE_ENCRYPT_PASSWORD 0x00360000
#define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000 /* Param: None */
#define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
@ -1812,6 +1815,18 @@ struct public_drv_mb {
#define FW_MB_PARAM_OEM_UPDATE_S_TAG 0x02
#define FW_MB_PARAM_OEM_UPDATE_CFG 0x04
#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001
#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_OFFSET 0
#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002
#define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_OFFSET 1
#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004
#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_OFFSET 2
#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008
#define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_OFFSET 3
#define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF
#define FW_MB_PARAM_PPFID_BITMAP_OFFSET 0
u32 drv_pulse_mb;
#define DRV_PULSE_SEQ_MASK 0x00007fff
#define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000

4
drivers/net/qede/base/reg_addr.h
View File

@ -1235,3 +1235,7 @@
#define DORQ_REG_TAG1_OVRD_MODE 0x1008b4UL
#define DORQ_REG_PF_EXT_VID_BB_K2 0x1008c8UL
#define PRS_REG_SEARCH_NON_IP_AS_GFT 0x1f11c0UL
#define NIG_REG_LLH_PPFID2PFID_TBL_0 0x501970UL
#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL
#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL 0x501b98UL
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_BB_K2 0x501b40UL