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net/bnxt: support Thor platform

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1. Add templates to support Thor platform.
2. Flow counter manager is not enabled if no flow counters are
   configured.
3. Mark database is not enabled if mark action is not supported.
4. Removed application to port default flow.
5. Add allocate and write for the global registry file.
6. Multiple default flow templates are combined to one.
7. Remove default loopback action record, this is required in order to
   support multiple platforms.
8. Enable port table support in the generic table.
9. remove global template table in order to support multiple platforms.
10. Add support to get parent VNIC from port table database.
11. VF representor action mark is made optional since not all
    configurations need representor support.
12. Add layer 4 ports to computational fields.
13. Update templates to support the above changes.
14. Add support for wildcard.

Signed-off-by: Kishore Padmanabha <kishore.padmanabha@broadcom.com>
Signed-off-by: Venkat Duvvuru <venkatkumar.duvvuru@broadcom.com>
Reviewed-by: Mike Baucom <michael.baucom@broadcom.com>
Reviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>
This commit is contained in:
Kishore Padmanabha 2021-05-30 14:29:17 +05:30 committed by Ajit Khaparde
parent 0001cc58d3
commit 3fe124d253
35 changed files with 93181 additions and 79323 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
doc/guides/nics/features/bnxt.ini
View File

@ -53,9 +53,12 @@ Usage doc = Y
Perf doc = Y
[rte_flow items]
any = Y
eth = Y
ipv4 = Y
ipv6 = Y
gre = Y
icmp = Y
pf = Y
phy_port = Y
port_id = Y
@ -79,6 +82,7 @@ pf = Y
phy_port = Y
port_id = Y
rss = Y
sample = Y
set_ipv4_dst = Y
set_ipv4_src = Y
set_tp_dst = Y

2
drivers/net/bnxt/meson.build
View File

@ -8,7 +8,9 @@ if is_windows
subdir_done()
endif
headers = files('rte_pmd_bnxt.h')
cflags_options = [
'-DRTE_LIBRTE_BNXT_TF',
'-DSUPPORT_CFA_HW_ALL=1',
]

8
drivers/net/bnxt/tf_core/tf_core.h
View File

@ -1104,10 +1104,6 @@ struct tf_alloc_tbl_scope_parms {
* [in] Number of flows * 1000. If set, rx_mem_size_in_mb must equal 0.
*/
uint32_t rx_num_flows_in_k;
/**
* [in] SR2 only receive table access interface id
*/
uint32_t rx_tbl_if_id;
/**
* [in] All Maximum key size required.
*/
@ -1126,10 +1122,6 @@ struct tf_alloc_tbl_scope_parms {
* [in] Number of flows * 1000
*/
uint32_t tx_num_flows_in_k;
/**
* [in] SR2 only receive table access interface id
*/
uint32_t tx_tbl_if_id;
/**
* [in] Flush pending HW cached flows every 1/10th of value
* set in seconds, both idle and active flows are flushed

2
drivers/net/bnxt/tf_ulp/bnxt_tf_common.h
View File

@ -23,12 +23,10 @@
#define BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY 256
#define BNXT_ULP_DFLT_RX_MEM 0
#define BNXT_ULP_RX_NUM_FLOWS 32
#define BNXT_ULP_RX_TBL_IF_ID 0
#define BNXT_ULP_DFLT_TX_MAX_KEY 512
#define BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY 256
#define BNXT_ULP_DFLT_TX_MEM 0
#define BNXT_ULP_TX_NUM_FLOWS 32
#define BNXT_ULP_TX_TBL_IF_ID 0
enum bnxt_tf_rc {
BNXT_TF_RC_PARSE_ERR = -2,

99
drivers/net/bnxt/tf_ulp/bnxt_ulp.c
View File

@ -22,6 +22,7 @@
#include "ulp_flow_db.h"
#include "ulp_mapper.h"
#include "ulp_port_db.h"
#include "ulp_tun.h"
/* Linked list of all TF sessions. */
STAILQ_HEAD(, bnxt_ulp_session_state) bnxt_ulp_session_list =
@ -52,8 +53,11 @@ static int32_t
bnxt_ulp_devid_get(struct bnxt *bp,
enum bnxt_ulp_device_id *ulp_dev_id)
{
if (BNXT_CHIP_P5(bp))
return -EINVAL;
if (BNXT_CHIP_P5(bp)) {
/* TBD: needs to accommodate even SR2 */
*ulp_dev_id = BNXT_ULP_DEVICE_ID_THOR;
return 0;
}
if (BNXT_STINGRAY(bp))
*ulp_dev_id = BNXT_ULP_DEVICE_ID_STINGRAY;
@ -70,6 +74,7 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
{
uint32_t dev_id;
int32_t rc;
uint16_t *tmp_cnt;
rc = bnxt_ulp_cntxt_dev_id_get(bp->ulp_ctx, &dev_id);
if (rc) {
@ -113,6 +118,8 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
/* SP */
res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC] = 255;
res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 1;
/** TX **/
/* Identifiers */
res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 292;
@ -148,6 +155,9 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
/* SP */
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 488;
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 511;
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 1;
break;
case BNXT_ULP_DEVICE_ID_STINGRAY:
/** RX **/
@ -219,6 +229,73 @@ bnxt_ulp_tf_session_resources_get(struct bnxt *bp,
/* SP */
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 488;
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV6] = 512;
break;
case BNXT_ULP_DEVICE_ID_THOR:
/** RX **/
/* Identifiers */
res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 26;
res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 6;
res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_WC_PROF] = 32;
res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 32;
res->ident_cnt[TF_DIR_RX].cnt[TF_IDENT_TYPE_EM_PROF] = 32;
/* Table Types */
res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 1024;
res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 512;
res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 14;
res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_EM_FKB] = 32;
res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_WC_FKB] = 32;
/* ENCAP */
res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 64;
/* TCAMs */
tmp_cnt = &res->tcam_cnt[TF_DIR_RX].cnt[0];
tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = 300;
tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = 6;
res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 128;
res->tcam_cnt[TF_DIR_RX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 112;
/* EM */
res->em_cnt[TF_DIR_RX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 13200;
/* SP */
res->tbl_cnt[TF_DIR_RX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 64;
/** TX **/
/* Identifiers */
res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_HIGH] = 26;
res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_L2_CTXT_LOW] = 26;
res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_WC_PROF] = 32;
res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_PROF_FUNC] = 63;
res->ident_cnt[TF_DIR_TX].cnt[TF_IDENT_TYPE_EM_PROF] = 32;
/* Table Types */
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_FULL_ACT_RECORD] = 1024;
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_STATS_64] = 512;
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 14;
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_EM_FKB] = 32;
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_WC_FKB] = 32;
/* ENCAP */
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_ENCAP_64B] = 64;
/* TCAMs */
tmp_cnt = &res->tcam_cnt[TF_DIR_TX].cnt[0];
tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_HIGH] = 200;
tmp_cnt[TF_TCAM_TBL_TYPE_L2_CTXT_TCAM_LOW] = 110;
res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_PROF_TCAM] = 128;
res->tcam_cnt[TF_DIR_TX].cnt[TF_TCAM_TBL_TYPE_WC_TCAM] = 128;
/* EM */
res->em_cnt[TF_DIR_TX].cnt[TF_EM_TBL_TYPE_EM_RECORD] = 15232;
/* SP */
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_ACT_SP_SMAC_IPV4] = 100;
res->tbl_cnt[TF_DIR_TX].cnt[TF_TBL_TYPE_MIRROR_CONFIG] = 1;
break;
default:
return -EINVAL;
@ -273,6 +350,9 @@ ulp_ctx_session_open(struct bnxt *bp,
case BNXT_ULP_DEVICE_ID_STINGRAY:
params.device_type = TF_DEVICE_TYPE_SR;
break;
case BNXT_ULP_DEVICE_ID_THOR:
params.device_type = TF_DEVICE_TYPE_THOR;
break;
default:
BNXT_TF_DBG(ERR, "Unable to determine device for "
"opening session.\n");
@ -346,14 +426,12 @@ bnxt_init_tbl_scope_parms(struct bnxt *bp,
BNXT_ULP_DFLT_RX_MAX_ACTN_ENTRY;
params->rx_mem_size_in_mb = BNXT_ULP_DFLT_RX_MEM;
params->rx_num_flows_in_k = BNXT_ULP_RX_NUM_FLOWS;
params->rx_tbl_if_id = BNXT_ULP_RX_TBL_IF_ID;
params->tx_max_key_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_KEY;
params->tx_max_action_entry_sz_in_bits =
BNXT_ULP_DFLT_TX_MAX_ACTN_ENTRY;
params->tx_mem_size_in_mb = BNXT_ULP_DFLT_TX_MEM;
params->tx_num_flows_in_k = BNXT_ULP_TX_NUM_FLOWS;
params->tx_tbl_if_id = BNXT_ULP_TX_TBL_IF_ID;
} else {
params->rx_max_key_sz_in_bits = BNXT_ULP_DFLT_RX_MAX_KEY;
params->rx_max_action_entry_sz_in_bits =
@ -361,7 +439,6 @@ bnxt_init_tbl_scope_parms(struct bnxt *bp,
params->rx_mem_size_in_mb = BNXT_ULP_DFLT_RX_MEM;
params->rx_num_flows_in_k =
dparms->ext_flow_db_num_entries / 1024;
params->rx_tbl_if_id = BNXT_ULP_RX_TBL_IF_ID;
params->tx_max_key_sz_in_bits = BNXT_ULP_DFLT_TX_MAX_KEY;
params->tx_max_action_entry_sz_in_bits =
@ -369,7 +446,6 @@ bnxt_init_tbl_scope_parms(struct bnxt *bp,
params->tx_mem_size_in_mb = BNXT_ULP_DFLT_TX_MEM;
params->tx_num_flows_in_k =
dparms->ext_flow_db_num_entries / 1024;
params->tx_tbl_if_id = BNXT_ULP_TX_TBL_IF_ID;
}
BNXT_TF_DBG(INFO, "Table Scope initialized with %uK flows.\n",
params->rx_num_flows_in_k);
@ -530,6 +606,8 @@ ulp_ctx_init(struct bnxt *bp,
if (rc)
goto error_deinit;
ulp_tun_tbl_init(ulp_data->tun_tbl);
bnxt_ulp_cntxt_tfp_set(bp->ulp_ctx, &bp->tfp);
return rc;
@ -827,8 +905,7 @@ bnxt_ulp_destroy_vfr_default_rules(struct bnxt *bp, bool global)
continue;
/* Destroy the flows */
ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id);
ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id);
ulp_default_flow_destroy(bp->eth_dev, info->vfr_flow_id);
/* Clean up the tx action pointer */
vfr_eth_dev = &rte_eth_devices[port_id];
if (vfr_eth_dev) {
@ -1071,7 +1148,11 @@ bnxt_ulp_port_init(struct bnxt *bp)
goto jump_to_error;
}
/* create the default rules */
bnxt_ulp_create_df_rules(bp);
rc = bnxt_ulp_create_df_rules(bp);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to create default flow\n");
goto jump_to_error;
}
if (BNXT_ACCUM_STATS_EN(bp))
bp->ulp_ctx->cfg_data->accum_stats = true;

7
drivers/net/bnxt/tf_ulp/bnxt_ulp.h
View File

@ -10,6 +10,7 @@
#include <stdbool.h>
#include <sys/queue.h>
#include "rte_version.h"
#include "rte_ethdev.h"
#include "ulp_template_db_enum.h"
@ -38,14 +39,12 @@ enum bnxt_ulp_flow_mem_type {
};
struct bnxt_ulp_df_rule_info {
uint32_t port_to_app_flow_id;
uint32_t app_to_port_flow_id;
uint32_t def_port_flow_id;
uint8_t valid;
};
struct bnxt_ulp_vfr_rule_info {
uint32_t rep2vf_flow_id;
uint32_t vf2rep_flow_id;
uint32_t vfr_flow_id;
uint16_t parent_port_id;
uint8_t valid;
};

4
drivers/net/bnxt/tf_ulp/bnxt_ulp_flow.c
View File

@ -70,8 +70,10 @@ bnxt_ulp_set_dir_attributes(struct ulp_rte_parser_params *params,
params->dir_attr |= BNXT_ULP_FLOW_ATTR_EGRESS;
if (attr->ingress)
params->dir_attr |= BNXT_ULP_FLOW_ATTR_INGRESS;
#if RTE_VERSION_NUM(17, 11, 10, 16) < RTE_VERSION
if (attr->transfer)
params->dir_attr |= BNXT_ULP_FLOW_ATTR_TRANSFER;
#endif
}
void
@ -79,6 +81,7 @@ bnxt_ulp_init_mapper_params(struct bnxt_ulp_mapper_create_parms *mapper_cparms,
struct ulp_rte_parser_params *params,
enum bnxt_ulp_fdb_type flow_type)
{
memset(mapper_cparms, 0, sizeof(*mapper_cparms));
mapper_cparms->flow_type = flow_type;
mapper_cparms->app_priority = params->priority;
mapper_cparms->dir_attr = params->dir_attr;
@ -186,6 +189,7 @@ bnxt_ulp_flow_create(struct rte_eth_dev *dev,
params.fid = fid;
params.func_id = func_id;
params.priority = attr->priority;
params.port_id = dev->data->port_id;
/* Perform the rte flow post process */
ret = bnxt_ulp_rte_parser_post_process(&params);
if (ret == BNXT_TF_RC_ERROR)

4
drivers/net/bnxt/tf_ulp/meson.build
View File

@ -27,5 +27,5 @@ sources += files(
'ulp_rte_handler_tbl.c',
'ulp_template_db_wh_plus_act.c',
'ulp_template_db_wh_plus_class.c',
'ulp_template_db_stingray_act.c',
'ulp_template_db_stingray_class.c')
'ulp_template_db_thor_act.c',
'ulp_template_db_thor_class.c')

65
drivers/net/bnxt/tf_ulp/ulp_def_rules.c
View File

@ -457,9 +457,7 @@ bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global)
return;
ulp_default_flow_destroy(bp->eth_dev,
info->port_to_app_flow_id);
ulp_default_flow_destroy(bp->eth_dev,
info->app_to_port_flow_id);
info->def_port_flow_id);
memset(info, 0, sizeof(struct bnxt_ulp_df_rule_info));
return;
}
@ -471,9 +469,7 @@ bnxt_ulp_destroy_df_rules(struct bnxt *bp, bool global)
continue;
ulp_default_flow_destroy(bp->eth_dev,
info->port_to_app_flow_id);
ulp_default_flow_destroy(bp->eth_dev,
info->app_to_port_flow_id);
info->def_port_flow_id);
memset(info, 0, sizeof(struct bnxt_ulp_df_rule_info));
}
}
@ -496,6 +492,10 @@ bnxt_create_port_app_df_rule(struct bnxt *bp, uint8_t flow_type,
}
};
if (!flow_type) {
*flow_id = 0;
return 0;
}
return ulp_default_flow_create(bp->eth_dev, param_list, flow_type,
flow_id);
}
@ -505,7 +505,7 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
{
struct bnxt_ulp_df_rule_info *info;
uint8_t port_id;
int rc;
int rc = 0;
if (!BNXT_TRUFLOW_EN(bp) ||
BNXT_ETH_DEV_IS_REPRESENTOR(bp->eth_dev) || !bp->ulp_ctx)
@ -513,39 +513,22 @@ bnxt_ulp_create_df_rules(struct bnxt *bp)
port_id = bp->eth_dev->data->port_id;
info = &bp->ulp_ctx->cfg_data->df_rule_info[port_id];
rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_PORT_TO_VS,
&info->port_to_app_flow_id);
rc = bnxt_create_port_app_df_rule(bp,
BNXT_ULP_DF_TPL_DEFAULT_UPLINK_PORT,
&info->def_port_flow_id);
if (rc) {
BNXT_TF_DBG(ERR,
"Failed to create port to app default rule\n");
return rc;
}
bp->tx_cfa_action = 0;
rc = bnxt_create_port_app_df_rule(bp, BNXT_ULP_DF_TPL_VS_TO_PORT,
&info->app_to_port_flow_id);
if (rc) {
BNXT_TF_DBG(ERR,
"Failed to create app to port default rule\n");
goto port_to_app_free;
}
rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
info->app_to_port_flow_id,
info->def_port_flow_id,
&bp->tx_cfa_action);
if (rc)
goto app_to_port_free;
bp->tx_cfa_action = 0;
info->valid = true;
return 0;
app_to_port_free:
ulp_default_flow_destroy(bp->eth_dev, info->app_to_port_flow_id);
port_to_app_free:
ulp_default_flow_destroy(bp->eth_dev, info->port_to_app_flow_id);
info->valid = false;
return rc;
}
static int32_t
@ -598,22 +581,15 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev)
}
memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info));
rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_VFREP_TO_VF,
rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_DEFAULT_VFR,
vfr_port_id,
&info->rep2vf_flow_id);
&info->vfr_flow_id);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to create VFREP to VF default rule\n");
goto error;
}
rc = bnxt_create_port_vfr_default_rule(bp, BNXT_ULP_DF_TPL_VF_TO_VFREP,
vfr_port_id,
&info->vf2rep_flow_id);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to create VF to VFREP default rule\n");
BNXT_TF_DBG(ERR, "Failed to create VFR default rule\n");
goto error;
}
rc = ulp_default_flow_db_cfa_action_get(bp->ulp_ctx,
info->rep2vf_flow_id,
info->vfr_flow_id,
&vfr->vfr_tx_cfa_action);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to get the tx cfa action\n");
@ -626,10 +602,8 @@ bnxt_ulp_create_vfr_default_rules(struct rte_eth_dev *vfr_ethdev)
return 0;
error:
if (info->rep2vf_flow_id)
ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id);
if (info->vf2rep_flow_id)
ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id);
if (info->vfr_flow_id)
ulp_default_flow_destroy(bp->eth_dev, info->vfr_flow_id);
return rc;
}
@ -653,8 +627,7 @@ bnxt_ulp_delete_vfr_default_rules(struct bnxt_representor *vfr)
BNXT_TF_DBG(ERR, "VFR already freed\n");
return -EINVAL;
}
ulp_default_flow_destroy(bp->eth_dev, info->rep2vf_flow_id);
ulp_default_flow_destroy(bp->eth_dev, info->vf2rep_flow_id);
ulp_default_flow_destroy(bp->eth_dev, info->vfr_flow_id);
vfr->vfr_tx_cfa_action = 0;
memset(info, 0, sizeof(struct bnxt_ulp_vfr_rule_info));
return 0;

18
drivers/net/bnxt/tf_ulp/ulp_fc_mgr.c
View File

@ -80,6 +80,12 @@ ulp_fc_mgr_init(struct bnxt_ulp_context *ctxt)
return -EINVAL;
}
if (!dparms->flow_count_db_entries) {
BNXT_TF_DBG(DEBUG, "flow counter support is not enabled\n");
bnxt_ulp_cntxt_ptr2_fc_info_set(ctxt, NULL);
return 0;
}
ulp_fc_info = rte_zmalloc("ulp_fc_info", sizeof(*ulp_fc_info), 0);
if (!ulp_fc_info)
goto error;
@ -169,7 +175,10 @@ bool ulp_fc_mgr_thread_isstarted(struct bnxt_ulp_context *ctxt)
ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
return !!(ulp_fc_info->flags & ULP_FLAG_FC_THREAD);
if (ulp_fc_info)
return !!(ulp_fc_info->flags & ULP_FLAG_FC_THREAD);
return false;
}
/*
@ -186,7 +195,7 @@ ulp_fc_mgr_thread_start(struct bnxt_ulp_context *ctxt)
ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
if (!(ulp_fc_info->flags & ULP_FLAG_FC_THREAD)) {
if (ulp_fc_info && !(ulp_fc_info->flags & ULP_FLAG_FC_THREAD)) {
rte_eal_alarm_set(US_PER_S * ULP_FC_TIMER,
ulp_fc_mgr_alarm_cb,
(void *)ctxt);
@ -459,7 +468,10 @@ bool ulp_fc_mgr_start_idx_isset(struct bnxt_ulp_context *ctxt, enum tf_dir dir)
ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ctxt);
return ulp_fc_info->shadow_hw_tbl[dir].start_idx_is_set;
if (ulp_fc_info)
return ulp_fc_info->shadow_hw_tbl[dir].start_idx_is_set;
return false;
}
/*

9
drivers/net/bnxt/tf_ulp/ulp_flow_db.c
View File

@ -522,7 +522,9 @@ ulp_flow_db_init(struct bnxt_ulp_context *ulp_ctxt)
bnxt_ulp_cntxt_ptr2_flow_db_set(ulp_ctxt, flow_db);
/* Determine the number of flows based on EM type */
bnxt_ulp_cntxt_mem_type_get(ulp_ctxt, &mtype);
if (bnxt_ulp_cntxt_mem_type_get(ulp_ctxt, &mtype))
goto error_free;
if (mtype == BNXT_ULP_FLOW_MEM_TYPE_INT)
num_flows = dparms->int_flow_db_num_entries;
else
@ -676,6 +678,7 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
struct bnxt_ulp_flow_db *flow_db;
struct bnxt_ulp_flow_tbl *flow_tbl;
struct ulp_fdb_resource_info *resource, *fid_resource;
struct bnxt_ulp_fc_info *ulp_fc_info;
uint32_t idx;
flow_db = bnxt_ulp_cntxt_ptr2_flow_db_get(ulp_ctxt);
@ -728,9 +731,11 @@ ulp_flow_db_resource_add(struct bnxt_ulp_context *ulp_ctxt,
ulp_flow_db_res_params_to_info(fid_resource, params);
}
ulp_fc_info = bnxt_ulp_cntxt_ptr2_fc_info_get(ulp_ctxt);
if (params->resource_type == TF_TBL_TYPE_ACT_STATS_64 &&
params->resource_sub_type ==
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT) {
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT &&
ulp_fc_info) {
/* Store the first HW counter ID for this table */
if (!ulp_fc_mgr_start_idx_isset(ulp_ctxt, params->direction))
ulp_fc_mgr_start_idx_set(ulp_ctxt, params->direction,

24
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.c
View File

@ -246,8 +246,28 @@ ulp_mapper_gen_tbl_entry_data_get(struct ulp_mapper_gen_tbl_entry *entry,
return 0;
}
/*
* Free the generic table list entry
/* Free the generic table list entry
*
* ulp_ctx [in] - Pointer to the ulp context
* tbl_idx [in] - Index of the generic table
* ckey [in] - Key for the entry in the table
*
* returns 0 on success
*/
int32_t
ulp_mapper_gen_tbl_entry_free(struct bnxt_ulp_context *ulp_ctx,
uint32_t tbl_idx, uint32_t ckey)
{
struct ulp_flow_db_res_params res;
res.direction = tbl_idx & 0x1;
res.resource_sub_type = tbl_idx >> 1;
res.resource_hndl = ckey;
return ulp_mapper_gen_tbl_res_free(ulp_ctx, &res);
}
/* Free the generic table list resource
*
* ulp_ctx [in] - Pointer to the ulp context
* res [in] - Pointer to flow db resource entry

14
drivers/net/bnxt/tf_ulp/ulp_gen_tbl.h
View File

@ -131,7 +131,7 @@ ulp_mapper_gen_tbl_entry_data_get(struct ulp_mapper_gen_tbl_entry *entry,
uint32_t data_size);
/*
* Free the generic table list entry
* Free the generic table list resource
*
* ulp_ctx [in] - Pointer to the ulp context
* res [in] - Pointer to flow db resource entry
@ -142,6 +142,18 @@ int32_t
ulp_mapper_gen_tbl_res_free(struct bnxt_ulp_context *ulp_ctx,
struct ulp_flow_db_res_params *res);
/* Free the generic table list entry
*
* ulp_ctx [in] - Pointer to the ulp context
* tbl_idx [in] - Index of the generic table
* ckey [in] - Key for the entry in the table
*
* returns 0 on success
*/
int32_t
ulp_mapper_gen_tbl_entry_free(struct bnxt_ulp_context *ulp_ctx,
uint32_t tbl_idx, uint32_t ckey);
/*
* Write the generic table list hash entry
*

408
drivers/net/bnxt/tf_ulp/ulp_mapper.c
View File

@ -200,16 +200,6 @@ ulp_mapper_resource_index_tbl_alloc(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
/* Retrieve the global template table */
static uint32_t *
ulp_mapper_glb_template_table_get(uint32_t *num_entries)
{
if (!num_entries)
return NULL;
*num_entries = BNXT_ULP_GLB_TEMPLATE_TBL_MAX_SZ;
return ulp_glb_template_tbl;
}
static int32_t
ulp_mapper_glb_field_tbl_get(struct bnxt_ulp_mapper_parms *parms,
uint32_t operand,
@ -896,6 +886,20 @@ ulp_mapper_field_port_db_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
break;
case BNXT_ULP_PORT_TABLE_DRV_FUNC_MAC:
if (ulp_port_db_drv_mac_addr_get(parms->ulp_ctx, port_id,
val)) {
BNXT_TF_DBG(ERR, "Invalid port id %u\n", port_id);
return -EINVAL;
}
break;
case BNXT_ULP_PORT_TABLE_DRV_FUNC_PARENT_VNIC:
if (ulp_port_db_parent_vnic_get(parms->ulp_ctx, port_id,
val)) {
BNXT_TF_DBG(ERR, "Invalid port id %u\n", port_id);
return -EINVAL;
}
break;
default:
BNXT_TF_DBG(ERR, "Invalid port_data %s\n", fld->description);
return -EINVAL;
@ -1676,18 +1680,11 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
sparms.dir = tbl->direction;
sparms.tcam_tbl_type = tbl->resource_type;
sparms.idx = idx;
/* Already verified the key/mask lengths */
sparms.key = ulp_blob_data_get(key, &tmplen);
sparms.key_sz_in_bits = tmplen;
sparms.mask = ulp_blob_data_get(mask, &tmplen);
sparms.key_sz_in_bits = tbl->key_bit_size;
sparms.result = ulp_blob_data_get(data, &tmplen);
if (tbl->result_bit_size != tmplen) {
BNXT_TF_DBG(ERR, "Result len (%d) != Expected (%d)\n",
tmplen, tbl->result_bit_size);
return -EINVAL;
}
sparms.result_sz_in_bits = tbl->result_bit_size;
sparms.result_sz_in_bits = tmplen;
if (tf_set_tcam_entry(tfp, &sparms)) {
BNXT_TF_DBG(ERR, "tcam[%s][%s][%x] write failed.\n",
tf_tcam_tbl_2_str(sparms.tcam_tbl_type),
@ -1705,6 +1702,103 @@ ulp_mapper_tcam_tbl_entry_write(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
/*
* internal function to post process key/mask blobs for dynamic pad WC tcam tbl
*
* parms [in] The mappers parms with data related to the flow.
*
* key [in] The original key to be transformed
*
* mask [in] The original mask to be transformed
*
* tkey [in/out] The transformed key
*
* tmask [in/out] The transformed mask
*
* returns zero on success, non-zero on failure
*/
static uint32_t
ulp_mapper_wc_tcam_tbl_dyn_post_process(struct bnxt_ulp_device_params *dparms,
struct ulp_blob *key,
struct ulp_blob *mask,
struct ulp_blob *tkey,
struct ulp_blob *tmask)
{
uint16_t tlen, blen, clen, slice_width, num_slices, max_slices, offset;
uint32_t cword, i, rc;
int32_t pad;
uint8_t *val;
slice_width = dparms->wc_slice_width;
clen = dparms->wc_ctl_size_bits;
max_slices = dparms->wc_max_slices;
blen = ulp_blob_data_len_get(key);
/* Get the length of the key based on number of slices and width */
num_slices = 1;
tlen = slice_width;
while (tlen < blen &&
num_slices <= max_slices) {
num_slices = num_slices << 1;
tlen = tlen << 1;
}
if (num_slices > max_slices) {
BNXT_TF_DBG(ERR, "Key size (%d) too large for WC\n", blen);
return -EINVAL;
}
/* The key/mask may not be on a natural slice boundary, pad it */
pad = tlen - blen;
if (ulp_blob_pad_push(key, pad) < 0 ||
ulp_blob_pad_push(mask, pad) < 0) {
BNXT_TF_DBG(ERR, "Unable to pad key/mask\n");
return -EINVAL;
}
/* The new length accounts for the ctrl word length and num slices */
tlen = tlen + clen * num_slices;
if (!ulp_blob_init(tkey, tlen, key->byte_order) ||
!ulp_blob_init(tmask, tlen, mask->byte_order)) {
BNXT_TF_DBG(ERR, "Unable to post process wc tcam entry\n");
return -EINVAL;
}
/* Build the transformed key/mask */
cword = dparms->wc_mode_list[num_slices - 1];
cword = tfp_cpu_to_be_32(cword);
offset = 0;
for (i = 0; i < num_slices; i++) {
val = ulp_blob_push_32(tkey, &cword, clen);
if (!val) {
BNXT_TF_DBG(ERR, "Key ctrl word push failed\n");
return -EINVAL;
}
val = ulp_blob_push_32(tmask, &cword, clen);
if (!val) {
BNXT_TF_DBG(ERR, "Mask ctrl word push failed\n");
return -EINVAL;
}
rc = ulp_blob_append(tkey, key, offset, slice_width);
if (rc) {
BNXT_TF_DBG(ERR, "Key blob append failed\n");
return rc;
}
rc = ulp_blob_append(tmask, mask, offset, slice_width);
if (rc) {
BNXT_TF_DBG(ERR, "Mask blob append failed\n");
return rc;
}
offset += slice_width;
}
/* The key/mask are byte reversed on every 4 byte chunk */
ulp_blob_perform_byte_reverse(tkey, 4);
ulp_blob_perform_byte_reverse(tmask, 4);
return 0;
}
/* internal function to post process the key/mask blobs for wildcard tcam tbl */
static void ulp_mapper_wc_tcam_tbl_post_process(struct ulp_blob *blob)
{
@ -1717,10 +1811,13 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct bnxt_ulp_mapper_tbl_info *tbl)
{
struct bnxt_ulp_mapper_key_info *kflds;
struct ulp_blob key, mask, data, update_data;
struct ulp_blob okey, omask, data, update_data;
struct ulp_blob tkey, tmask; /* transform key and mask */
struct ulp_blob *key, *mask;
uint32_t i, num_kflds;
struct tf *tfp;
int32_t rc, trc;
struct bnxt_ulp_device_params *dparms = parms->device_params;
struct tf_alloc_tcam_entry_parms aparms = { 0 };
struct tf_search_tcam_entry_parms searchparms = { 0 };
struct ulp_flow_db_res_params fid_parms = { 0 };
@ -1729,6 +1826,10 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
uint16_t tmplen = 0;
uint16_t idx;
/* Set the key and mask to the original key and mask. */
key = &okey;
mask = &omask;
/* Skip this if table opcode is NOP */
if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_NOT_USED ||
tbl->tbl_opcode >= BNXT_ULP_TCAM_TBL_OPC_LAST) {
@ -1749,23 +1850,15 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
parms->device_params->byte_order) ||
!ulp_blob_init(&mask, tbl->blob_key_bit_size,
parms->device_params->byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
parms->device_params->byte_order) ||
if (!ulp_blob_init(key, tbl->blob_key_bit_size, tbl->byte_order) ||
!ulp_blob_init(mask, tbl->blob_key_bit_size, tbl->byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size, dparms->byte_order) ||
!ulp_blob_init(&update_data, tbl->result_bit_size,
parms->device_params->byte_order)) {
dparms->byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) {
key.byte_order = BNXT_ULP_BYTE_ORDER_BE;
mask.byte_order = BNXT_ULP_BYTE_ORDER_BE;
}
/* create the key/mask */
/*
* NOTE: The WC table will require some kind of flag to handle the
@ -1775,7 +1868,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Setup the key */
rc = ulp_mapper_field_process(parms, tbl->direction,
&kflds[i].field_info_spec,
&key, 1, "TCAM Key");
key, 1, "TCAM Key");
if (rc) {
BNXT_TF_DBG(ERR, "Key field set failed %s\n",
kflds[i].field_info_spec.description);
@ -1785,7 +1878,7 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Setup the mask */
rc = ulp_mapper_field_process(parms, tbl->direction,
&kflds[i].field_info_mask,
&mask, 0, "TCAM Mask");
mask, 0, "TCAM Mask");
if (rc) {
BNXT_TF_DBG(ERR, "Mask field set failed %s\n",
kflds[i].field_info_mask.description);
@ -1795,28 +1888,34 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* For wild card tcam perform the post process to swap the blob */
if (tbl->resource_type == TF_TCAM_TBL_TYPE_WC_TCAM) {
ulp_mapper_wc_tcam_tbl_post_process(&key);
ulp_mapper_wc_tcam_tbl_post_process(&mask);
if (dparms->dynamic_pad_en) {
/* Sets up the slices for writing to the WC TCAM */
rc = ulp_mapper_wc_tcam_tbl_dyn_post_process(dparms,
key, mask,
&tkey,
&tmask);
if (rc) {
BNXT_TF_DBG(ERR,
"Failed to post proc WC entry.\n");
return rc;
}
/* Now need to use the transform Key/Mask */
key = &tkey;
mask = &tmask;
} else {
ulp_mapper_wc_tcam_tbl_post_process(key);
ulp_mapper_wc_tcam_tbl_post_process(mask);
}
}
if (tbl->tbl_opcode == BNXT_ULP_TCAM_TBL_OPC_ALLOC_WR_REGFILE) {
/* allocate the tcam index */
aparms.dir = tbl->direction;
aparms.tcam_tbl_type = tbl->resource_type;
aparms.key = ulp_blob_data_get(&key, &tmplen);
aparms.key = ulp_blob_data_get(key, &tmplen);
aparms.key_sz_in_bits = tmplen;
if (tbl->blob_key_bit_size != tmplen) {
BNXT_TF_DBG(ERR, "Key len (%d) != Expected (%d)\n",
tmplen, tbl->blob_key_bit_size);
return -EINVAL;
}
aparms.mask = ulp_blob_data_get(&mask, &tmplen);
if (tbl->blob_key_bit_size != tmplen) {
BNXT_TF_DBG(ERR, "Mask len (%d) != Expected (%d)\n",
tmplen, tbl->blob_key_bit_size);
return -EINVAL;
}
aparms.mask = ulp_blob_data_get(mask, &tmplen);
/* calculate the entry priority */
rc = ulp_mapper_priority_opc_process(parms, tbl,
@ -1840,9 +1939,9 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
*/
searchparms.dir = tbl->direction;
searchparms.tcam_tbl_type = tbl->resource_type;
searchparms.key = ulp_blob_data_get(&key, &tmplen);
searchparms.key = ulp_blob_data_get(key, &tmplen);
searchparms.key_sz_in_bits = tbl->key_bit_size;
searchparms.mask = ulp_blob_data_get(&mask, &tmplen);
searchparms.mask = ulp_blob_data_get(mask, &tmplen);
searchparms.alloc = 1;
searchparms.result = ulp_blob_data_get(&data, &tmplen);
searchparms.result_sz_in_bits = tbl->result_bit_size;
@ -1890,8 +1989,8 @@ ulp_mapper_tcam_tbl_process(struct bnxt_ulp_mapper_parms *parms,
"TCAM Result");
/* write the tcam entry */
if (!rc)
rc = ulp_mapper_tcam_tbl_entry_write(parms, tbl, &key,
&mask, &data, idx);
rc = ulp_mapper_tcam_tbl_entry_write(parms, tbl, key,
mask, &data, idx);
} else {
/*Scan identifier list, extract identifier and update regfile*/
rc = ulp_mapper_tcam_tbl_scan_ident_extract(parms, tbl, &data);
@ -1938,8 +2037,10 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct tf_insert_em_entry_parms iparms = { 0 };
struct tf_delete_em_entry_parms free_parms = { 0 };
enum bnxt_ulp_flow_mem_type mtype;
struct bnxt_ulp_device_params *dparms = parms->device_params;
int32_t trc;
int32_t rc = 0;
int32_t pad = 0;
rc = bnxt_ulp_cntxt_mem_type_get(parms->ulp_ctx, &mtype);
if (rc) {
@ -1955,9 +2056,9 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
/* Initialize the key/result blobs */
if (!ulp_blob_init(&key, tbl->blob_key_bit_size,
parms->device_params->byte_order) ||
tbl->byte_order) ||
!ulp_blob_init(&data, tbl->result_bit_size,
parms->device_params->byte_order)) {
tbl->byte_order)) {
BNXT_TF_DBG(ERR, "blob inits failed.\n");
return -EINVAL;
}
@ -1974,10 +2075,19 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
}
/*
* TBD: Normally should process identifiers in case of using recycle or
* loopback. Not supporting recycle for now.
*/
/* if dynamic padding is enabled then add padding to result data */
if (dparms->dynamic_pad_en) {
/* add padding to make sure key is at byte boundary */
ulp_blob_pad_align(&key, ULP_BUFFER_ALIGN_8_BITS);
/* add the pad */
pad = dparms->em_blk_align_bits - dparms->em_blk_size_bits;
if (pad < 0) {
BNXT_TF_DBG(ERR, "Invalid em blk size and align\n");
return -EINVAL;
}
ulp_blob_pad_push(&data, (uint32_t)pad);
}
/* Create the result data blob */
rc = ulp_mapper_tbl_result_build(parms, tbl, &data, "EM Result");
@ -1985,9 +2095,33 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
BNXT_TF_DBG(ERR, "Failed to build the result blob\n");
return rc;
}
if (dparms->dynamic_pad_en) {
uint32_t abits = dparms->em_blk_align_bits;
/* when dynamic padding is enabled merge result + key */
rc = ulp_blob_block_merge(&data, &key, abits, pad);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to merge the result blob\n");
return rc;
}
/* add padding to make sure merged result is at slice boundary*/
ulp_blob_pad_align(&data, abits);
ulp_blob_perform_byte_reverse(&data, ULP_BITS_2_BYTE(abits));
}
/* do the transpose for the internal EM keys */
if (tbl->resource_type == TF_MEM_INTERNAL)
ulp_blob_perform_byte_reverse(&key);
if (tbl->resource_type == TF_MEM_INTERNAL) {
if (dparms->em_key_align_bytes) {
int32_t b = ULP_BYTE_2_BITS(dparms->em_key_align_bytes);
tmplen = ulp_blob_data_len_get(&key);
ulp_blob_pad_push(&key, b - tmplen);
}
tmplen = ulp_blob_data_len_get(&key);
ulp_blob_perform_byte_reverse(&key, ULP_BITS_2_BYTE(tmplen));
}
rc = bnxt_ulp_cntxt_tbl_scope_id_get(parms->ulp_ctx,
&iparms.tbl_scope_id);
@ -2006,7 +2140,10 @@ ulp_mapper_em_tbl_process(struct bnxt_ulp_mapper_parms *parms,
iparms.key = ulp_blob_data_get(&key, &tmplen);
iparms.key_sz_in_bits = tbl->key_bit_size;
iparms.em_record = ulp_blob_data_get(&data, &tmplen);
iparms.em_record_sz_in_bits = tbl->result_bit_size;
if (tbl->result_bit_size)
iparms.em_record_sz_in_bits = tbl->result_bit_size;
else
iparms.em_record_sz_in_bits = tmplen;
rc = tf_insert_em_entry(tfp, &iparms);
if (rc) {
@ -2064,19 +2201,19 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
struct ulp_blob data;
uint64_t regval = 0;
uint16_t tmplen;
uint32_t index, hit;
uint32_t index;
int32_t rc = 0, trc = 0;
struct tf_alloc_tbl_entry_parms aparms = { 0 };
struct tf_search_tbl_entry_parms srchparms = { 0 };
struct tf_set_tbl_entry_parms sparms = { 0 };
struct tf_get_tbl_entry_parms gparms = { 0 };
struct tf_free_tbl_entry_parms free_parms = { 0 };
uint32_t tbl_scope_id;
struct tf *tfp = bnxt_ulp_cntxt_tfp_get(parms->ulp_ctx);
struct bnxt_ulp_glb_resource_info glb_res;
uint16_t bit_size;
bool alloc = false;
bool write = false;
bool search = false;
bool global = false;
uint64_t act_rec_size;
/* use the max size if encap is enabled */
@ -2111,21 +2248,6 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
alloc = true;
write = true;
break;
case BNXT_ULP_INDEX_TBL_OPC_SRCH_ALLOC_WR_REGFILE:
if (tbl->resource_type == TF_TBL_TYPE_EXT) {
/* Not currently supporting with EXT */
BNXT_TF_DBG(ERR,
"Ext Table Search Opcode not supported.\n");
return -EINVAL;
}
/*
* Search for the entry in the tf core. If it is hit, save the
* index in the regfile. If it is a miss, Build the entry,
* alloc an index, write the table, and store the data in the
* regfile (same as ALLOC_WR).
*/
search = true;
break;
case BNXT_ULP_INDEX_TBL_OPC_WR_REGFILE:
/*
* get the index to write to from the regfile and then write
@ -2146,6 +2268,19 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
write = true;
break;
case BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_GLB_REGFILE:
/*
* Build the entry, alloc an index, write the table, and store
* the data in the global regfile.
*/
alloc = true;
global = true;
write = true;
glb_res.direction = tbl->direction;
glb_res.resource_func = tbl->resource_func;
glb_res.resource_type = tbl->resource_type;
glb_res.glb_regfile_index = tbl->tbl_operand;
break;
case BNXT_ULP_INDEX_TBL_OPC_WR_GLB_REGFILE:
if (tbl->fdb_opcode != BNXT_ULP_FDB_OPC_NOP) {
BNXT_TF_DBG(ERR, "Template error, wrong fdb opcode\n");
@ -2222,7 +2357,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return -EINVAL;
}
if (write || search) {
if (write) {
/* Get the result fields list */
rc = ulp_mapper_tbl_result_build(parms,
tbl,
@ -2234,36 +2369,6 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
}
}
if (search) {
/* Use the result blob to perform a search */
memset(&srchparms, 0, sizeof(srchparms));
srchparms.dir = tbl->direction;
srchparms.type = tbl->resource_type;
srchparms.alloc = 1;
srchparms.result = ulp_blob_data_get(&data, &tmplen);
srchparms.result_sz_in_bytes = ULP_BITS_2_BYTE(tmplen);
srchparms.tbl_scope_id = tbl_scope_id;
rc = tf_search_tbl_entry(tfp, &srchparms);
if (rc) {
BNXT_TF_DBG(ERR, "Alloc table[%s][%s] failed rc=%d\n",
tf_tbl_type_2_str(tbl->resource_type),
tf_dir_2_str(tbl->direction), rc);
return rc;
}
if (srchparms.search_status == REJECT) {
BNXT_TF_DBG(ERR, "Alloc table[%s][%s] rejected.\n",
tf_tbl_type_2_str(tbl->resource_type),
tf_dir_2_str(tbl->direction));
return -ENOMEM;
}
index = srchparms.idx;
hit = srchparms.hit;
if (hit)
write = false;
else
write = true;
}
if (alloc) {
aparms.dir = tbl->direction;
aparms.type = tbl->resource_type;
@ -2278,9 +2383,7 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
return rc;
}
index = aparms.idx;
}
if (search || alloc) {
/*
* Store the index in the regfile since we either allocated it
* or it was a hit.
@ -2294,12 +2397,19 @@ ulp_mapper_index_tbl_process(struct bnxt_ulp_mapper_parms *parms,
regval = TF_ACT_REC_OFFSET_2_PTR(index);
else
regval = index;
regval = tfp_cpu_to_be_64(regval);
rc = ulp_regfile_write(parms->regfile,
tbl->tbl_operand,
tfp_cpu_to_be_64(regval));
if (global) {
rc = ulp_mapper_glb_resource_write(parms->mapper_data,
&glb_res, regval);
} else {
rc = ulp_regfile_write(parms->regfile,
tbl->tbl_operand, regval);
}
if (rc) {
BNXT_TF_DBG(ERR, "Failed to write regfile[%d] rc=%d\n",
BNXT_TF_DBG(ERR,
"Failed to write %s regfile[%d] rc=%d\n",
(global) ? "global" : "reg",
tbl->tbl_operand, rc);
goto error;
}
@ -3312,62 +3422,6 @@ ulp_mapper_flow_destroy(struct bnxt_ulp_context *ulp_ctx,
return rc;
}
/* Function to handle the default global templates that are allocated during
* the startup and reused later.
*/
static int32_t
ulp_mapper_glb_template_table_init(struct bnxt_ulp_context *ulp_ctx)
{
uint32_t *glbl_tmpl_list;
uint32_t num_glb_tmpls, idx, dev_id;
struct bnxt_ulp_mapper_parms parms;
struct bnxt_ulp_mapper_data *mapper_data;
int32_t rc = 0;
glbl_tmpl_list = ulp_mapper_glb_template_table_get(&num_glb_tmpls);
if (!glbl_tmpl_list || !num_glb_tmpls)
return rc; /* No global templates to process */
/* Get the device id from the ulp context */
if (bnxt_ulp_cntxt_dev_id_get(ulp_ctx, &dev_id)) {
BNXT_TF_DBG(ERR, "Invalid ulp context\n");
return -EINVAL;
}
mapper_data = bnxt_ulp_cntxt_ptr2_mapper_data_get(ulp_ctx);
if (!mapper_data) {
BNXT_TF_DBG(ERR, "Failed to get the ulp mapper data\n");
return -EINVAL;
}
/* Iterate the global resources and process each one */
for (idx = 0; idx < num_glb_tmpls; idx++) {
/* Initialize the parms structure */
memset(&parms, 0, sizeof(parms));
parms.tfp = bnxt_ulp_cntxt_tfp_get(ulp_ctx);
parms.ulp_ctx = ulp_ctx;
parms.dev_id = dev_id;
parms.mapper_data = mapper_data;
parms.flow_type = BNXT_ULP_FDB_TYPE_DEFAULT;
parms.tmpl_type = BNXT_ULP_TEMPLATE_TYPE_CLASS;
/* Get the class table entry from dev id and class id */
parms.class_tid = glbl_tmpl_list[idx];
parms.device_params = bnxt_ulp_device_params_get(parms.dev_id);
if (!parms.device_params) {
BNXT_TF_DBG(ERR, "No device for device id %d\n",
parms.dev_id);
return -EINVAL;
}
rc = ulp_mapper_tbls_process(&parms, parms.class_tid);
if (rc)
return rc;
}
return rc;
}
/* Function to handle the mapping of the Flow to be compatible
* with the underlying hardware.
*/
@ -3442,6 +3496,7 @@ ulp_mapper_flow_create(struct bnxt_ulp_context *ulp_ctx,
rc = ulp_mapper_tbls_process(&parms, parms.act_tid);
if (rc)
goto flow_error;
cparms->shared_hndl = parms.shared_hndl;
}
if (parms.class_tid) {
@ -3520,13 +3575,6 @@ ulp_mapper_init(struct bnxt_ulp_context *ulp_ctx)
goto error;
}
/* Allocate global template table entries */
rc = ulp_mapper_glb_template_table_init(ulp_ctx);
if (rc) {
BNXT_TF_DBG(ERR, "Failed to initialize global templates\n");
goto error;
}
return 0;
error:
/* Ignore the return code in favor of returning the original error. */

7
drivers/net/bnxt/tf_ulp/ulp_mapper.h
View File

@ -82,6 +82,7 @@ struct bnxt_ulp_mapper_create_parms {
/* if set then create a parent flow */
uint32_t parent_flow;
uint8_t tun_idx;
uint64_t shared_hndl;
/* support pattern based rejection */
uint32_t flow_pattern_id;
@ -120,4 +121,10 @@ ulp_mapper_resources_free(struct bnxt_ulp_context *ulp_ctx,
enum bnxt_ulp_fdb_type flow_type,
uint32_t fid);
int32_t
ulp_mapper_get_shared_fid(struct bnxt_ulp_context *ulp,
uint32_t id,
uint16_t key,
uint32_t *fid);
#endif /* _ULP_MAPPER_H_ */

10
drivers/net/bnxt/tf_ulp/ulp_mark_mgr.c
View File

@ -73,6 +73,12 @@ ulp_mark_db_init(struct bnxt_ulp_context *ctxt)
return -EINVAL;
}
if (!dparms->mark_db_lfid_entries || !dparms->mark_db_gfid_entries) {
BNXT_TF_DBG(DEBUG, "mark Table is not allocated\n");
bnxt_ulp_cntxt_ptr2_mark_db_set(ctxt, NULL);
return 0;
}
mark_tbl = rte_zmalloc("ulp_rx_mark_tbl_ptr",
sizeof(struct bnxt_ulp_mark_tbl), 0);
if (!mark_tbl)
@ -182,10 +188,8 @@ ulp_mark_db_mark_get(struct bnxt_ulp_context *ctxt,
return -EINVAL;
mtbl = bnxt_ulp_cntxt_ptr2_mark_db_get(ctxt);
if (!mtbl) {
BNXT_TF_DBG(ERR, "Unable to get Mark Table\n");
if (!mtbl)
return -EINVAL;
}
idx = ulp_mark_db_idx_get(is_gfid, fid, mtbl);

90
drivers/net/bnxt/tf_ulp/ulp_port_db.c
View File

@ -8,6 +8,7 @@
#include "bnxt_vnic.h"
#include "bnxt_tf_common.h"
#include "ulp_port_db.h"
#include "tfp.h"
static uint32_t
ulp_port_db_allocate_ifindex(struct bnxt_ulp_port_db *port_db)
@ -186,6 +187,7 @@ int32_t ulp_port_db_dev_port_intf_update(struct bnxt_ulp_context *ulp_ctxt,
* the kernel. And to send it to the kernel, we need the PF's vnic id.
*/
func->func_parent_vnic = bnxt_get_parent_vnic_id(port_id, intf->type);
func->func_parent_vnic = tfp_cpu_to_be_16(func->func_parent_vnic);
bnxt_get_iface_mac(port_id, intf->type, func->func_mac,
func->func_parent_mac);
@ -587,11 +589,32 @@ ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt,
return 0;
}
/* internal function to get the */
static struct ulp_func_if_info*
ulp_port_db_func_if_info_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id)
{
struct bnxt_ulp_port_db *port_db;
uint16_t func_id;
port_db = bnxt_ulp_cntxt_ptr2_port_db_get(ulp_ctxt);
if (ulp_port_db_port_func_id_get(ulp_ctxt, port_id, &func_id)) {
BNXT_TF_DBG(ERR, "Invalid port_id %x\n", port_id);
return NULL;
}
if (!port_db->ulp_func_id_tbl[func_id].func_valid) {
BNXT_TF_DBG(ERR, "Invalid func_id %x\n", func_id);
return NULL;
}
return &port_db->ulp_func_id_tbl[func_id];
}
/*
* Api to get the parent mac address for a given port id.
*
* ulp_ctxt [in] Ptr to ulp context
* port_id [in].device port id
* port_id [in] device port id
* mac_addr [out] mac address
*
* Returns 0 on success or negative number on failure.
@ -600,19 +623,58 @@ int32_t
ulp_port_db_parent_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint8_t **mac_addr)
{
struct bnxt_ulp_port_db *port_db;
uint16_t func_id;
struct ulp_func_if_info *info;
port_db = bnxt_ulp_cntxt_ptr2_port_db_get(ulp_ctxt);
if (ulp_port_db_port_func_id_get(ulp_ctxt, port_id, &func_id)) {
BNXT_TF_DBG(ERR, "Invalid port_id %x\n", port_id);
return -EINVAL;
info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id);
if (info) {
*mac_addr = info->func_parent_mac;
return 0;
}
if (!port_db->ulp_func_id_tbl[func_id].func_valid) {
BNXT_TF_DBG(ERR, "Invalid func_id %x\n", func_id);
return -ENOENT;
}
*mac_addr = port_db->ulp_func_id_tbl[func_id].func_parent_mac;
return 0;
return -EINVAL;
}
/*
* Api to get the mac address for a given port id.
*
* ulp_ctxt [in] Ptr to ulp context
* port_id [in] device port id
* mac_addr [out] mac address
*
* Returns 0 on success or negative number on failure.
*/
int32_t
ulp_port_db_drv_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint8_t **mac_addr)
{
struct ulp_func_if_info *info;
info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id);
if (info) {
*mac_addr = info->func_mac;
return 0;
}
return -EINVAL;
}
/*
* Api to get the parent vnic for a given port id.
*
* ulp_ctxt [in] Ptr to ulp context
* port_id [in] device port id
* vnic [out] parent vnic
*
* Returns 0 on success or negative number on failure.
*/
int32_t
ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint8_t **vnic)
{
struct ulp_func_if_info *info;
info = ulp_port_db_func_if_info_get(ulp_ctxt, port_id);
if (info) {
*vnic = (uint8_t *)&info->func_parent_vnic;
return 0;
}
return -EINVAL;
}

29
drivers/net/bnxt/tf_ulp/ulp_port_db.h
View File

@ -279,7 +279,7 @@ ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt,
* Api to get the parent mac address for a given port id.
*
* ulp_ctxt [in] Ptr to ulp context
* port_id [in].device port id
* port_id [in] device port id
* mac_addr [out] mac address
*
* Returns 0 on success or negative number on failure.
@ -287,4 +287,31 @@ ulp_port_db_port_func_id_get(struct bnxt_ulp_context *ulp_ctxt,
int32_t
ulp_port_db_parent_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint8_t **mac_addr);
/*
* Api to get the mac address for a given port id.
*
* ulp_ctxt [in] Ptr to ulp context
* port_id [in] device port id
* mac_addr [out] mac address
*
* Returns 0 on success or negative number on failure.
*/
int32_t
ulp_port_db_drv_mac_addr_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint8_t **mac_addr);
/*
* Api to get the parent vnic for a given port id.
*
* ulp_ctxt [in] Ptr to ulp context
* port_id [in] device port id
* vnic [out] parent vnic
*
* Returns 0 on success or negative number on failure.
*/
int32_t
ulp_port_db_parent_vnic_get(struct bnxt_ulp_context *ulp_ctxt,
uint32_t port_id, uint8_t **vnic);
#endif /* _ULP_PORT_DB_H_ */

16
drivers/net/bnxt/tf_ulp/ulp_rte_handler_tbl.c
View File

@ -208,6 +208,10 @@ struct bnxt_ulp_rte_act_info ulp_act_info[] = {
[RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK] = {
.act_type = BNXT_ULP_ACT_TYPE_NOT_SUPPORTED,
.proto_act_func = NULL
},
[RTE_FLOW_ACTION_TYPE_SAMPLE] = {
.act_type = BNXT_ULP_ACT_TYPE_SUPPORTED,
.proto_act_func = ulp_rte_sample_act_handler
}
};
@ -230,8 +234,8 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_ANY] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_item_any_handler
},
[RTE_FLOW_ITEM_TYPE_PF] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
@ -270,8 +274,8 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.proto_hdr_func = ulp_rte_ipv6_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_ICMP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_icmp_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_UDP] = {
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
@ -302,8 +306,8 @@ struct bnxt_ulp_rte_hdr_info ulp_hdr_info[] = {
.proto_hdr_func = NULL
},
[RTE_FLOW_ITEM_TYPE_GRE] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,
.proto_hdr_func = NULL
.hdr_type = BNXT_ULP_HDR_TYPE_SUPPORTED,
.proto_hdr_func = ulp_rte_gre_hdr_handler
},
[RTE_FLOW_ITEM_TYPE_FUZZY] = {
.hdr_type = BNXT_ULP_HDR_TYPE_NOT_SUPPORTED,

150
drivers/net/bnxt/tf_ulp/ulp_rte_parser.c
View File

@ -874,6 +874,32 @@ ulp_rte_l3_proto_type_update(struct ulp_rte_parser_params *param,
BNXT_ULP_HDR_BIT_O_TCP);
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_O_L4, 1);
}
} else if (proto == IPPROTO_GRE) {
ULP_BITMAP_SET(param->hdr_bitmap.bits, BNXT_ULP_HDR_BIT_T_GRE);
} else if (proto == IPPROTO_ICMP) {
if (ULP_COMP_FLD_IDX_RD(param, BNXT_ULP_CF_IDX_L3_TUN))
ULP_BITMAP_SET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_I_ICMP);
else
ULP_BITMAP_SET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_O_ICMP);
}
if (proto) {
if (in_flag) {
ULP_COMP_FLD_IDX_WR(param,
BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
1);
ULP_COMP_FLD_IDX_WR(param,
BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
proto);
} else {
ULP_COMP_FLD_IDX_WR(param,
BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
1);
ULP_COMP_FLD_IDX_WR(param,
BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
proto);
}
}
}
@ -1022,9 +1048,6 @@ ulp_rte_ipv4_hdr_handler(const struct rte_flow_item *item,
if (ipv4_mask)
proto &= ipv4_mask->hdr.next_proto_id;
if (proto == IPPROTO_GRE)
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE);
/* Update the field protocol hdr bitmap */
ulp_rte_l3_proto_type_update(params, proto, inner_flag);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt);
@ -1170,9 +1193,6 @@ ulp_rte_ipv6_hdr_handler(const struct rte_flow_item *item,
if (ipv6_mask)
proto &= ipv6_mask->hdr.proto;
if (proto == IPPROTO_GRE)
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE);
/* Update the field protocol hdr bitmap */
ulp_rte_l3_proto_type_update(params, proto, inner_flag);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_L3_HDR_CNT, ++cnt);
@ -1185,11 +1205,16 @@ static void
ulp_rte_l4_proto_type_update(struct ulp_rte_parser_params *param,
uint16_t dst_port)
{
if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN)) {
if (dst_port == tfp_cpu_to_be_16(ULP_UDP_PORT_VXLAN))
ULP_BITMAP_SET(param->hdr_fp_bit.bits,
BNXT_ULP_HDR_BIT_T_VXLAN);
if (ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_T_VXLAN) ||
ULP_BITMAP_ISSET(param->hdr_bitmap.bits,
BNXT_ULP_HDR_BIT_T_GRE))
ULP_COMP_FLD_IDX_WR(param, BNXT_ULP_CF_IDX_L3_TUN, 1);
}
}
/* Function to handle the parsing of RTE Flow item UDP Header. */
@ -1203,7 +1228,7 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
uint32_t idx = params->field_idx;
uint32_t size;
uint16_t dport = 0;
uint16_t dport = 0, sport = 0;
uint32_t cnt;
cnt = ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L4_HDR_CNT);
@ -1221,6 +1246,7 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
field = ulp_rte_parser_fld_copy(&params->hdr_field[idx],
&udp_spec->hdr.src_port,
size);
sport = udp_spec->hdr.src_port;
size = sizeof(udp_spec->hdr.dst_port);
field = ulp_rte_parser_fld_copy(field,
&udp_spec->hdr.dst_port,
@ -1258,6 +1284,14 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_UDP);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
(uint32_t)rte_be_to_cpu_16(sport));
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
(uint32_t)rte_be_to_cpu_16(dport));
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
IPPROTO_UDP);
if (udp_mask && udp_mask->hdr.src_port)
ULP_COMP_FLD_IDX_WR(params,
BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
@ -1266,10 +1300,17 @@ ulp_rte_udp_hdr_handler(const struct rte_flow_item *item,
ULP_COMP_FLD_IDX_WR(params,
BNXT_ULP_CF_IDX_I_L4_FB_DST_PORT,
1);
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_UDP);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
(uint32_t)rte_be_to_cpu_16(sport));
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
(uint32_t)rte_be_to_cpu_16(dport));
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
IPPROTO_UDP);
if (udp_mask && udp_mask->hdr.src_port)
ULP_COMP_FLD_IDX_WR(params,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
@ -1296,6 +1337,7 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_hdr_field *field;
struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
uint32_t idx = params->field_idx;
uint16_t dport = 0, sport = 0;
uint32_t size;
uint32_t cnt;
@ -1310,10 +1352,12 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
* header fields
*/
if (tcp_spec) {
sport = tcp_spec->hdr.src_port;
size = sizeof(tcp_spec->hdr.src_port);
field = ulp_rte_parser_fld_copy(&params->hdr_field[idx],
&tcp_spec->hdr.src_port,
size);
dport = tcp_spec->hdr.dst_port;
size = sizeof(tcp_spec->hdr.dst_port);
field = ulp_rte_parser_fld_copy(field,
&tcp_spec->hdr.dst_port,
@ -1387,6 +1431,14 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
ULP_BITMAP_ISSET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP)) {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_TCP);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_SRC_PORT,
(uint32_t)rte_be_to_cpu_16(sport));
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L4_DST_PORT,
(uint32_t)rte_be_to_cpu_16(dport));
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_FB_PROTO_ID,
1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_I_L3_PROTO_ID,
IPPROTO_TCP);
if (tcp_mask && tcp_mask->hdr.src_port)
ULP_COMP_FLD_IDX_WR(params,
BNXT_ULP_CF_IDX_I_L4_FB_SRC_PORT,
@ -1398,6 +1450,14 @@ ulp_rte_tcp_hdr_handler(const struct rte_flow_item *item,
} else {
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_TCP);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4, 1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_SRC_PORT,
(uint32_t)rte_be_to_cpu_16(sport));
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L4_DST_PORT,
(uint32_t)rte_be_to_cpu_16(dport));
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_FB_PROTO_ID,
1);
ULP_COMP_FLD_IDX_WR(params, BNXT_ULP_CF_IDX_O_L3_PROTO_ID,
IPPROTO_TCP);
if (tcp_mask && tcp_mask->hdr.src_port)
ULP_COMP_FLD_IDX_WR(params,
BNXT_ULP_CF_IDX_O_L4_FB_SRC_PORT,
@ -1464,6 +1524,7 @@ ulp_rte_vxlan_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with vxlan */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_VXLAN);
ulp_rte_l4_proto_type_update(params, 0);
return BNXT_TF_RC_SUCCESS;
}
@ -1479,11 +1540,6 @@ ulp_rte_gre_hdr_handler(const struct rte_flow_item *item,
uint32_t size;
struct ulp_rte_hdr_field *field;
if (!gre_spec && !gre_mask) {
BNXT_TF_DBG(ERR, "Parse Error: GRE item is invalid\n");
return BNXT_TF_RC_ERROR;
}
if (gre_spec) {
size = sizeof(gre_spec->c_rsvd0_ver);
field = ulp_rte_parser_fld_copy(&params->hdr_field[idx],
@ -1507,6 +1563,7 @@ ulp_rte_gre_hdr_handler(const struct rte_flow_item *item,
/* Update the hdr_bitmap with GRE */
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_T_GRE);
ulp_rte_l4_proto_type_update(params, 0);
return BNXT_TF_RC_SUCCESS;
}
@ -1518,6 +1575,68 @@ ulp_rte_item_any_handler(const struct rte_flow_item *item __rte_unused,
return BNXT_TF_RC_SUCCESS;
}
/* Function to handle the parsing of RTE Flow item ICMP Header. */
int32_t
ulp_rte_icmp_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params)
{
const struct rte_flow_item_icmp *icmp_spec = item->spec;
const struct rte_flow_item_icmp *icmp_mask = item->mask;
struct ulp_rte_hdr_bitmap *hdr_bitmap = &params->hdr_bitmap;
uint32_t idx = params->field_idx;
uint32_t size;
struct ulp_rte_hdr_field *field;
if (icmp_spec) {
size = sizeof(icmp_spec->hdr.icmp_type);
field = ulp_rte_parser_fld_copy(&params->hdr_field[idx],
&icmp_spec->hdr.icmp_type,
size);
size = sizeof(icmp_spec->hdr.icmp_code);
field = ulp_rte_parser_fld_copy(field,
&icmp_spec->hdr.icmp_code,
size);
size = sizeof(icmp_spec->hdr.icmp_cksum);
field = ulp_rte_parser_fld_copy(field,
&icmp_spec->hdr.icmp_cksum,
size);
size = sizeof(icmp_spec->hdr.icmp_ident);
field = ulp_rte_parser_fld_copy(field,
&icmp_spec->hdr.icmp_ident,
size);
size = sizeof(icmp_spec->hdr.icmp_seq_nb);
field = ulp_rte_parser_fld_copy(field,
&icmp_spec->hdr.icmp_seq_nb,
size);
}
if (icmp_mask) {
ulp_rte_prsr_mask_copy(params, &idx,
&icmp_mask->hdr.icmp_type,
sizeof(icmp_mask->hdr.icmp_type));
ulp_rte_prsr_mask_copy(params, &idx,
&icmp_mask->hdr.icmp_code,
sizeof(icmp_mask->hdr.icmp_code));
ulp_rte_prsr_mask_copy(params, &idx,
&icmp_mask->hdr.icmp_cksum,
sizeof(icmp_mask->hdr.icmp_cksum));
ulp_rte_prsr_mask_copy(params, &idx,
&icmp_mask->hdr.icmp_ident,
sizeof(icmp_mask->hdr.icmp_ident));
ulp_rte_prsr_mask_copy(params, &idx,
&icmp_mask->hdr.icmp_seq_nb,
sizeof(icmp_mask->hdr.icmp_seq_nb));
}
/* Add number of GRE header elements */
params->field_idx += BNXT_ULP_PROTO_HDR_ICMP_NUM;
/* Update the hdr_bitmap with ICMP */
if (ULP_COMP_FLD_IDX_RD(params, BNXT_ULP_CF_IDX_L3_TUN))
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_I_ICMP);
else
ULP_BITMAP_SET(hdr_bitmap->bits, BNXT_ULP_HDR_BIT_O_ICMP);
return BNXT_TF_RC_SUCCESS;
}
/* Function to handle the parsing of RTE Flow item void Header */
int32_t
ulp_rte_void_hdr_handler(const struct rte_flow_item *item __rte_unused,
@ -1872,7 +1991,6 @@ ulp_rte_drop_act_handler(const struct rte_flow_action *action_item __rte_unused,
int32_t
ulp_rte_count_act_handler(const struct rte_flow_action *action_item,
struct ulp_rte_parser_params *params)
{
const struct rte_flow_action_count *act_count;
struct ulp_rte_act_prop *act_prop = &params->act_prop;

5
drivers/net/bnxt/tf_ulp/ulp_rte_parser.h
View File

@ -135,6 +135,11 @@ int32_t
ulp_rte_item_any_handler(const struct rte_flow_item *item __rte_unused,
struct ulp_rte_parser_params *params __rte_unused);
/* Function to handle the parsing of RTE Flow item ICMP Header. */
int32_t
ulp_rte_icmp_hdr_handler(const struct rte_flow_item *item,
struct ulp_rte_parser_params *params);
/* Function to handle the parsing of RTE Flow item void Header. */
int32_t
ulp_rte_void_hdr_handler(const struct rte_flow_item *item,

143562
drivers/net/bnxt/tf_ulp/ulp_template_db_class.c
View File

File diff suppressed because it is too large Load Diff

9075
drivers/net/bnxt/tf_ulp/ulp_template_db_enum.h
View File

File diff suppressed because it is too large Load Diff

575
drivers/net/bnxt/tf_ulp/ulp_template_db_field.h
View File

@ -19,6 +19,16 @@ enum bnxt_ulp_glb_hf {
BNXT_ULP_GLB_HF_ID_I_ETH_TYPE,
BNXT_ULP_GLB_HF_ID_T_GRE_VER,
BNXT_ULP_GLB_HF_ID_T_GRE_PROTO_TYPE,
BNXT_ULP_GLB_HF_ID_O_ICMP_TYPE,
BNXT_ULP_GLB_HF_ID_I_ICMP_TYPE,
BNXT_ULP_GLB_HF_ID_O_ICMP_CODE,
BNXT_ULP_GLB_HF_ID_I_ICMP_CODE,
BNXT_ULP_GLB_HF_ID_O_ICMP_CSUM,
BNXT_ULP_GLB_HF_ID_I_ICMP_CSUM,
BNXT_ULP_GLB_HF_ID_O_ICMP_IDENT,
BNXT_ULP_GLB_HF_ID_I_ICMP_IDENT,
BNXT_ULP_GLB_HF_ID_O_ICMP_SEQ_NUM,
BNXT_ULP_GLB_HF_ID_I_ICMP_SEQ_NUM,
BNXT_ULP_GLB_HF_ID_O_IPV4_VER,
BNXT_ULP_GLB_HF_ID_I_IPV4_VER,
BNXT_ULP_GLB_HF_ID_O_IPV4_TOS,
@ -55,16 +65,6 @@ enum bnxt_ulp_glb_hf {
BNXT_ULP_GLB_HF_ID_I_IPV6_SRC_ADDR,
BNXT_ULP_GLB_HF_ID_O_IPV6_DST_ADDR,
BNXT_ULP_GLB_HF_ID_I_IPV6_DST_ADDR,
BNXT_ULP_GLB_HF_ID_O_L3_PROTO_ID,
BNXT_ULP_GLB_HF_ID_I_L3_PROTO_ID,
BNXT_ULP_GLB_HF_ID_O_L3_SRC_ADDR,
BNXT_ULP_GLB_HF_ID_I_L3_SRC_ADDR,
BNXT_ULP_GLB_HF_ID_O_L3_DST_ADDR,
BNXT_ULP_GLB_HF_ID_I_L3_DST_ADDR,
BNXT_ULP_GLB_HF_ID_O_L4_SRC_PORT,
BNXT_ULP_GLB_HF_ID_I_L4_SRC_PORT,
BNXT_ULP_GLB_HF_ID_O_L4_DST_PORT,
BNXT_ULP_GLB_HF_ID_I_L4_DST_PORT,
BNXT_ULP_GLB_HF_ID_O_TCP_SRC_PORT,
BNXT_ULP_GLB_HF_ID_I_TCP_SRC_PORT,
BNXT_ULP_GLB_HF_ID_O_TCP_DST_PORT,
@ -115,16 +115,14 @@ enum bnxt_ulp_hf1_0_bitmask {
BNXT_ULP_HF1_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF1_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF1_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
BNXT_ULP_HF1_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF1_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
};
enum bnxt_ulp_hf1_1_bitmask {
@ -142,16 +140,7 @@ enum bnxt_ulp_hf1_1_bitmask {
BNXT_ULP_HF1_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF1_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF1_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_1_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF1_1_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF1_1_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
BNXT_ULP_HF1_1_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
BNXT_ULP_HF1_1_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
BNXT_ULP_HF1_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
BNXT_ULP_HF1_1_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
BNXT_ULP_HF1_1_BITMASK_O_TCP_CSUM = 0x0000020000000000,
BNXT_ULP_HF1_1_BITMASK_O_TCP_URP = 0x0000010000000000
BNXT_ULP_HF1_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
};
enum bnxt_ulp_hf1_2_bitmask {
@ -160,20 +149,17 @@ enum bnxt_ulp_hf1_2_bitmask {
BNXT_ULP_HF1_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF1_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF1_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_2_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF1_2_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF1_2_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
BNXT_ULP_HF1_2_BITMASK_O_UDP_CSUM = 0x0000200000000000
BNXT_ULP_HF1_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF1_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF1_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
};
enum bnxt_ulp_hf1_3_bitmask {
@ -182,14 +168,19 @@ enum bnxt_ulp_hf1_3_bitmask {
BNXT_ULP_HF1_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF1_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF1_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
BNXT_ULP_HF1_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF1_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF1_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF1_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
};
enum bnxt_ulp_hf1_4_bitmask {
@ -223,18 +214,25 @@ enum bnxt_ulp_hf1_5_bitmask {
BNXT_ULP_HF1_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF1_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF1_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
BNXT_ULP_HF1_5_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
BNXT_ULP_HF1_5_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
BNXT_ULP_HF1_5_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
BNXT_ULP_HF1_5_BITMASK_O_UDP_CSUM = 0x0000800000000000
BNXT_ULP_HF1_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF1_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF1_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF1_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
BNXT_ULP_HF1_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
BNXT_ULP_HF1_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
BNXT_ULP_HF1_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
BNXT_ULP_HF1_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
BNXT_ULP_HF1_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
BNXT_ULP_HF1_5_BITMASK_O_TCP_URP = 0x0000010000000000
};
enum bnxt_ulp_hf1_6_bitmask {
@ -243,19 +241,18 @@ enum bnxt_ulp_hf1_6_bitmask {
BNXT_ULP_HF1_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF1_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF1_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF1_6_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF1_6_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF1_6_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
BNXT_ULP_HF1_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF1_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
BNXT_ULP_HF1_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
BNXT_ULP_HF1_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
BNXT_ULP_HF1_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
BNXT_ULP_HF1_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
};
enum bnxt_ulp_hf1_7_bitmask {
@ -264,28 +261,20 @@ enum bnxt_ulp_hf1_7_bitmask {
BNXT_ULP_HF1_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF1_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF1_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF1_7_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF1_7_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF1_7_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF1_7_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF1_7_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF1_7_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
BNXT_ULP_HF1_7_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
BNXT_ULP_HF1_7_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
BNXT_ULP_HF1_7_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
BNXT_ULP_HF1_7_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
BNXT_ULP_HF1_7_BITMASK_O_TCP_CSUM = 0x0000004000000000,
BNXT_ULP_HF1_7_BITMASK_O_TCP_URP = 0x0000002000000000
BNXT_ULP_HF1_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF1_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF1_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF1_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
BNXT_ULP_HF1_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
};
enum bnxt_ulp_hf1_8_bitmask {
@ -297,20 +286,23 @@ enum bnxt_ulp_hf1_8_bitmask {
BNXT_ULP_HF1_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF1_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF1_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF1_8_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF1_8_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF1_8_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
BNXT_ULP_HF1_8_BITMASK_O_UDP_CSUM = 0x0000040000000000
BNXT_ULP_HF1_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF1_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF1_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF1_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
BNXT_ULP_HF1_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
BNXT_ULP_HF1_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
BNXT_ULP_HF1_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
BNXT_ULP_HF1_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
BNXT_ULP_HF1_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
BNXT_ULP_HF1_8_BITMASK_O_TCP_URP = 0x0000008000000000
};
enum bnxt_ulp_hf1_9_bitmask {
@ -322,14 +314,25 @@ enum bnxt_ulp_hf1_9_bitmask {
BNXT_ULP_HF1_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF1_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF1_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
BNXT_ULP_HF1_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF1_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF1_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF1_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF1_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
BNXT_ULP_HF1_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
BNXT_ULP_HF1_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
BNXT_ULP_HF1_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
BNXT_ULP_HF1_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
BNXT_ULP_HF1_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
BNXT_ULP_HF1_9_BITMASK_O_TCP_URP = 0x0000002000000000
};
enum bnxt_ulp_hf1_10_bitmask {
@ -349,15 +352,10 @@ enum bnxt_ulp_hf1_10_bitmask {
BNXT_ULP_HF1_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF1_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF1_10_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF1_10_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF1_10_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
BNXT_ULP_HF1_10_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
BNXT_ULP_HF1_10_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
BNXT_ULP_HF1_10_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
BNXT_ULP_HF1_10_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
BNXT_ULP_HF1_10_BITMASK_O_TCP_CSUM = 0x0000010000000000,
BNXT_ULP_HF1_10_BITMASK_O_TCP_URP = 0x0000008000000000
BNXT_ULP_HF1_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF1_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF1_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
BNXT_ULP_HF1_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
};
enum bnxt_ulp_hf1_11_bitmask {
@ -369,18 +367,46 @@ enum bnxt_ulp_hf1_11_bitmask {
BNXT_ULP_HF1_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF1_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF1_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF1_11_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
BNXT_ULP_HF1_11_BITMASK_O_UDP_CSUM = 0x0000100000000000
BNXT_ULP_HF1_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF1_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF1_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF1_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF1_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
BNXT_ULP_HF1_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
};
enum bnxt_ulp_hf1_12_bitmask {
BNXT_ULP_HF1_12_BITMASK_WM = 0x8000000000000000,
BNXT_ULP_HF1_12_BITMASK_SVIF_INDEX = 0x4000000000000000,
BNXT_ULP_HF1_12_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF1_12_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF1_12_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF1_12_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF1_12_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF1_12_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF1_12_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
BNXT_ULP_HF1_12_BITMASK_O_UDP_CSUM = 0x0000200000000000,
BNXT_ULP_HF1_12_BITMASK_T_VXLAN_FLAGS = 0x0000100000000000,
BNXT_ULP_HF1_12_BITMASK_T_VXLAN_RSVD0 = 0x0000080000000000,
BNXT_ULP_HF1_12_BITMASK_T_VXLAN_VNI = 0x0000040000000000,
BNXT_ULP_HF1_12_BITMASK_T_VXLAN_RSVD1 = 0x0000020000000000
};
enum bnxt_ulp_hf2_0_bitmask {
@ -389,16 +415,14 @@ enum bnxt_ulp_hf2_0_bitmask {
BNXT_ULP_HF2_0_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF2_0_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF2_0_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
BNXT_ULP_HF2_0_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF2_0_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
};
enum bnxt_ulp_hf2_1_bitmask {
@ -416,16 +440,7 @@ enum bnxt_ulp_hf2_1_bitmask {
BNXT_ULP_HF2_1_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF2_1_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF2_1_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF2_1_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF2_1_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF2_1_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
BNXT_ULP_HF2_1_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
BNXT_ULP_HF2_1_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
BNXT_ULP_HF2_1_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
BNXT_ULP_HF2_1_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
BNXT_ULP_HF2_1_BITMASK_O_TCP_CSUM = 0x0000020000000000,
BNXT_ULP_HF2_1_BITMASK_O_TCP_URP = 0x0000010000000000
BNXT_ULP_HF2_1_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000
};
enum bnxt_ulp_hf2_2_bitmask {
@ -434,20 +449,17 @@ enum bnxt_ulp_hf2_2_bitmask {
BNXT_ULP_HF2_2_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF2_2_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF2_2_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF2_2_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF2_2_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF2_2_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
BNXT_ULP_HF2_2_BITMASK_O_UDP_CSUM = 0x0000200000000000
BNXT_ULP_HF2_2_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF2_2_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF2_2_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF2_2_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
};
enum bnxt_ulp_hf2_3_bitmask {
@ -456,14 +468,19 @@ enum bnxt_ulp_hf2_3_bitmask {
BNXT_ULP_HF2_3_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF2_3_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF2_3_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000
BNXT_ULP_HF2_3_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF2_3_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF2_3_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF2_3_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
};
enum bnxt_ulp_hf2_4_bitmask {
@ -497,18 +514,25 @@ enum bnxt_ulp_hf2_5_bitmask {
BNXT_ULP_HF2_5_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF2_5_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF2_5_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
BNXT_ULP_HF2_5_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
BNXT_ULP_HF2_5_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
BNXT_ULP_HF2_5_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
BNXT_ULP_HF2_5_BITMASK_O_UDP_CSUM = 0x0000800000000000
BNXT_ULP_HF2_5_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF2_5_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF2_5_BITMASK_O_TCP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF2_5_BITMASK_O_TCP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF2_5_BITMASK_O_TCP_SENT_SEQ = 0x0000400000000000,
BNXT_ULP_HF2_5_BITMASK_O_TCP_RECV_ACK = 0x0000200000000000,
BNXT_ULP_HF2_5_BITMASK_O_TCP_DATA_OFF = 0x0000100000000000,
BNXT_ULP_HF2_5_BITMASK_O_TCP_TCP_FLAGS = 0x0000080000000000,
BNXT_ULP_HF2_5_BITMASK_O_TCP_RX_WIN = 0x0000040000000000,
BNXT_ULP_HF2_5_BITMASK_O_TCP_CSUM = 0x0000020000000000,
BNXT_ULP_HF2_5_BITMASK_O_TCP_URP = 0x0000010000000000
};
enum bnxt_ulp_hf2_6_bitmask {
@ -517,19 +541,18 @@ enum bnxt_ulp_hf2_6_bitmask {
BNXT_ULP_HF2_6_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF2_6_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF2_6_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF2_6_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF2_6_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF2_6_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000
BNXT_ULP_HF2_6_BITMASK_O_IPV6_VER = 0x0400000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV6_TC = 0x0200000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV6_FLOW_LABEL = 0x0100000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0080000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV6_PROTO_ID = 0x0040000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV6_TTL = 0x0020000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV6_SRC_ADDR = 0x0010000000000000,
BNXT_ULP_HF2_6_BITMASK_O_IPV6_DST_ADDR = 0x0008000000000000,
BNXT_ULP_HF2_6_BITMASK_O_UDP_SRC_PORT = 0x0004000000000000,
BNXT_ULP_HF2_6_BITMASK_O_UDP_DST_PORT = 0x0002000000000000,
BNXT_ULP_HF2_6_BITMASK_O_UDP_LENGTH = 0x0001000000000000,
BNXT_ULP_HF2_6_BITMASK_O_UDP_CSUM = 0x0000800000000000
};
enum bnxt_ulp_hf2_7_bitmask {
@ -538,28 +561,20 @@ enum bnxt_ulp_hf2_7_bitmask {
BNXT_ULP_HF2_7_BITMASK_O_ETH_DMAC = 0x2000000000000000,
BNXT_ULP_HF2_7_BITMASK_O_ETH_SMAC = 0x1000000000000000,
BNXT_ULP_HF2_7_BITMASK_O_ETH_TYPE = 0x0800000000000000,
BNXT_ULP_HF2_7_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF2_7_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF2_7_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF2_7_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF2_7_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF2_7_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
BNXT_ULP_HF2_7_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
BNXT_ULP_HF2_7_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
BNXT_ULP_HF2_7_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
BNXT_ULP_HF2_7_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
BNXT_ULP_HF2_7_BITMASK_O_TCP_CSUM = 0x0000004000000000,
BNXT_ULP_HF2_7_BITMASK_O_TCP_URP = 0x0000002000000000
BNXT_ULP_HF2_7_BITMASK_O_IPV4_VER = 0x0400000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_TOS = 0x0200000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_LEN = 0x0100000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_ID = 0x0080000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_FRAG_OFF = 0x0040000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_TTL = 0x0020000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_PROTO_ID = 0x0010000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_CSUM = 0x0008000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_SRC_ADDR = 0x0004000000000000,
BNXT_ULP_HF2_7_BITMASK_O_IPV4_DST_ADDR = 0x0002000000000000,
BNXT_ULP_HF2_7_BITMASK_O_UDP_SRC_PORT = 0x0001000000000000,
BNXT_ULP_HF2_7_BITMASK_O_UDP_DST_PORT = 0x0000800000000000,
BNXT_ULP_HF2_7_BITMASK_O_UDP_LENGTH = 0x0000400000000000,
BNXT_ULP_HF2_7_BITMASK_O_UDP_CSUM = 0x0000200000000000
};
enum bnxt_ulp_hf2_8_bitmask {
@ -571,20 +586,23 @@ enum bnxt_ulp_hf2_8_bitmask {
BNXT_ULP_HF2_8_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF2_8_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF2_8_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF2_8_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF2_8_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF2_8_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
BNXT_ULP_HF2_8_BITMASK_O_UDP_CSUM = 0x0000040000000000
BNXT_ULP_HF2_8_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF2_8_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF2_8_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF2_8_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF2_8_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
BNXT_ULP_HF2_8_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
BNXT_ULP_HF2_8_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
BNXT_ULP_HF2_8_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
BNXT_ULP_HF2_8_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
BNXT_ULP_HF2_8_BITMASK_O_TCP_CSUM = 0x0000010000000000,
BNXT_ULP_HF2_8_BITMASK_O_TCP_URP = 0x0000008000000000
};
enum bnxt_ulp_hf2_9_bitmask {
@ -596,14 +614,25 @@ enum bnxt_ulp_hf2_9_bitmask {
BNXT_ULP_HF2_9_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF2_9_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF2_9_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000
BNXT_ULP_HF2_9_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF2_9_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF2_9_BITMASK_O_TCP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF2_9_BITMASK_O_TCP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF2_9_BITMASK_O_TCP_SENT_SEQ = 0x0000080000000000,
BNXT_ULP_HF2_9_BITMASK_O_TCP_RECV_ACK = 0x0000040000000000,
BNXT_ULP_HF2_9_BITMASK_O_TCP_DATA_OFF = 0x0000020000000000,
BNXT_ULP_HF2_9_BITMASK_O_TCP_TCP_FLAGS = 0x0000010000000000,
BNXT_ULP_HF2_9_BITMASK_O_TCP_RX_WIN = 0x0000008000000000,
BNXT_ULP_HF2_9_BITMASK_O_TCP_CSUM = 0x0000004000000000,
BNXT_ULP_HF2_9_BITMASK_O_TCP_URP = 0x0000002000000000
};
enum bnxt_ulp_hf2_10_bitmask {
@ -623,15 +652,10 @@ enum bnxt_ulp_hf2_10_bitmask {
BNXT_ULP_HF2_10_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF2_10_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF2_10_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF2_10_BITMASK_O_TCP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF2_10_BITMASK_O_TCP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF2_10_BITMASK_O_TCP_SENT_SEQ = 0x0000200000000000,
BNXT_ULP_HF2_10_BITMASK_O_TCP_RECV_ACK = 0x0000100000000000,
BNXT_ULP_HF2_10_BITMASK_O_TCP_DATA_OFF = 0x0000080000000000,
BNXT_ULP_HF2_10_BITMASK_O_TCP_TCP_FLAGS = 0x0000040000000000,
BNXT_ULP_HF2_10_BITMASK_O_TCP_RX_WIN = 0x0000020000000000,
BNXT_ULP_HF2_10_BITMASK_O_TCP_CSUM = 0x0000010000000000,
BNXT_ULP_HF2_10_BITMASK_O_TCP_URP = 0x0000008000000000
BNXT_ULP_HF2_10_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF2_10_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF2_10_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
BNXT_ULP_HF2_10_BITMASK_O_UDP_CSUM = 0x0000100000000000
};
enum bnxt_ulp_hf2_11_bitmask {
@ -643,17 +667,20 @@ enum bnxt_ulp_hf2_11_bitmask {
BNXT_ULP_HF2_11_BITMASK_OO_VLAN_CFI_PRI = 0x0400000000000000,
BNXT_ULP_HF2_11_BITMASK_OO_VLAN_VID = 0x0200000000000000,
BNXT_ULP_HF2_11_BITMASK_OO_VLAN_TYPE = 0x0100000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV6_VER = 0x0080000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV6_TC = 0x0040000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV6_FLOW_LABEL = 0x0020000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV6_PAYLOAD_LEN = 0x0010000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV6_PROTO_ID = 0x0008000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV6_TTL = 0x0004000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV6_SRC_ADDR = 0x0002000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV6_DST_ADDR = 0x0001000000000000,
BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT = 0x0000800000000000,
BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT = 0x0000400000000000,
BNXT_ULP_HF2_11_BITMASK_O_UDP_LENGTH = 0x0000200000000000,
BNXT_ULP_HF2_11_BITMASK_O_UDP_CSUM = 0x0000100000000000
BNXT_ULP_HF2_11_BITMASK_O_IPV4_VER = 0x0080000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV4_TOS = 0x0040000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV4_LEN = 0x0020000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV4_FRAG_ID = 0x0010000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV4_FRAG_OFF = 0x0008000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV4_TTL = 0x0004000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV4_PROTO_ID = 0x0002000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV4_CSUM = 0x0001000000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV4_SRC_ADDR = 0x0000800000000000,
BNXT_ULP_HF2_11_BITMASK_O_IPV4_DST_ADDR = 0x0000400000000000,
BNXT_ULP_HF2_11_BITMASK_O_UDP_SRC_PORT = 0x0000200000000000,
BNXT_ULP_HF2_11_BITMASK_O_UDP_DST_PORT = 0x0000100000000000,
BNXT_ULP_HF2_11_BITMASK_O_UDP_LENGTH = 0x0000080000000000,
BNXT_ULP_HF2_11_BITMASK_O_UDP_CSUM = 0x0000040000000000
};
#endif

709
drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_act.c
View File

@ -1,709 +0,0 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2021 Broadcom
* All rights reserved.
*/
/* date: Tue Dec 1 17:07:12 2020 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
#include "ulp_template_db_tbl.h"
/* Mapper templates for header act list */
struct bnxt_ulp_mapper_tmpl_info ulp_stingray_act_tmpl_list[] = {
/* act_tid: 1, stingray, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_STINGRAY,
.num_tbls = 4,
.start_tbl_idx = 0,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 0,
.cond_nums = 0 }
}
};
struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[] = {
{ /* act_tid: 1, stingray, table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_start_idx = 0,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1,
.encap_num_fields = 0
},
{ /* act_tid: 1, stingray, table: int_vtag_encap_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_ENCAP_16B,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
.execute_info = {
.cond_true_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_start_idx = 1,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
.encap_num_fields = 12
},
{ /* act_tid: 1, stingray, table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
.execute_info = {
.cond_true_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 2,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.result_start_idx = 13,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
},
{ /* act_tid: 1, stingray, table: ext_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_EXT,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_EXT,
.execute_info = {
.cond_true_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 2,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.result_start_idx = 39,
.result_bit_size = 128,
.result_num_fields = 26,
.encap_num_fields = 0
}
};
struct bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[] = {
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
},
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_PUSH_VLAN
}
};
struct bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[] = {
/* act_tid: 1, stingray, table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 1, stingray, table: int_vtag_encap_record.0 */
{
.description = "ecv_tun_type",
.field_bit_size = 3,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "ecv_l4_type",
.field_bit_size = 3,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "ecv_l3_type",
.field_bit_size = 3,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "ecv_l2_en",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "ecv_vtag_type",
.field_bit_size = 4,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
ULP_SR_SYM_ECV_VTAG_TYPE_ADD_1_ENCAP_PRI}
},
{
.description = "ecv_custom_en",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "ecv_valid",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
},
{
.description = "vtag_tpid",
.field_bit_size = 16,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_PUSH_VLAN & 0xff}
},
{
.description = "vtag_vid",
.field_bit_size = 12,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_VID & 0xff}
},
{
.description = "vtag_de",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vtag_pcp",
.field_bit_size = 3,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_VLAN_PCP & 0xff}
},
{
.description = "spare",
.field_bit_size = 80,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 1, stingray, table: int_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
},
{
.description = "age_enable",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "agg_cntr_en",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "rate_cntr_en",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "flow_cntr_en",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
},
{
.description = "tcpflags_key",
.field_bit_size = 8,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tcpflags_mir",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tcpflags_match",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "encap_ptr",
.field_bit_size = 11,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
(BNXT_ULP_RF_IDX_ENCAP_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_ENCAP_PTR_0 & 0xff}
},
{
.description = "dst_ip_ptr",
.field_bit_size = 10,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
},
{
.description = "tcp_dst_port",
.field_bit_size = 16,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
.field_cond_opr = {
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST
},
{
.description = "src_ip_ptr",
.field_bit_size = 10,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
},
{
.description = "tcp_src_port",
.field_bit_size = 16,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
.field_cond_opr = {
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST
},
{
.description = "meter_id",
.field_bit_size = 10,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_rdir",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tl3_rdir",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_ttl_dec",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
},
{
.description = "tl3_ttl_dec",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
},
{
.description = "decap_func",
.field_bit_size = 4,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
.field_cond_opr = {
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
ULP_SR_SYM_DECAP_FUNC_THRU_TUN},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
ULP_SR_SYM_DECAP_FUNC_NONE}
},
{
.description = "vnic_or_vport",
.field_bit_size = 12,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
},
{
.description = "pop_vlan",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
},
{
.description = "meter",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mirror",
.field_bit_size = 2,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "drop",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
},
{
.description = "hit",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "type",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 1, stingray, table: ext_full_act_record.0 */
{
.description = "flow_cntr_ptr",
.field_bit_size = 14,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
},
{
.description = "age_enable",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "agg_cntr_en",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "rate_cntr_en",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "flow_cntr_en",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_COUNT >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_COUNT & 0xff}
},
{
.description = "flow_cntr_ext",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tcpflags_key",
.field_bit_size = 8,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tcpflags_mir",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tcpflags_match",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "encap_ptr",
.field_bit_size = 11,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "encap_rec_int",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "dst_ip_ptr",
.field_bit_size = 10,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
(BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0 & 0xff}
},
{
.description = "tcp_dst_port",
.field_bit_size = 16,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
.field_cond_opr = {
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_DST & 0xff},
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_SET_TP_DST >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_TP_DST & 0xff},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST
},
{
.description = "src_ip_ptr",
.field_bit_size = 10,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
(BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0 & 0xff}
},
{
.description = "tcp_src_port",
.field_bit_size = 16,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
.field_cond_opr = {
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_SET_TP_SRC & 0xff},
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_SET_TP_SRC & 0xff},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST
},
{
.description = "meter_id",
.field_bit_size = 10,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_rdir",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "tl3_rdir",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "l3_ttl_dec",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
(BNXT_ULP_CF_IDX_ACT_DEC_TTL >> 8) & 0xff,
BNXT_ULP_CF_IDX_ACT_DEC_TTL & 0xff}
},
{
.description = "tl3_ttl_dec",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_CF,
.field_opr1 = {
(BNXT_ULP_CF_IDX_ACT_T_DEC_TTL >> 8) & 0xff,
BNXT_ULP_CF_IDX_ACT_T_DEC_TTL & 0xff}
},
{
.description = "decap_func",
.field_bit_size = 4,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_ACT_BIT,
.field_cond_opr = {
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_VXLAN_DECAP & 0xff},
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
ULP_SR_SYM_DECAP_FUNC_THRU_TUN},
.field_src2 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr2 = {
ULP_SR_SYM_DECAP_FUNC_NONE}
},
{
.description = "vnic_or_vport",
.field_bit_size = 12,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
},
{
.description = "pop_vlan",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_POP_VLAN & 0xff}
},
{
.description = "meter",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mirror",
.field_bit_size = 2,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "drop",
.field_bit_size = 1,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_BIT,
.field_opr1 = {
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 56) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 48) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 40) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 32) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 24) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 16) & 0xff,
((uint64_t)BNXT_ULP_ACT_BIT_DROP >> 8) & 0xff,
(uint64_t)BNXT_ULP_ACT_BIT_DROP & 0xff}
}
};

752
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.c
View File

@ -3,7 +3,7 @@
* All rights reserved.
*/
/* date: Fri Jan 29 11:27:48 2021 */
/* date: Thu Mar 4 10:12:06 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
@ -91,34 +91,26 @@ struct bnxt_ulp_generic_tbl_params ulp_generic_tbl_params[] = {
.num_buckets = 8,
.hash_tbl_entries = 1024,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
/* device tables */
const struct bnxt_ulp_template_device_tbls ulp_template_stingray_tbls[] = {
[BNXT_ULP_TEMPLATE_TYPE_CLASS] = {
.tmpl_list = ulp_stingray_class_tmpl_list,
.tmpl_list_size = ULP_STINGRAY_CLASS_TMPL_LIST_SIZE,
.tbl_list = ulp_stingray_class_tbl_list,
.tbl_list_size = ULP_STINGRAY_CLASS_TBL_LIST_SIZE,
.key_info_list = ulp_stingray_class_key_info_list,
.key_info_list_size = ULP_STINGRAY_CLASS_KEY_INFO_LIST_SIZE,
.ident_list = ulp_stingray_class_ident_list,
.ident_list_size = ULP_STINGRAY_CLASS_IDENT_LIST_SIZE,
.cond_list = ulp_stingray_class_cond_list,
.cond_list_size = ULP_STINGRAY_CLASS_COND_LIST_SIZE,
.result_field_list = ulp_stingray_class_result_field_list,
.result_field_list_size = ULP_STINGRAY_CLASS_RESULT_FIELD_LIST_SIZE
},
[BNXT_ULP_TEMPLATE_TYPE_ACTION] = {
.tmpl_list = ulp_stingray_act_tmpl_list,
.tmpl_list_size = ULP_STINGRAY_ACT_TMPL_LIST_SIZE,
.tbl_list = ulp_stingray_act_tbl_list,
.tbl_list_size = ULP_STINGRAY_ACT_TBL_LIST_SIZE,
.cond_list = ulp_stingray_act_cond_list,
.cond_list_size = ULP_STINGRAY_ACT_COND_LIST_SIZE,
.result_field_list = ulp_stingray_act_result_field_list,
.result_field_list_size = ULP_STINGRAY_ACT_RESULT_FIELD_LIST_SIZE
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 |
BNXT_ULP_DIRECTION_INGRESS] = {
.name = "INGRESS GENERIC_TABLE_PORT_TABLE",
.result_num_entries = 1024,
.result_num_bytes = 18,
.key_num_bytes = 0,
.num_buckets = 0,
.hash_tbl_entries = 0,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
},
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_PORT_TABLE << 1 |
BNXT_ULP_DIRECTION_EGRESS] = {
.name = "EGRESS GENERIC_TABLE_PORT_TABLE",
.result_num_entries = 1024,
.result_num_bytes = 18,
.key_num_bytes = 0,
.num_buckets = 0,
.hash_tbl_entries = 0,
.result_byte_order = BNXT_ULP_BYTE_ORDER_LE
}
};
@ -154,6 +146,32 @@ const struct bnxt_ulp_template_device_tbls ulp_template_wh_plus_tbls[] = {
}
};
/* device tables */
const struct bnxt_ulp_template_device_tbls ulp_template_thor_tbls[] = {
[BNXT_ULP_TEMPLATE_TYPE_CLASS] = {
.tmpl_list = ulp_thor_class_tmpl_list,
.tmpl_list_size = ULP_THOR_CLASS_TMPL_LIST_SIZE,
.tbl_list = ulp_thor_class_tbl_list,
.tbl_list_size = ULP_THOR_CLASS_TBL_LIST_SIZE,
.key_info_list = ulp_thor_class_key_info_list,
.key_info_list_size = ULP_THOR_CLASS_KEY_INFO_LIST_SIZE,
.ident_list = ulp_thor_class_ident_list,
.ident_list_size = ULP_THOR_CLASS_IDENT_LIST_SIZE,
.cond_list = ulp_thor_class_cond_list,
.cond_list_size = ULP_THOR_CLASS_COND_LIST_SIZE,
.result_field_list = ulp_thor_class_result_field_list,
.result_field_list_size = ULP_THOR_CLASS_RESULT_FIELD_LIST_SIZE
},
[BNXT_ULP_TEMPLATE_TYPE_ACTION] = {
.tmpl_list = ulp_thor_act_tmpl_list,
.tmpl_list_size = ULP_THOR_ACT_TMPL_LIST_SIZE,
.tbl_list = ulp_thor_act_tbl_list,
.tbl_list_size = ULP_THOR_ACT_TBL_LIST_SIZE,
.result_field_list = ulp_thor_act_result_field_list,
.result_field_list_size = ULP_THOR_ACT_RESULT_FIELD_LIST_SIZE
}
};
/* List of device specific parameters */
struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
[BNXT_ULP_DEVICE_ID_WH_PLUS] = {
@ -173,17 +191,18 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.packet_count_mask = 0xffffffff00000000,
.byte_count_shift = 0,
.packet_count_shift = 36,
.dynamic_pad_en = 0,
.dev_tbls = ulp_template_wh_plus_tbls
},
[BNXT_ULP_DEVICE_ID_STINGRAY] = {
.description = "Stingray",
[BNXT_ULP_DEVICE_ID_THOR] = {
.description = "Thor",
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.encap_byte_swap = 1,
.int_flow_db_num_entries = 16384,
.ext_flow_db_num_entries = 32768,
.mark_db_lfid_entries = 65536,
.mark_db_gfid_entries = 65536,
.flow_count_db_entries = 16384,
.mark_db_lfid_entries = 0,
.mark_db_gfid_entries = 0,
.flow_count_db_entries = 0,
.fdb_parent_flow_entries = 2,
.num_resources_per_flow = 8,
.num_phy_ports = 2,
@ -192,7 +211,16 @@ struct bnxt_ulp_device_params ulp_device_params[BNXT_ULP_DEVICE_ID_LAST] = {
.packet_count_mask = 0xffffffff00000000,
.byte_count_shift = 0,
.packet_count_shift = 36,
.dev_tbls = ulp_template_stingray_tbls
.dynamic_pad_en = 1,
.em_blk_size_bits = 100,
.em_blk_align_bits = 128,
.em_key_align_bytes = 80,
.wc_slice_width = 160,
.wc_max_slices = 4,
.wc_mode_list = {0x0000000c, 0x0000000e, 0x0000000f, 0x0000000f},
.wc_mod_list_max_size = 4,
.wc_ctl_size_bits = 32,
.dev_tbls = ulp_template_thor_tbls
}
};
@ -248,11 +276,6 @@ struct bnxt_ulp_glb_resource_info ulp_glb_resource_tbl[] = {
}
};
/* Lists global action records */
uint32_t ulp_glb_template_tbl[] = {
BNXT_ULP_DF_TPL_LOOPBACK_ACTION_REC
};
/* Provides act_bitmask */
struct bnxt_ulp_shared_act_info ulp_shared_act_info[] = {
[BNXT_ULP_RESOURCE_SUB_TYPE_GENERIC_TABLE_SHARED_MIRROR << 1 |
@ -360,85 +383,76 @@ uint8_t ulp_glb_field_tbl[] = {
[2050] = 2,
[2052] = 3,
[2054] = 4,
[2058] = 5,
[2060] = 6,
[2062] = 7,
[2064] = 8,
[2066] = 9,
[2068] = 10,
[2070] = 11,
[2072] = 12,
[2074] = 13,
[2076] = 14,
[2088] = 5,
[2090] = 6,
[2092] = 7,
[2094] = 8,
[2096] = 9,
[2098] = 10,
[2100] = 11,
[2102] = 12,
[2176] = 0,
[2177] = 1,
[2178] = 2,
[2180] = 3,
[2182] = 4,
[2186] = 5,
[2188] = 6,
[2190] = 7,
[2192] = 8,
[2194] = 9,
[2196] = 10,
[2198] = 11,
[2200] = 12,
[2202] = 13,
[2204] = 14,
[2232] = 15,
[2234] = 16,
[2236] = 17,
[2238] = 18,
[2240] = 19,
[2242] = 20,
[2244] = 21,
[2246] = 22,
[2248] = 23,
[2196] = 5,
[2198] = 6,
[2200] = 7,
[2202] = 8,
[2204] = 9,
[2206] = 10,
[2208] = 11,
[2210] = 12,
[2212] = 13,
[2214] = 14,
[2304] = 0,
[2305] = 1,
[2306] = 2,
[2308] = 3,
[2310] = 4,
[2314] = 5,
[2316] = 6,
[2318] = 7,
[2320] = 8,
[2322] = 9,
[2324] = 10,
[2326] = 11,
[2328] = 12,
[2330] = 13,
[2332] = 14,
[2378] = 15,
[2380] = 16,
[2382] = 17,
[2384] = 18,
[2344] = 8,
[2346] = 9,
[2348] = 10,
[2350] = 11,
[2352] = 12,
[2354] = 13,
[2356] = 14,
[2358] = 15,
[2386] = 5,
[2390] = 6,
[2394] = 7,
[2432] = 0,
[2433] = 1,
[2434] = 2,
[2436] = 3,
[2438] = 4,
[2462] = 5,
[2464] = 6,
[2466] = 7,
[2468] = 8,
[2470] = 9,
[2472] = 10,
[2474] = 11,
[2476] = 12,
[2452] = 8,
[2454] = 9,
[2456] = 10,
[2458] = 11,
[2460] = 12,
[2462] = 13,
[2464] = 14,
[2466] = 15,
[2468] = 16,
[2470] = 17,
[2514] = 5,
[2518] = 6,
[2522] = 7,
[2560] = 0,
[2561] = 1,
[2562] = 2,
[2564] = 3,
[2566] = 4,
[2590] = 5,
[2592] = 6,
[2594] = 7,
[2596] = 8,
[2598] = 9,
[2600] = 10,
[2602] = 11,
[2604] = 12,
[2600] = 5,
[2602] = 6,
[2604] = 7,
[2606] = 8,
[2608] = 9,
[2610] = 10,
[2612] = 11,
[2614] = 12,
[2616] = 13,
[2618] = 14,
[2620] = 15,
@ -453,82 +467,83 @@ uint8_t ulp_glb_field_tbl[] = {
[2690] = 2,
[2692] = 3,
[2694] = 4,
[2718] = 5,
[2720] = 6,
[2722] = 7,
[2724] = 8,
[2726] = 9,
[2728] = 10,
[2730] = 11,
[2732] = 12,
[2762] = 13,
[2764] = 14,
[2766] = 15,
[2768] = 16,
[2708] = 5,
[2710] = 6,
[2712] = 7,
[2714] = 8,
[2716] = 9,
[2718] = 10,
[2720] = 11,
[2722] = 12,
[2724] = 13,
[2726] = 14,
[2744] = 15,
[2746] = 16,
[2748] = 17,
[2750] = 18,
[2752] = 19,
[2754] = 20,
[2756] = 21,
[2758] = 22,
[2760] = 23,
[2816] = 0,
[2817] = 1,
[2818] = 2,
[2820] = 3,
[2822] = 4,
[2826] = 8,
[2828] = 9,
[2830] = 10,
[2832] = 11,
[2834] = 12,
[2836] = 13,
[2838] = 14,
[2840] = 15,
[2842] = 16,
[2844] = 17,
[2898] = 5,
[2902] = 6,
[2906] = 7,
[2856] = 5,
[2858] = 6,
[2860] = 7,
[2862] = 8,
[2864] = 9,
[2866] = 10,
[2868] = 11,
[2870] = 12,
[2890] = 13,
[2892] = 14,
[2894] = 15,
[2896] = 16,
[2944] = 0,
[2945] = 1,
[2946] = 2,
[2948] = 3,
[2950] = 4,
[2954] = 8,
[2956] = 9,
[2958] = 10,
[2960] = 11,
[2962] = 12,
[2964] = 13,
[2966] = 14,
[2968] = 15,
[2970] = 16,
[2972] = 17,
[3000] = 18,
[3002] = 19,
[3004] = 20,
[3006] = 21,
[3008] = 22,
[3010] = 23,
[3012] = 24,
[3014] = 25,
[3016] = 26,
[3026] = 5,
[3030] = 6,
[3034] = 7,
[2964] = 5,
[2966] = 6,
[2968] = 7,
[2970] = 8,
[2972] = 9,
[2974] = 10,
[2976] = 11,
[2978] = 12,
[2980] = 13,
[2982] = 14,
[3018] = 15,
[3020] = 16,
[3022] = 17,
[3024] = 18,
[3072] = 0,
[3073] = 1,
[3074] = 2,
[3076] = 3,
[3078] = 4,
[3082] = 8,
[3084] = 9,
[3086] = 10,
[3088] = 11,
[3090] = 12,
[3092] = 13,
[3094] = 14,
[3096] = 15,
[3098] = 16,
[3100] = 17,
[3146] = 18,
[3148] = 19,
[3150] = 20,
[3152] = 21,
[3112] = 8,
[3114] = 9,
[3116] = 10,
[3118] = 11,
[3120] = 12,
[3122] = 13,
[3124] = 14,
[3126] = 15,
[3128] = 16,
[3130] = 17,
[3132] = 18,
[3134] = 19,
[3136] = 20,
[3138] = 21,
[3140] = 22,
[3142] = 23,
[3144] = 24,
[3154] = 5,
[3158] = 6,
[3162] = 7,
@ -537,14 +552,25 @@ uint8_t ulp_glb_field_tbl[] = {
[3202] = 2,
[3204] = 3,
[3206] = 4,
[3230] = 8,
[3232] = 9,
[3234] = 10,
[3236] = 11,
[3238] = 12,
[3240] = 13,
[3242] = 14,
[3244] = 15,
[3220] = 8,
[3222] = 9,
[3224] = 10,
[3226] = 11,
[3228] = 12,
[3230] = 13,
[3232] = 14,
[3234] = 15,
[3236] = 16,
[3238] = 17,
[3256] = 18,
[3258] = 19,
[3260] = 20,
[3262] = 21,
[3264] = 22,
[3266] = 23,
[3268] = 24,
[3270] = 25,
[3272] = 26,
[3282] = 5,
[3286] = 6,
[3290] = 7,
@ -553,23 +579,18 @@ uint8_t ulp_glb_field_tbl[] = {
[3330] = 2,
[3332] = 3,
[3334] = 4,
[3358] = 8,
[3360] = 9,
[3362] = 10,
[3364] = 11,
[3366] = 12,
[3368] = 13,
[3370] = 14,
[3372] = 15,
[3384] = 16,
[3386] = 17,
[3388] = 18,
[3390] = 19,
[3392] = 20,
[3394] = 21,
[3396] = 22,
[3398] = 23,
[3400] = 24,
[3368] = 8,
[3370] = 9,
[3372] = 10,
[3374] = 11,
[3376] = 12,
[3378] = 13,
[3380] = 14,
[3382] = 15,
[3402] = 16,
[3404] = 17,
[3406] = 18,
[3408] = 19,
[3410] = 5,
[3414] = 6,
[3418] = 7,
@ -578,105 +599,121 @@ uint8_t ulp_glb_field_tbl[] = {
[3458] = 2,
[3460] = 3,
[3462] = 4,
[3486] = 8,
[3488] = 9,
[3490] = 10,
[3492] = 11,
[3494] = 12,
[3496] = 13,
[3498] = 14,
[3500] = 15,
[3530] = 16,
[3532] = 17,
[3534] = 18,
[3536] = 19,
[3476] = 8,
[3478] = 9,
[3480] = 10,
[3482] = 11,
[3484] = 12,
[3486] = 13,
[3488] = 14,
[3490] = 15,
[3492] = 16,
[3494] = 17,
[3530] = 18,
[3532] = 19,
[3534] = 20,
[3536] = 21,
[3538] = 5,
[3542] = 6,
[3546] = 7,
[3584] = 0,
[3585] = 1,
[3586] = 2,
[3588] = 3,
[3590] = 4,
[3604] = 5,
[3606] = 6,
[3608] = 7,
[3610] = 8,
[3612] = 9,
[3614] = 10,
[3616] = 11,
[3618] = 12,
[3620] = 13,
[3622] = 14,
[3658] = 15,
[3660] = 16,
[3662] = 17,
[3664] = 18,
[3678] = 19,
[3679] = 20,
[3680] = 21,
[3681] = 22,
[4096] = 0,
[4097] = 1,
[4098] = 2,
[4100] = 3,
[4102] = 4,
[4106] = 5,
[4108] = 6,
[4110] = 7,
[4112] = 8,
[4114] = 9,
[4116] = 10,
[4118] = 11,
[4120] = 12,
[4122] = 13,
[4124] = 14,
[4136] = 5,
[4138] = 6,
[4140] = 7,
[4142] = 8,
[4144] = 9,
[4146] = 10,
[4148] = 11,
[4150] = 12,
[4224] = 0,
[4225] = 1,
[4226] = 2,
[4228] = 3,
[4230] = 4,
[4234] = 5,
[4236] = 6,
[4238] = 7,
[4240] = 8,
[4242] = 9,
[4244] = 10,
[4246] = 11,
[4248] = 12,
[4250] = 13,
[4252] = 14,
[4280] = 15,
[4282] = 16,
[4284] = 17,
[4286] = 18,
[4288] = 19,
[4290] = 20,
[4292] = 21,
[4294] = 22,
[4296] = 23,
[4244] = 5,
[4246] = 6,
[4248] = 7,
[4250] = 8,
[4252] = 9,
[4254] = 10,
[4256] = 11,
[4258] = 12,
[4260] = 13,
[4262] = 14,
[4352] = 0,
[4353] = 1,
[4354] = 2,
[4356] = 3,
[4358] = 4,
[4362] = 5,
[4364] = 6,
[4366] = 7,
[4368] = 8,
[4370] = 9,
[4372] = 10,
[4374] = 11,
[4376] = 12,
[4378] = 13,
[4380] = 14,
[4426] = 15,
[4428] = 16,
[4430] = 17,
[4432] = 18,
[4392] = 8,
[4394] = 9,
[4396] = 10,
[4398] = 11,
[4400] = 12,
[4402] = 13,
[4404] = 14,
[4406] = 15,
[4434] = 5,
[4438] = 6,
[4442] = 7,
[4480] = 0,
[4481] = 1,
[4482] = 2,
[4484] = 3,
[4486] = 4,
[4510] = 5,
[4512] = 6,
[4514] = 7,
[4516] = 8,
[4518] = 9,
[4520] = 10,
[4522] = 11,
[4524] = 12,
[4500] = 8,
[4502] = 9,
[4504] = 10,
[4506] = 11,
[4508] = 12,
[4510] = 13,
[4512] = 14,
[4514] = 15,
[4516] = 16,
[4518] = 17,
[4562] = 5,
[4566] = 6,
[4570] = 7,
[4608] = 0,
[4609] = 1,
[4610] = 2,
[4612] = 3,
[4614] = 4,
[4638] = 5,
[4640] = 6,
[4642] = 7,
[4644] = 8,
[4646] = 9,
[4648] = 10,
[4650] = 11,
[4652] = 12,
[4648] = 5,
[4650] = 6,
[4652] = 7,
[4654] = 8,
[4656] = 9,
[4658] = 10,
[4660] = 11,
[4662] = 12,
[4664] = 13,
[4666] = 14,
[4668] = 15,
@ -691,82 +728,83 @@ uint8_t ulp_glb_field_tbl[] = {
[4738] = 2,
[4740] = 3,
[4742] = 4,
[4766] = 5,
[4768] = 6,
[4770] = 7,
[4772] = 8,
[4774] = 9,
[4776] = 10,
[4778] = 11,
[4780] = 12,
[4810] = 13,
[4812] = 14,
[4814] = 15,
[4816] = 16,
[4756] = 5,
[4758] = 6,
[4760] = 7,
[4762] = 8,
[4764] = 9,
[4766] = 10,
[4768] = 11,
[4770] = 12,
[4772] = 13,
[4774] = 14,
[4792] = 15,
[4794] = 16,
[4796] = 17,
[4798] = 18,
[4800] = 19,
[4802] = 20,
[4804] = 21,
[4806] = 22,
[4808] = 23,
[4864] = 0,
[4865] = 1,
[4866] = 2,
[4868] = 3,
[4870] = 4,
[4874] = 8,
[4876] = 9,
[4878] = 10,
[4880] = 11,
[4882] = 12,
[4884] = 13,
[4886] = 14,
[4888] = 15,
[4890] = 16,
[4892] = 17,
[4946] = 5,
[4950] = 6,
[4954] = 7,
[4904] = 5,
[4906] = 6,
[4908] = 7,
[4910] = 8,
[4912] = 9,
[4914] = 10,
[4916] = 11,
[4918] = 12,
[4938] = 13,
[4940] = 14,
[4942] = 15,
[4944] = 16,
[4992] = 0,
[4993] = 1,
[4994] = 2,
[4996] = 3,
[4998] = 4,
[5002] = 8,
[5004] = 9,
[5006] = 10,
[5008] = 11,
[5010] = 12,
[5012] = 13,
[5014] = 14,
[5016] = 15,
[5018] = 16,
[5020] = 17,
[5048] = 18,
[5050] = 19,
[5052] = 20,
[5054] = 21,
[5056] = 22,
[5058] = 23,
[5060] = 24,
[5062] = 25,
[5064] = 26,
[5074] = 5,
[5078] = 6,
[5082] = 7,
[5012] = 5,
[5014] = 6,
[5016] = 7,
[5018] = 8,
[5020] = 9,
[5022] = 10,
[5024] = 11,
[5026] = 12,
[5028] = 13,
[5030] = 14,
[5066] = 15,
[5068] = 16,
[5070] = 17,
[5072] = 18,
[5120] = 0,
[5121] = 1,
[5122] = 2,
[5124] = 3,
[5126] = 4,
[5130] = 8,
[5132] = 9,
[5134] = 10,
[5136] = 11,
[5138] = 12,
[5140] = 13,
[5142] = 14,
[5144] = 15,
[5146] = 16,
[5148] = 17,
[5194] = 18,
[5196] = 19,
[5198] = 20,
[5200] = 21,
[5160] = 8,
[5162] = 9,
[5164] = 10,
[5166] = 11,
[5168] = 12,
[5170] = 13,
[5172] = 14,
[5174] = 15,
[5176] = 16,
[5178] = 17,
[5180] = 18,
[5182] = 19,
[5184] = 20,
[5186] = 21,
[5188] = 22,
[5190] = 23,
[5192] = 24,
[5202] = 5,
[5206] = 6,
[5210] = 7,
@ -775,14 +813,25 @@ uint8_t ulp_glb_field_tbl[] = {
[5250] = 2,
[5252] = 3,
[5254] = 4,
[5278] = 8,
[5280] = 9,
[5282] = 10,
[5284] = 11,
[5286] = 12,
[5288] = 13,
[5290] = 14,
[5292] = 15,
[5268] = 8,
[5270] = 9,
[5272] = 10,
[5274] = 11,
[5276] = 12,
[5278] = 13,
[5280] = 14,
[5282] = 15,
[5284] = 16,
[5286] = 17,
[5304] = 18,
[5306] = 19,
[5308] = 20,
[5310] = 21,
[5312] = 22,
[5314] = 23,
[5316] = 24,
[5318] = 25,
[5320] = 26,
[5330] = 5,
[5334] = 6,
[5338] = 7,
@ -791,23 +840,18 @@ uint8_t ulp_glb_field_tbl[] = {
[5378] = 2,
[5380] = 3,
[5382] = 4,
[5406] = 8,
[5408] = 9,
[5410] = 10,
[5412] = 11,
[5414] = 12,
[5416] = 13,
[5418] = 14,
[5420] = 15,
[5432] = 16,
[5434] = 17,
[5436] = 18,
[5438] = 19,
[5440] = 20,
[5442] = 21,
[5444] = 22,
[5446] = 23,
[5448] = 24,
[5416] = 8,
[5418] = 9,
[5420] = 10,
[5422] = 11,
[5424] = 12,
[5426] = 13,
[5428] = 14,
[5430] = 15,
[5450] = 16,
[5452] = 17,
[5454] = 18,
[5456] = 19,
[5458] = 5,
[5462] = 6,
[5466] = 7,
@ -816,18 +860,20 @@ uint8_t ulp_glb_field_tbl[] = {
[5506] = 2,
[5508] = 3,
[5510] = 4,
[5534] = 8,
[5536] = 9,
[5538] = 10,
[5540] = 11,
[5542] = 12,
[5544] = 13,
[5546] = 14,
[5548] = 15,
[5578] = 16,
[5580] = 17,
[5582] = 18,
[5584] = 19,
[5524] = 8,
[5526] = 9,
[5528] = 10,
[5530] = 11,
[5532] = 12,
[5534] = 13,
[5536] = 14,
[5538] = 15,
[5540] = 16,
[5542] = 17,
[5578] = 18,
[5580] = 19,
[5582] = 20,
[5584] = 21,
[5586] = 5,
[5590] = 6,
[5594] = 7

42
drivers/net/bnxt/tf_ulp/ulp_template_db_tbl.h
View File

@ -57,6 +57,10 @@ extern struct bnxt_ulp_mapper_tmpl_info ulp_stingray_act_tmpl_list[];
extern struct bnxt_ulp_mapper_tbl_info ulp_stingray_act_tbl_list[];
extern struct bnxt_ulp_mapper_key_info ulp_stingray_act_key_info_list[];
extern struct bnxt_ulp_mapper_ident_info ulp_stingray_act_ident_list[];
extern struct
bnxt_ulp_mapper_field_info ulp_stingray_act_result_field_list[];
@ -66,5 +70,43 @@ bnxt_ulp_mapper_cond_info ulp_stingray_class_cond_list[];
extern struct
bnxt_ulp_mapper_cond_info ulp_stingray_act_cond_list[];
/* Thor template table declarations */
extern struct bnxt_ulp_mapper_tmpl_info ulp_thor_class_tmpl_list[];
extern struct bnxt_ulp_mapper_tbl_info ulp_thor_class_tbl_list[];
extern struct
bnxt_ulp_mapper_key_info ulp_thor_class_key_info_list[];
extern struct
bnxt_ulp_mapper_field_info ulp_thor_class_result_field_list[];
extern struct bnxt_ulp_mapper_ident_info ulp_thor_class_ident_list[];
extern struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[];
extern struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[];
extern struct bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[];
extern struct bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[];
extern struct
bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[];
extern struct
bnxt_ulp_mapper_cond_info ulp_thor_class_cond_list[];
extern struct
bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[];
extern struct bnxt_ulp_mapper_key_info ulp_wh_plus_act_key_info_list[];
extern struct bnxt_ulp_mapper_ident_info ulp_wh_plus_act_ident_list[];
/* Global declarations */
extern uint8_t ulp_glb_field_tbl[];
extern struct
bnxt_ulp_shared_act_info ulp_shared_act_info[];
#endif

229
drivers/net/bnxt/tf_ulp/ulp_template_db_thor_act.c Normal file
View File

@ -0,0 +1,229 @@
/* SPDX-License-Identifier: BSD-3-Clause
* Copyright(c) 2014-2021 Broadcom
* All rights reserved.
*/
/* date: Mon Feb 8 09:17:37 2021 */
#include "ulp_template_db_enum.h"
#include "ulp_template_db_field.h"
#include "ulp_template_struct.h"
#include "ulp_template_db_tbl.h"
/* Mapper templates for header act list */
struct bnxt_ulp_mapper_tmpl_info ulp_thor_act_tmpl_list[] = {
/* act_tid: 1, thor, ingress */
[1] = {
.device_name = BNXT_ULP_DEVICE_ID_THOR,
.num_tbls = 2,
.start_tbl_idx = 0,
.reject_info = {
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_FALSE,
.cond_start_idx = 0,
.cond_nums = 0 }
}
};
struct bnxt_ulp_mapper_tbl_info ulp_thor_act_tbl_list[] = {
{ /* act_tid: 1, thor, table: int_flow_counter_tbl.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_ACT_STATS_64,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_INT_COUNT,
.direction = TF_DIR_RX,
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_start_idx = 0,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
},
{ /* act_tid: 1, thor, table: int_full_act_record.0 */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
.resource_type = TF_TBL_TYPE_FULL_ACT_RECORD,
.resource_sub_type =
BNXT_ULP_RESOURCE_SUB_TYPE_INDEX_TABLE_NORMAL,
.direction = TF_DIR_RX,
.mem_type_opcode = BNXT_ULP_MEM_TYPE_OPC_EXECUTE_IF_INT,
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_TRUE,
.cond_start_idx = 1,
.cond_nums = 0 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 1,
.result_bit_size = 128,
.result_num_fields = 17,
.encap_num_fields = 0
}
};
struct bnxt_ulp_mapper_cond_info ulp_thor_act_cond_list[] = {
/* cond_execute: act_tid: 1, int_flow_counter_tbl.0 */
{
.cond_opcode = BNXT_ULP_COND_OPC_ACT_BIT_IS_SET,
.cond_operand = BNXT_ULP_ACT_BIT_COUNT
}
};
struct bnxt_ulp_mapper_field_info ulp_thor_act_result_field_list[] = {
/* act_tid: 1, thor, table: int_flow_counter_tbl.0 */
{
.description = "count",
.field_bit_size = 64,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
/* act_tid: 1, thor, table: int_full_act_record.0 */
{
.description = "sp_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "encap_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mod_rec_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "rsvd1",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "rsvd0",
.field_bit_size = 8,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "decap_func",
.field_bit_size = 5,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "meter",
.field_bit_size = 10,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "stats_op",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "stats_ptr",
.field_bit_size = 16,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_RF,
.field_opr1 = {
(BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 >> 8) & 0xff,
BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0 & 0xff}
},
{
.description = "vnic_or_vport",
.field_bit_size = 11,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ACT_PROP,
.field_opr1 = {
(BNXT_ULP_ACT_PROP_IDX_VNIC >> 8) & 0xff,
BNXT_ULP_ACT_PROP_IDX_VNIC & 0xff}
},
{
.description = "use_default",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "mirror",
.field_bit_size = 4,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "cnd_copy",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "vlan_dlt_rpt",
.field_bit_size = 2,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "drop",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "hit",
.field_bit_size = 1,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_ZERO
},
{
.description = "type",
.field_bit_size = 3,
.field_opc = BNXT_ULP_FIELD_OPC_COND_OP,
.field_cond_src = BNXT_ULP_FIELD_COND_SRC_TRUE,
.field_src1 = BNXT_ULP_FIELD_SRC_CONST,
.field_opr1 = {
1}
}
};
struct
bnxt_ulp_mapper_ident_info ulp_thor_act_ident_list[] = {
};
struct
bnxt_ulp_mapper_key_info ulp_thor_act_key_info_list[] = {
};

9564
drivers/net/bnxt/tf_ulp/ulp_template_db_stingray_class.c → drivers/net/bnxt/tf_ulp/ulp_template_db_thor_class.c
View File

File diff suppressed because it is too large Load Diff

71
drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_act.c
View File

@ -84,13 +84,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 9,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_GENERIC_TBL_OPC_READ,
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 0,
.blob_key_bit_size = 1,
.key_bit_size = 1,
@ -107,7 +108,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 10,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
@ -115,6 +116,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 0,
.result_bit_size = 64,
.result_num_fields = 1
@ -129,7 +131,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 11,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
@ -137,6 +139,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 1,
.result_bit_size = 0,
.result_num_fields = 0,
@ -160,6 +163,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 13,
.result_bit_size = 128,
.result_num_fields = 26,
@ -183,6 +187,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 39,
.result_bit_size = 128,
.result_num_fields = 26,
@ -199,7 +204,8 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.cond_nums = 0 },
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_ALLOC_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE
},
{ /* act_tid: 2, wh_plus, table: mirror_tbl.alloc */
.resource_func = BNXT_ULP_RESOURCE_FUNC_INDEX_TABLE,
@ -219,6 +225,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 77,
.result_bit_size = 32,
.result_num_fields = 6
@ -232,7 +239,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 12,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
@ -241,6 +248,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 83,
.result_bit_size = 64,
.result_num_fields = 1
@ -264,6 +272,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 84,
.result_bit_size = 128,
.result_num_fields = 26,
@ -288,6 +297,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_RID_REGFILE,
.fdb_operand = BNXT_ULP_RF_IDX_RID,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 110,
.result_bit_size = 128,
.result_num_fields = 26,
@ -310,6 +320,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.mark_db_opcode = BNXT_ULP_MARK_DB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 148,
.result_bit_size = 32,
.result_num_fields = 6
@ -330,6 +341,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.gen_tbl_lkup_type = BNXT_ULP_GENERIC_TBL_LKUP_TYPE_INDEX,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.key_start_idx = 1,
.blob_key_bit_size = 1,
.key_bit_size = 1,
@ -347,13 +359,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 13,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 156,
.result_bit_size = 64,
.result_num_fields = 1
@ -367,13 +380,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 14,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 157,
.result_bit_size = 32,
.result_num_fields = 1
@ -387,13 +401,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 15,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 158,
.result_bit_size = 32,
.result_num_fields = 1
@ -414,6 +429,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 159,
.result_bit_size = 0,
.result_num_fields = 0,
@ -436,6 +452,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 171,
.result_bit_size = 128,
.result_num_fields = 26
@ -457,6 +474,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 197,
.result_bit_size = 128,
.result_num_fields = 26,
@ -471,13 +489,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 16,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 235,
.result_bit_size = 64,
.result_num_fields = 1
@ -492,13 +511,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 17,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 236,
.result_bit_size = 0,
.result_num_fields = 0,
@ -521,6 +541,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 248,
.result_bit_size = 128,
.result_num_fields = 26
@ -535,13 +556,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 18,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 274,
.result_bit_size = 128,
.result_num_fields = 26,
@ -557,13 +579,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 0,
.cond_false_goto = 0,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 19,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 312,
.result_bit_size = 128,
.result_num_fields = 26,
@ -578,13 +601,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 20,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 350,
.result_bit_size = 64,
.result_num_fields = 1
@ -598,13 +622,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 21,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_SRC_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 351,
.result_bit_size = 32,
.result_num_fields = 1
@ -618,13 +643,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 22,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MODIFY_IPV4_DST_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 352,
.result_bit_size = 32,
.result_num_fields = 1
@ -645,6 +671,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_GLB_RF_IDX_ENCAP_MAC_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_NOP,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 353,
.result_bit_size = 0,
.result_num_fields = 0,
@ -667,6 +694,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 365,
.result_bit_size = 128,
.result_num_fields = 26
@ -688,6 +716,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 391,
.result_bit_size = 128,
.result_num_fields = 26,
@ -702,13 +731,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 23,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_FLOW_CNTR_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 429,
.result_bit_size = 64,
.result_num_fields = 1
@ -722,13 +752,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 24,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 430,
.result_bit_size = 0,
.result_num_fields = 0,
@ -743,13 +774,14 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.execute_info = {
.cond_true_goto = 1,
.cond_false_goto = 1,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_OR,
.cond_list_opcode = BNXT_ULP_COND_LIST_OPC_AND,
.cond_start_idx = 25,
.cond_nums = 1 },
.tbl_opcode = BNXT_ULP_INDEX_TBL_OPC_ALLOC_WR_REGFILE,
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_SP_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 433,
.result_bit_size = 0,
.result_num_fields = 0,
@ -772,6 +804,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_ENCAP_PTR_0,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 436,
.result_bit_size = 0,
.result_num_fields = 0,
@ -794,6 +827,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 448,
.result_bit_size = 128,
.result_num_fields = 26
@ -815,6 +849,7 @@ struct bnxt_ulp_mapper_tbl_info ulp_wh_plus_act_tbl_list[] = {
.tbl_operand = BNXT_ULP_RF_IDX_MAIN_ACTION_PTR,
.accept_opcode = BNXT_ULP_ACCEPT_OPC_ALWAYS,
.fdb_opcode = BNXT_ULP_FDB_OPC_PUSH_FID,
.byte_order = BNXT_ULP_BYTE_ORDER_LE,
.result_start_idx = 474,
.result_bit_size = 128,
.result_num_fields = 26,

6683
drivers/net/bnxt/tf_ulp/ulp_template_db_wh_plus_class.c
View File

File diff suppressed because it is too large Load Diff

12
drivers/net/bnxt/tf_ulp/ulp_template_struct.h
View File

@ -28,6 +28,7 @@
#define BNXT_ULP_PROTO_HDR_TCP_NUM 9
#define BNXT_ULP_PROTO_HDR_VXLAN_NUM 4
#define BNXT_ULP_PROTO_HDR_GRE_NUM 6
#define BNXT_ULP_PROTO_HDR_ICMP_NUM 5
#define BNXT_ULP_PROTO_HDR_MAX 128
#define BNXT_ULP_PROTO_HDR_FIELD_SVIF_IDX 1
@ -204,6 +205,16 @@ struct bnxt_ulp_device_params {
uint64_t packet_count_mask;
uint32_t byte_count_shift;
uint32_t packet_count_shift;
uint32_t dynamic_pad_en;
uint16_t em_blk_size_bits;
uint16_t em_blk_align_bits;
uint16_t em_key_align_bytes;
uint16_t em_result_size_bits;
uint16_t wc_slice_width;
uint16_t wc_max_slices;
uint32_t wc_mode_list[4];
uint32_t wc_mod_list_max_size;
uint32_t wc_ctl_size_bits;
const struct bnxt_ulp_template_device_tbls *dev_tbls;
};
@ -226,6 +237,7 @@ struct bnxt_ulp_mapper_tbl_info {
uint8_t direction;
enum bnxt_ulp_pri_opc pri_opcode;
uint32_t pri_operand;
enum bnxt_ulp_byte_order byte_order;
/* conflict resolution opcode */
enum bnxt_ulp_accept_opc accept_opcode;

4
drivers/net/bnxt/tf_ulp/ulp_tun.h
View File

@ -16,10 +16,6 @@
#include "ulp_template_db_enum.h"
#include "ulp_template_struct.h"
#if RTE_VERSION_NUM(17, 11, 10, 16) == RTE_VERSION
#define RTE_ETHER_ADDR_LEN ETHER_ADDR_LEN
#endif
#define BNXT_OUTER_TUN_FLOW(l3_tun, params) \
((l3_tun) && \
ULP_BITMAP_ISSET((params)->act_bitmap.bits, \

187
drivers/net/bnxt/tf_ulp/ulp_utils.c
View File

@ -3,6 +3,7 @@
* All rights reserved.
*/
#include <rte_common.h>
#include "ulp_utils.h"
#include "bnxt_tf_common.h"
@ -232,6 +233,7 @@ ulp_bs_push_msb(uint8_t *bs, uint16_t pos, uint8_t len, uint8_t *val)
* big endian. All fields are packed with this order.
*
* returns 0 on error or 1 on success
* Notes - If bitlen is zero then set it to max.
*/
uint32_t
ulp_blob_init(struct ulp_blob *blob,
@ -243,7 +245,10 @@ ulp_blob_init(struct ulp_blob *blob,
BNXT_TF_DBG(ERR, "invalid argument\n");
return 0; /* failure */
}
blob->bitlen = bitlen;
if (bitlen)
blob->bitlen = bitlen;
else
blob->bitlen = BNXT_ULP_FLMP_BLOB_SIZE_IN_BITS;
blob->byte_order = order;
blob->write_idx = 0;
memset(blob->data, 0, sizeof(blob->data));
@ -505,6 +510,31 @@ ulp_blob_pad_push(struct ulp_blob *blob,
return datalen;
}
/*
* Adds pad to an initialized blob at the current offset based on
* the alignment.
*
* blob [in] The blob that needs to be aligned
*
* align [in] Alignment in bits.
*
* returns the number of pad bits added, -1 on failure
*/
int32_t
ulp_blob_pad_align(struct ulp_blob *blob,
uint32_t align)
{
int32_t pad = 0;
pad = RTE_ALIGN(blob->write_idx, align) - blob->write_idx;
if (pad > (int32_t)(blob->bitlen - blob->write_idx)) {
BNXT_TF_DBG(ERR, "Pad too large for blob\n");
return -1;
}
blob->write_idx += pad;
return pad;
}
/* Get data from src and put into dst using little-endian format */
static void
ulp_bs_get_lsb(uint8_t *src, uint16_t bitpos, uint8_t bitlen, uint8_t *dst)
@ -668,6 +698,24 @@ ulp_blob_data_get(struct ulp_blob *blob,
return blob->data;
}
/*
* Get the data length of the binary blob.
*
* blob [in] The blob's data len to be retrieved.
*
* returns length of the binary blob
*/
uint16_t
ulp_blob_data_len_get(struct ulp_blob *blob)
{
/* validate the arguments */
if (!blob) {
BNXT_TF_DBG(ERR, "invalid argument\n");
return 0; /* failure */
}
return blob->write_idx;
}
/*
* Set the encap swap start index of the binary blob.
*
@ -731,14 +779,17 @@ ulp_blob_perform_encap_swap(struct ulp_blob *blob)
* vice-versa.
*
* blob [in] The blob's data to be used for swap.
* chunk_size[in] the swap is done within the chunk in bytes
*
* returns void.
*/
void
ulp_blob_perform_byte_reverse(struct ulp_blob *blob)
ulp_blob_perform_byte_reverse(struct ulp_blob *blob,
uint32_t chunk_size)
{
uint32_t idx = 0, num = 0;
uint32_t idx = 0, jdx = 0, num = 0;
uint8_t xchar;
uint8_t *buff;
/* validate the arguments */
if (!blob) {
@ -746,11 +797,15 @@ ulp_blob_perform_byte_reverse(struct ulp_blob *blob)
return; /* failure */
}
num = ULP_BITS_2_BYTE_NR(blob->write_idx);
for (idx = 0; idx < (num / 2); idx++) {
xchar = blob->data[idx];
blob->data[idx] = blob->data[(num - 1) - idx];
blob->data[(num - 1) - idx] = xchar;
buff = blob->data;
num = ULP_BITS_2_BYTE(blob->write_idx) / chunk_size;
for (idx = 0; idx < num; idx++) {
for (jdx = 0; jdx < chunk_size / 2; jdx++) {
xchar = buff[jdx];
buff[jdx] = buff[(chunk_size - 1) - jdx];
buff[(chunk_size - 1) - jdx] = xchar;
}
buff += chunk_size;
}
}
@ -816,6 +871,122 @@ ulp_blob_perform_64B_byte_swap(struct ulp_blob *blob)
}
}
static int32_t
ulp_blob_msb_block_merge(struct ulp_blob *dst, struct ulp_blob *src,
uint32_t block_size, uint32_t pad)
{
uint32_t i, k, write_bytes, remaining;
uint16_t num;
uint8_t *src_buf = ulp_blob_data_get(src, &num);
uint8_t bluff;
for (i = 0; i < num;) {
if (((dst->write_idx % block_size) + (num - i)) > block_size)
write_bytes = block_size - dst->write_idx;
else
write_bytes = num - i;
for (k = 0; k < ULP_BITS_2_BYTE_NR(write_bytes); k++) {
ulp_bs_put_msb(dst->data, dst->write_idx, ULP_BLOB_BYTE,
*src_buf);
dst->write_idx += ULP_BLOB_BYTE;
src_buf++;
}
remaining = write_bytes % ULP_BLOB_BYTE;
if (remaining) {
bluff = (*src_buf) & ((uint8_t)-1 <<
(ULP_BLOB_BYTE - remaining));
ulp_bs_put_msb(dst->data, dst->write_idx,
ULP_BLOB_BYTE, bluff);
dst->write_idx += remaining;
}
if (write_bytes != (num - i)) {
/* add the padding */
ulp_blob_pad_push(dst, pad);
if (remaining) {
ulp_bs_put_msb(dst->data, dst->write_idx,
ULP_BLOB_BYTE - remaining,
*src_buf);
dst->write_idx += ULP_BLOB_BYTE - remaining;
src_buf++;
}
}
i += write_bytes;
}
return 0;
}
/*
* Perform the blob buffer merge.
* This api makes the src blob merged to the dst blob.
* The block size and pad size help in padding the dst blob
*
* dst [in] The destination blob, the blob to be merged.
* src [in] The src blob.
* block_size [in] The size of the block after which padding gets applied.
* pad [in] The size of the pad to be applied.
*
* returns 0 on success.
*/
int32_t
ulp_blob_block_merge(struct ulp_blob *dst, struct ulp_blob *src,
uint32_t block_size, uint32_t pad)
{
if (dst->byte_order == BNXT_ULP_BYTE_ORDER_BE &&
src->byte_order == BNXT_ULP_BYTE_ORDER_BE)
return ulp_blob_msb_block_merge(dst, src, block_size, pad);
BNXT_TF_DBG(ERR, "block merge not implemented yet\n");
return -EINVAL;
}
int32_t
ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
uint16_t src_offset, uint16_t src_len)
{
uint32_t k, remaining;
uint16_t num;
uint8_t bluff;
uint8_t *src_buf = ulp_blob_data_get(src, &num);
if ((src_offset + src_len) > num)
return -EINVAL;
/* Only supporting BE for now */
if (src->byte_order != BNXT_ULP_BYTE_ORDER_BE ||
dst->byte_order != BNXT_ULP_BYTE_ORDER_BE)
return -EINVAL;
/* Handle if the source offset is not on a byte boundary */
remaining = src_offset % ULP_BLOB_BYTE;
if (remaining) {
bluff = src_buf[src_offset / ULP_BLOB_BYTE] & ((uint8_t)-1 >>
(ULP_BLOB_BYTE - remaining));
ulp_bs_put_msb(dst->data, dst->write_idx,
ULP_BLOB_BYTE, bluff);
dst->write_idx += remaining;
}
/* Push the byte aligned pieces */
for (k = 0; k < ULP_BITS_2_BYTE_NR(src_len); k++) {
ulp_bs_put_msb(dst->data, dst->write_idx, ULP_BLOB_BYTE,
*src_buf);
dst->write_idx += ULP_BLOB_BYTE;
src_buf++;
}
/* Handle the remaining if length is not a byte boundary */
remaining = src_len % ULP_BLOB_BYTE;
if (remaining) {
bluff = (*src_buf) & ((uint8_t)-1 <<
(ULP_BLOB_BYTE - remaining));
ulp_bs_put_msb(dst->data, dst->write_idx,
ULP_BLOB_BYTE, bluff);
dst->write_idx += remaining;
}
return 0;
}
/*
* Read data from the operand
*

64
drivers/net/bnxt/tf_ulp/ulp_utils.h
View File

@ -9,10 +9,12 @@
#include "bnxt.h"
#include "ulp_template_db_enum.h"
#define ULP_BUFFER_ALIGN_8_BITS 8
#define ULP_BUFFER_ALIGN_8_BYTE 8
#define ULP_BUFFER_ALIGN_16_BYTE 16
#define ULP_BUFFER_ALIGN_64_BYTE 64
#define ULP_64B_IN_BYTES 8
/*
* Macros for bitmap sets and gets
* These macros can be used if the val are power of 2.
@ -289,6 +291,16 @@ uint8_t *
ulp_blob_data_get(struct ulp_blob *blob,
uint16_t *datalen);
/*
* Get the data length of the binary blob.
*
* blob [in] The blob's data len to be retrieved.
*
* returns length of the binary blob
*/
uint16_t
ulp_blob_data_len_get(struct ulp_blob *blob);
/*
* Get data from the byte array in Little endian format.
*
@ -356,6 +368,20 @@ int32_t
ulp_blob_pad_push(struct ulp_blob *blob,
uint32_t datalen);
/*
* Adds pad to an initialized blob at the current offset based on
* the alignment.
*
* blob [in] The blob that needs to be aligned
*
* align [in] Alignment in bits.
*
* returns the number of pad bits added, -1 on failure
*/
int32_t
ulp_blob_pad_align(struct ulp_blob *blob,
uint32_t align);
/*
* Set the 64 bit swap start index of the binary blob.
*
@ -383,11 +409,13 @@ ulp_blob_perform_encap_swap(struct ulp_blob *blob);
* vice-versa.
*
* blob [in] The blob's data to be used for swap.
* chunk_size[in] the swap is done within the chunk in bytes
*
* returns void.
*/
void
ulp_blob_perform_byte_reverse(struct ulp_blob *blob);
ulp_blob_perform_byte_reverse(struct ulp_blob *blob,
uint32_t chunk_size);
/*
* Perform the blob buffer 64 bit word swap.
@ -413,6 +441,40 @@ ulp_blob_perform_64B_word_swap(struct ulp_blob *blob);
void
ulp_blob_perform_64B_byte_swap(struct ulp_blob *blob);
/*
* Perform the blob buffer merge.
* This api makes the src blob merged to the dst blob.
* The block size and pad size help in padding the dst blob
*
* dst [in] The destination blob, the blob to be merged.
* src [in] The src blob.
* block_size [in] The size of the block after which padding gets applied.
* pad [in] The size of the pad to be applied.
*
* returns 0 on success.
*/
int32_t
ulp_blob_block_merge(struct ulp_blob *dst, struct ulp_blob *src,
uint32_t block_size, uint32_t pad);
/*
* Append bits from src blob to dst blob.
* Only works on BE blobs
*
* dst [in/out] The destination blob to append to
*
* src [in] The src blob to append from
*
* src_offset [in] The bit offset from src to start at
*
* src_len [in] The number of bits to append to dst
*
* returns 0 on success, non-zero on error
*/
int32_t
ulp_blob_append(struct ulp_blob *dst, struct ulp_blob *src,
uint16_t src_offset, uint16_t src_len);
/*
* Read data from the operand
*