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net/qede/base: update firmware to 8.30.12.0

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Upgrade QEDE PMD FW to version 8.30.12.0.

The firmware upgrade change details are as:
 - Add support for steering by IP and UDP destination port.
 - Add source QP field for GSI offload.
 - Add UFP support.
 - Add support for outer IPv4 TX CSO with unknown tunnel type (in addition
   to inner header CSO).
 - Support flow ID in accelerated RFS flow.
 - Allow Doorbell on empty SPQ and LL2 TX queue (for doorbell recovery).
 - Enable PCI Relaxed Ordering for L2 RX data placement.
 - Additional enhancements and bug fixes

Signed-off-by: Rasesh Mody <rasesh.mody@cavium.com>
This commit is contained in:
Rasesh Mody 2017-09-18 18:51:31 -07:00 committed by Ferruh Yigit
parent 211507c164
commit 40cf1e753e
26 changed files with 1461 additions and 1138 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

750
drivers/net/qede/base/common_hsi.h
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@ -97,8 +97,8 @@
#define FW_MAJOR_VERSION 8
#define FW_MINOR_VERSION 20
#define FW_REVISION_VERSION 0
#define FW_MINOR_VERSION 30
#define FW_REVISION_VERSION 12
#define FW_ENGINEERING_VERSION 0
/***********************/
@ -106,73 +106,70 @@
/***********************/
/* PCI functions */
#define MAX_NUM_PORTS_K2 (4)
#define MAX_NUM_PORTS_BB (2)
#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
#define MAX_NUM_PORTS_BB (2)
#define MAX_NUM_PORTS_K2 (4)
#define MAX_NUM_PORTS_E5 (4)
#define MAX_NUM_PORTS (MAX_NUM_PORTS_E5)
#define MAX_NUM_PFS_K2 (16)
#define MAX_NUM_PFS_BB (8)
#define MAX_NUM_PFS (MAX_NUM_PFS_K2)
#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
#define MAX_NUM_PFS_BB (8)
#define MAX_NUM_PFS_K2 (16)
#define MAX_NUM_PFS_E5 (16)
#define MAX_NUM_PFS (MAX_NUM_PFS_E5)
#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
#define MAX_NUM_VFS_BB (120)
#define MAX_NUM_VFS_K2 (192)
#define E4_MAX_NUM_VFS (MAX_NUM_VFS_K2)
#define COMMON_MAX_NUM_VFS (240)
#define MAX_NUM_VFS_BB (120)
#define MAX_NUM_VFS_K2 (192)
#define MAX_NUM_VFS_E4 (MAX_NUM_VFS_K2)
#define MAX_NUM_VFS_E5 (240)
#define COMMON_MAX_NUM_VFS (MAX_NUM_VFS_E5)
#define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
#define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + E4_MAX_NUM_VFS)
#define MAX_NUM_FUNCTIONS_BB (MAX_NUM_PFS_BB + MAX_NUM_VFS_BB)
#define MAX_NUM_FUNCTIONS_K2 (MAX_NUM_PFS_K2 + MAX_NUM_VFS_K2)
#define MAX_NUM_FUNCTIONS (MAX_NUM_PFS + MAX_NUM_VFS_E4)
/* in both BB and K2, the VF number starts from 16. so for arrays containing all
* possible PFs and VFs - we need a constant for this size
*/
#define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
#define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2)
#define MAX_FUNCTION_NUMBER (MAX_NUM_PFS + E4_MAX_NUM_VFS)
#define MAX_FUNCTION_NUMBER_BB (MAX_NUM_PFS + MAX_NUM_VFS_BB)
#define MAX_FUNCTION_NUMBER_K2 (MAX_NUM_PFS + MAX_NUM_VFS_K2)
#define MAX_FUNCTION_NUMBER_E4 (MAX_NUM_PFS + MAX_NUM_VFS_E4)
#define MAX_FUNCTION_NUMBER_E5 (MAX_NUM_PFS + MAX_NUM_VFS_E5)
#define COMMON_MAX_FUNCTION_NUMBER (MAX_NUM_PFS + MAX_NUM_VFS_E5)
#define MAX_NUM_VPORTS_K2 (208)
#define MAX_NUM_VPORTS_BB (160)
#define MAX_NUM_VPORTS (MAX_NUM_VPORTS_K2)
#define MAX_NUM_VPORTS_K2 (208)
#define MAX_NUM_VPORTS_BB (160)
#define MAX_NUM_VPORTS_E4 (MAX_NUM_VPORTS_K2)
#define MAX_NUM_VPORTS_E5 (256)
#define COMMON_MAX_NUM_VPORTS (MAX_NUM_VPORTS_E5)
#define MAX_NUM_L2_QUEUES_K2 (320)
#define MAX_NUM_L2_QUEUES_BB (256)
#define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_K2)
#define MAX_NUM_L2_QUEUES_K2 (320)
#define MAX_NUM_L2_QUEUES_E5 (320) /* TODO_E5_VITALY - fix to 512 */
#define MAX_NUM_L2_QUEUES (MAX_NUM_L2_QUEUES_E5)
/* Traffic classes in network-facing blocks (PBF, BTB, NIG, BRB, PRS and QM) */
/* 4-Port K2. */
#define NUM_PHYS_TCS_4PORT_K2 (4)
#define NUM_OF_PHYS_TCS (8)
#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
#define LB_TC (NUM_OF_PHYS_TCS)
/* Num of possible traffic priority values */
#define NUM_OF_PRIO (8)
#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
#define MAX_PHYS_VOQS (NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB)
#define NUM_PHYS_TCS_4PORT_K2 4
#define NUM_PHYS_TCS_4PORT_TX_E5 6
#define NUM_PHYS_TCS_4PORT_RX_E5 4
#define NUM_OF_PHYS_TCS 8
#define PURE_LB_TC NUM_OF_PHYS_TCS
#define NUM_TCS_4PORT_K2 (NUM_PHYS_TCS_4PORT_K2 + 1)
#define NUM_TCS_4PORT_TX_E5 (NUM_PHYS_TCS_4PORT_TX_E5 + 1)
#define NUM_TCS_4PORT_RX_E5 (NUM_PHYS_TCS_4PORT_RX_E5 + 1)
#define NUM_OF_TCS (NUM_OF_PHYS_TCS + 1)
/* CIDs */
#define E4_NUM_OF_CONNECTION_TYPES (8)
#define NUM_OF_TASK_TYPES (8)
#define NUM_OF_LCIDS (320)
#define NUM_OF_LTIDS (320)
/* Clock values */
#define MASTER_CLK_FREQ_E4 (375e6)
#define STORM_CLK_FREQ_E4 (1000e6)
#define CLK25M_CLK_FREQ_E4 (25e6)
#define NUM_OF_CONNECTION_TYPES_E4 (8)
#define NUM_OF_CONNECTION_TYPES_E5 (16)
#define NUM_OF_TASK_TYPES (8)
#define NUM_OF_LCIDS (320)
#define NUM_OF_LTIDS (320)
/* Global PXP windows (GTT) */
#define NUM_OF_GTT 19
#define GTT_DWORD_SIZE_BITS 10
#define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
#define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS)
#define NUM_OF_GTT 19
#define GTT_DWORD_SIZE_BITS 10
#define GTT_BYTE_SIZE_BITS (GTT_DWORD_SIZE_BITS + 2)
#define GTT_DWORD_SIZE (1 << GTT_DWORD_SIZE_BITS)
/* Tools Version */
#define TOOLS_VERSION 10
@ -417,49 +414,51 @@
#define CAU_FSM_ETH_TX 1
/* Number of Protocol Indices per Status Block */
#define PIS_PER_SB 12
#define PIS_PER_SB_E4 12
#define PIS_PER_SB_E5 8
#define MAX_PIS_PER_SB_E4 OSAL_MAX_T(PIS_PER_SB_E4, PIS_PER_SB_E5)
/* fsm is stopped or not valid for this sb */
#define CAU_HC_STOPPED_STATE 3
#define CAU_HC_STOPPED_STATE 3
/* fsm is working without interrupt coalescing for this sb*/
#define CAU_HC_DISABLE_STATE 4
#define CAU_HC_DISABLE_STATE 4
/* fsm is working with interrupt coalescing for this sb*/
#define CAU_HC_ENABLE_STATE 0
#define CAU_HC_ENABLE_STATE 0
/*****************/
/* IGU CONSTANTS */
/*****************/
#define MAX_SB_PER_PATH_K2 (368)
#define MAX_SB_PER_PATH_BB (288)
#define MAX_TOT_SB_PER_PATH \
MAX_SB_PER_PATH_K2
#define MAX_SB_PER_PATH_K2 (368)
#define MAX_SB_PER_PATH_BB (288)
#define MAX_SB_PER_PATH_E5 (512)
#define MAX_TOT_SB_PER_PATH MAX_SB_PER_PATH_E5
#define MAX_SB_PER_PF_MIMD 129
#define MAX_SB_PER_PF_SIMD 64
#define MAX_SB_PER_VF 64
#define MAX_SB_PER_PF_MIMD 129
#define MAX_SB_PER_PF_SIMD 64
#define MAX_SB_PER_VF 64
/* Memory addresses on the BAR for the IGU Sub Block */
#define IGU_MEM_BASE 0x0000
#define IGU_MEM_BASE 0x0000
#define IGU_MEM_MSIX_BASE 0x0000
#define IGU_MEM_MSIX_UPPER 0x0101
#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
#define IGU_MEM_MSIX_BASE 0x0000
#define IGU_MEM_MSIX_UPPER 0x0101
#define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
#define IGU_MEM_PBA_MSIX_BASE 0x0200
#define IGU_MEM_PBA_MSIX_UPPER 0x0202
#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
#define IGU_MEM_PBA_MSIX_BASE 0x0200
#define IGU_MEM_PBA_MSIX_UPPER 0x0202
#define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
#define IGU_CMD_INT_ACK_BASE 0x0400
#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
MAX_TOT_SB_PER_PATH - \
1)
#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
#define IGU_CMD_INT_ACK_BASE 0x0400
#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
MAX_TOT_SB_PER_PATH - \
1)
#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
#define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
#define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
#define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
#define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
@ -467,8 +466,8 @@
#define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
#define IGU_CMD_PROD_UPD_BASE 0x0600
#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
MAX_TOT_SB_PER_PATH - \
#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE + \
MAX_TOT_SB_PER_PATH - \
1)
#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
@ -491,16 +490,16 @@
#define PXP_PER_PF_ENTRY_SIZE 8
#define PXP_NUM_GLOBAL_WINDOWS 243
#define PXP_GLOBAL_ENTRY_SIZE 4
#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
#define PXP_ADMIN_WINDOW_ALLOWED_LENGTH 4
#define PXP_PF_WINDOW_ADMIN_START 0
#define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
#define PXP_PF_WINDOW_ADMIN_END (PXP_PF_WINDOW_ADMIN_START + \
PXP_PF_WINDOW_ADMIN_LENGTH - 1)
PXP_PF_WINDOW_ADMIN_LENGTH - 1)
#define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
#define PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH (PXP_NUM_PF_WINDOWS * \
PXP_PER_PF_ENTRY_SIZE)
#define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
#define PXP_PF_WINDOW_ADMIN_PER_PF_END (PXP_PF_WINDOW_ADMIN_PER_PF_START + \
PXP_PF_WINDOW_ADMIN_PER_PF_LENGTH - 1)
#define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
#define PXP_PF_WINDOW_ADMIN_GLOBAL_LENGTH (PXP_NUM_GLOBAL_WINDOWS * \
PXP_GLOBAL_ENTRY_SIZE)
@ -575,19 +574,79 @@
#define PXP_BAR0_FIRST_INVALID_ADDRESS \
(PXP_BAR0_END_PSDM + 1)
#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
/* VF BAR */
#define PXP_VF_BAR0 0
/* ILT Records */
#define PXP_VF_BAR0_START_IGU 0
#define PXP_VF_BAR0_IGU_LENGTH 0x3000
#define PXP_VF_BAR0_END_IGU \
(PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1)
#define PXP_VF_BAR0_START_DQ 0x3000
#define PXP_VF_BAR0_DQ_LENGTH 0x200
#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
(PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS \
(PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4)
#define PXP_VF_BAR0_END_DQ \
(PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1)
#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
#define PXP_VF_BAR0_END_TSDM_ZONE_B \
(PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
#define PXP_VF_BAR0_END_MSDM_ZONE_B \
(PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
#define PXP_VF_BAR0_END_USDM_ZONE_B \
(PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
#define PXP_VF_BAR0_END_XSDM_ZONE_B \
(PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
#define PXP_VF_BAR0_END_YSDM_ZONE_B \
(PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
#define PXP_VF_BAR0_END_PSDM_ZONE_B \
(PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_GRC 0x3E00
#define PXP_VF_BAR0_GRC_LENGTH 0x200
#define PXP_VF_BAR0_END_GRC \
(PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1)
#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
#define PXP_VF_BAR0_START_IGU2 0x10000
#define PXP_VF_BAR0_IGU2_LENGTH 0xD000
#define PXP_VF_BAR0_END_IGU2 \
(PXP_VF_BAR0_START_IGU2 + PXP_VF_BAR0_IGU2_LENGTH - 1)
#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
// ILT Records
#define PXP_NUM_ILT_RECORDS_BB 7600
#define PXP_NUM_ILT_RECORDS_K2 11000
#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
/* Host Interface */
#define PXP_QUEUES_ZONE_MAX_NUM 320
#define MAX_NUM_ILT_RECORDS \
OSAL_MAX_T(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
#define PXP_NUM_ILT_RECORDS_E5 13664
// Host Interface
#define PXP_QUEUES_ZONE_MAX_NUM_E4 320
#define PXP_QUEUES_ZONE_MAX_NUM_E5 512
/*****************/
@ -635,7 +694,8 @@
/******************/
/* Number of PBF command queue lines. Each line is 32B. */
#define PBF_MAX_CMD_LINES 3328
#define PBF_MAX_CMD_LINES_E4 3328
#define PBF_MAX_CMD_LINES_E5 5280
/* Number of BTB blocks. Each block is 256B. */
#define BTB_MAX_BLOCKS 1440
@ -645,17 +705,6 @@
/*****************/
#define PRS_GFT_CAM_LINES_NO_MATCH 31
/* Async data KCQ CQE */
struct async_data {
/* Context ID of the connection */
__le32 cid;
/* Task Id of the task (for error that happened on a a task) */
__le16 itid;
/* error code - relevant only if the opcode indicates its an error */
u8 error_code;
/* internal fw debug parameter */
u8 fw_debug_param;
};
/*
* Interrupt coalescing TimeSet
@ -683,22 +732,29 @@ struct eth_rx_prod_data {
__le16 cqe_prod /* CQE producer. */;
};
struct regpair {
__le32 lo /* low word for reg-pair */;
__le32 hi /* high word for reg-pair */;
struct tcp_ulp_connect_done_params {
__le16 mss;
u8 snd_wnd_scale;
u8 flags;
#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1
#define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0
#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F
#define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_SHIFT 1
};
/*
* Event Ring VF-PF Channel data
*/
struct vf_pf_channel_eqe_data {
struct regpair msg_addr /* VF-PF message address */;
struct iscsi_connect_done_results {
__le16 icid /* Context ID of the connection */;
__le16 conn_id /* Driver connection ID */;
/* decided tcp params after connect done */
struct tcp_ulp_connect_done_params params;
};
struct iscsi_eqe_data {
__le32 cid /* Context ID of the connection */;
/* Task Id of the task (for error that happened on a a task) */;
__le16 conn_id;
__le16 icid /* Context ID of the connection */;
__le16 conn_id /* Driver connection ID */;
__le16 reserved;
/* error code - relevant only if the opcode indicates its an error */
u8 error_code;
u8 error_pdu_opcode_reserved;
@ -714,52 +770,10 @@ struct iscsi_eqe_data {
#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
};
/*
* Event Ring malicious VF data
*/
struct malicious_vf_eqe_data {
u8 vf_id /* Malicious VF ID */;
u8 err_id /* Malicious VF error */;
__le16 reserved[3];
};
/*
* Event Ring initial cleanup data
* Multi function mode
*/
struct initial_cleanup_eqe_data {
u8 vfId /* VF ID */;
u8 reserved[7];
};
/*
* Event Data Union
*/
union event_ring_data {
u8 bytes[8] /* Byte Array */;
struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */;
struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */;
struct regpair roceHandle /* Dedicated field for RDMA data */;
struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */;
struct initial_cleanup_eqe_data vf_init_cleanup
/* VF Initial Cleanup data */;
};
/* Event Ring Entry */
struct event_ring_entry {
u8 protocol_id /* Event Protocol ID */;
u8 opcode /* Event Opcode */;
__le16 reserved0 /* Reserved */;
__le16 echo /* Echo value from ramrod data on the host */;
u8 fw_return_code /* FW return code for SP ramrods */;
u8 flags;
/* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */
#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
union event_ring_data data;
};
/* Multi function mode */
enum mf_mode {
ERROR_MODE /* Unsupported mode */,
MF_OVLAN /* Multi function based on outer VLAN */,
@ -783,6 +797,12 @@ enum protocol_type {
};
struct regpair {
__le32 lo /* low word for reg-pair */;
__le32 hi /* high word for reg-pair */;
};
/*
* Ustorm Queue Zone
@ -852,6 +872,18 @@ struct cau_sb_entry {
#define CAU_SB_ENTRY_TPH_SHIFT 31
};
/*
* Igu cleanup bit values to distinguish between clean or producer consumer
* update.
*/
enum command_type_bit {
IGU_COMMAND_TYPE_NOP = 0,
IGU_COMMAND_TYPE_SET = 1,
MAX_COMMAND_TYPE_BIT
};
/* core doorbell data */
struct core_db_data {
u8 params;
@ -1008,7 +1040,7 @@ struct db_rdma_dpm_params {
#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1 /* RoCE S flag */
#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x3
#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1
#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30
/* Connection type is iWARP */
#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
@ -1072,9 +1104,9 @@ enum igu_seg_access {
* to the last-ethertype)
*/
enum l3_type {
e_l3Type_unknown,
e_l3Type_ipv4,
e_l3Type_ipv6,
e_l3_type_unknown,
e_l3_type_ipv4,
e_l3_type_ipv6,
MAX_L3_TYPE
};
@ -1085,9 +1117,9 @@ enum l3_type {
* first fragment, the protocol-type should be set to none.
*/
enum l4_protocol {
e_l4Protocol_none,
e_l4Protocol_tcp,
e_l4Protocol_udp,
e_l4_protocol_none,
e_l4_protocol_tcp,
e_l4_protocol_udp,
MAX_L4_PROTOCOL
};
@ -1311,260 +1343,230 @@ struct pxp_vf_zone_a_permission {
* Rdif context
*/
struct rdif_task_context {
__le32 initialRefTag;
__le16 appTagValue;
__le16 appTagMask;
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
u8 flags0;
#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
/* 0 = IP checksum, 1 = CRC */
#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
/* 1/2/3 - Protection Type */
#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
/* 0=0x0000, 1=0xffff */
#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
/* Keep reference tag constant */
#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7
u8 partialDifData[7];
__le16 partialCrcValue;
__le16 partialChecksumValue;
__le32 offsetInIO;
#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7
u8 partial_dif_data[7];
__le16 partial_crc_value;
__le16 partial_checksum_value;
__le32 offset_in_io;
__le16 flags1;
#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
#define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
/* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
/* 0=None, 1=DIF, 2=DIX */
#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
#define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
#define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
/* DIF tag right at the beginning of DIF interval */
#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
/* 0=None, 1=DIF */
#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
/* Forward application tag with mask */
#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14
#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
/* Forward reference tag with mask */
#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15
#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
__le16 state;
#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0
#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
#define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1
#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8
#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4
#define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
#define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8
#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9
/* mask for refernce tag handling */
#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10
#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
#define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
#define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10
#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
__le32 reserved2;
};
/* RSS hash type */
/*
* RSS hash type
*/
enum rss_hash_type {
RSS_HASH_TYPE_DEFAULT = 0,
RSS_HASH_TYPE_IPV4 = 1,
RSS_HASH_TYPE_TCP_IPV4 = 2,
RSS_HASH_TYPE_IPV6 = 3,
RSS_HASH_TYPE_TCP_IPV6 = 4,
RSS_HASH_TYPE_UDP_IPV4 = 5,
RSS_HASH_TYPE_UDP_IPV6 = 6,
RSS_HASH_TYPE_DEFAULT = 0,
RSS_HASH_TYPE_IPV4 = 1,
RSS_HASH_TYPE_TCP_IPV4 = 2,
RSS_HASH_TYPE_IPV6 = 3,
RSS_HASH_TYPE_TCP_IPV6 = 4,
RSS_HASH_TYPE_UDP_IPV4 = 5,
RSS_HASH_TYPE_UDP_IPV6 = 6,
MAX_RSS_HASH_TYPE
};
/* status block structure */
struct status_block {
__le16 pi_array[PIS_PER_SB];
__le32 sb_num;
#define STATUS_BLOCK_SB_NUM_MASK 0x1FF
#define STATUS_BLOCK_SB_NUM_SHIFT 0
#define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
#define STATUS_BLOCK_ZERO_PAD_SHIFT 9
#define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
#define STATUS_BLOCK_ZERO_PAD2_SHIFT 16
/*
* status block structure
*/
struct status_block_e4 {
__le16 pi_array[PIS_PER_SB_E4];
__le32 sb_num;
#define STATUS_BLOCK_E4_SB_NUM_MASK 0x1FF
#define STATUS_BLOCK_E4_SB_NUM_SHIFT 0
#define STATUS_BLOCK_E4_ZERO_PAD_MASK 0x7F
#define STATUS_BLOCK_E4_ZERO_PAD_SHIFT 9
#define STATUS_BLOCK_E4_ZERO_PAD2_MASK 0xFFFF
#define STATUS_BLOCK_E4_ZERO_PAD2_SHIFT 16
__le32 prod_index;
#define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
#define STATUS_BLOCK_PROD_INDEX_SHIFT 0
#define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
#define STATUS_BLOCK_E4_PROD_INDEX_MASK 0xFFFFFF
#define STATUS_BLOCK_E4_PROD_INDEX_SHIFT 0
#define STATUS_BLOCK_E4_ZERO_PAD3_MASK 0xFF
#define STATUS_BLOCK_E4_ZERO_PAD3_SHIFT 24
};
/* VF BAR */
#define PXP_VF_BAR0 0
/*
* status block structure
*/
struct status_block_e5 {
__le16 pi_array[PIS_PER_SB_E5];
__le32 sb_num;
#define STATUS_BLOCK_E5_SB_NUM_MASK 0x1FF
#define STATUS_BLOCK_E5_SB_NUM_SHIFT 0
#define STATUS_BLOCK_E5_ZERO_PAD_MASK 0x7F
#define STATUS_BLOCK_E5_ZERO_PAD_SHIFT 9
#define STATUS_BLOCK_E5_ZERO_PAD2_MASK 0xFFFF
#define STATUS_BLOCK_E5_ZERO_PAD2_SHIFT 16
__le32 prod_index;
#define STATUS_BLOCK_E5_PROD_INDEX_MASK 0xFFFFFF
#define STATUS_BLOCK_E5_PROD_INDEX_SHIFT 0
#define STATUS_BLOCK_E5_ZERO_PAD3_MASK 0xFF
#define STATUS_BLOCK_E5_ZERO_PAD3_SHIFT 24
};
#define PXP_VF_BAR0_START_GRC 0x3E00
#define PXP_VF_BAR0_GRC_LENGTH 0x200
#define PXP_VF_BAR0_END_GRC \
(PXP_VF_BAR0_START_GRC + PXP_VF_BAR0_GRC_LENGTH - 1)
#define PXP_VF_BAR0_START_IGU 0
#define PXP_VF_BAR0_IGU_LENGTH 0x3000
#define PXP_VF_BAR0_END_IGU \
(PXP_VF_BAR0_START_IGU + PXP_VF_BAR0_IGU_LENGTH - 1)
#define PXP_VF_BAR0_START_DQ 0x3000
#define PXP_VF_BAR0_DQ_LENGTH 0x200
#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
(PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS \
(PXP_VF_BAR0_ME_OPAQUE_ADDRESS + 4)
#define PXP_VF_BAR0_END_DQ \
(PXP_VF_BAR0_START_DQ + PXP_VF_BAR0_DQ_LENGTH - 1)
#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
#define PXP_VF_BAR0_END_TSDM_ZONE_B \
(PXP_VF_BAR0_START_TSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
#define PXP_VF_BAR0_END_MSDM_ZONE_B \
(PXP_VF_BAR0_START_MSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
#define PXP_VF_BAR0_END_USDM_ZONE_B \
(PXP_VF_BAR0_START_USDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
#define PXP_VF_BAR0_END_XSDM_ZONE_B \
(PXP_VF_BAR0_START_XSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
#define PXP_VF_BAR0_END_YSDM_ZONE_B \
(PXP_VF_BAR0_START_YSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
#define PXP_VF_BAR0_END_PSDM_ZONE_B \
(PXP_VF_BAR0_START_PSDM_ZONE_B + PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
/*
* Tdif context
*/
struct tdif_task_context {
__le32 initialRefTag;
__le16 appTagValue;
__le16 appTagMask;
__le16 partialCrcValueB;
__le16 partialChecksumValueB;
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
__le16 partial_crc_value_b;
__le16 partial_checksum_value_b;
__le16 stateB;
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1
#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4
#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8
#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9
#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
u8 reserved1;
u8 flags0;
#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
/* 0 = IP checksum, 1 = CRC */
#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
/* 1/2/3 - Protection Type */
#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
/* 0=0x0000, 1=0xffff */
#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
__le32 flags1;
#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
#define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
/* 0=512B, 1=1KB, 2=2KB, 3=4KB, 4=8KB */
#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
/* 0=None, 1=DIF, 2=DIX */
#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
#define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
#define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
/* DIF tag right at the beginning of DIF interval */
#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
/* reserved */
#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1 /* reserved */
#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
/* 0=None, 1=DIF */
#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1
#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23
#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14
#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18
#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22
#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23
/* mask for refernce tag handling */
#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24
#define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
#define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24
/* Forward application tag with mask */
#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28
#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28
/* Forward reference tag with mask */
#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29
#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29
/* Keep reference tag constant */
#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30
#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
__le32 offsetInIOB;
__le16 partialCrcValueA;
__le16 partialChecksumValueA;
__le32 offsetInIOA;
u8 partialDifDataA[8];
u8 partialDifDataB[8];
#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30
#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
__le32 offset_in_io_b;
__le16 partial_crc_value_a;
__le16 partial_checksum_value_a;
__le32 offset_in_io_a;
u8 partial_dif_data_a[8];
u8 partial_dif_data_b[8];
};

2
drivers/net/qede/base/ecore.h
View File

@ -846,8 +846,8 @@ static OSAL_INLINE u8 ecore_concrete_to_sw_fid(u32 concrete_fid)
return sw_fid;
}
#define PURE_LB_TC 8
#define PKT_LB_TC 9
#define MAX_NUM_VOQS_E4 20
int ecore_configure_vport_wfq(struct ecore_dev *p_dev, u16 vp_id, u32 rate);
void ecore_configure_vp_wfq_on_link_change(struct ecore_dev *p_dev,

10
drivers/net/qede/base/ecore_cxt.c
View File

@ -59,8 +59,8 @@
/* connection context union */
union conn_context {
struct core_conn_context core_ctx;
struct eth_conn_context eth_ctx;
struct e4_core_conn_context core_ctx;
struct e4_eth_conn_context eth_ctx;
};
/* TYPE-0 task context - iSCSI, FCOE */
@ -1432,11 +1432,14 @@ static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
{
struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
struct ecore_mcp_link_state *p_link;
struct ecore_qm_iids iids;
OSAL_MEM_ZERO(&iids, sizeof(iids));
ecore_cxt_qm_iids(p_hwfn, &iids);
p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output;
ecore_qm_pf_rt_init(p_hwfn, p_ptt, p_hwfn->port_id,
p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
iids.cids, iids.vf_cids, iids.tids,
@ -1445,7 +1448,8 @@ void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
qm_info->num_vf_pqs,
qm_info->start_vport,
qm_info->num_vports, qm_info->pf_wfq,
qm_info->pf_rl, p_hwfn->qm_info.qm_pq_params,
qm_info->pf_rl, p_link->speed,
p_hwfn->qm_info.qm_pq_params,
p_hwfn->qm_info.qm_vport_params);
}

2
drivers/net/qede/base/ecore_dcbx.c
View File

@ -931,8 +931,6 @@ void ecore_dcbx_set_pf_update_params(struct ecore_dcbx_results *p_src,
struct protocol_dcb_data *p_dcb_data;
u8 update_flag;
p_dest->pf_id = p_src->pf_id;
update_flag = p_src->arr[DCBX_PROTOCOL_ETH].update;
p_dest->update_eth_dcb_data_mode = update_flag;
update_flag = p_src->arr[DCBX_PROTOCOL_IWARP].update;

17
drivers/net/qede/base/ecore_dev.c
View File

@ -665,7 +665,7 @@ static void ecore_init_qm_port_params(struct ecore_hwfn *p_hwfn)
p_qm_port->active = 1;
p_qm_port->active_phys_tcs = active_phys_tcs;
p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports;
p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES_E4 / num_ports;
p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports;
}
}
@ -2059,7 +2059,21 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
int hw_mode)
{
u32 ppf_to_eng_sel[NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE];
u32 val;
enum _ecore_status_t rc = ECORE_SUCCESS;
u8 i;
/* In CMT for non-RoCE packets - use connection based classification */
val = ECORE_IS_CMT(p_hwfn->p_dev) ? 0x8 : 0x0;
for (i = 0; i < NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE; i++)
ppf_to_eng_sel[i] = val;
STORE_RT_REG_AGG(p_hwfn, NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET,
ppf_to_eng_sel);
/* In CMT the gate should be cleared by the 2nd hwfn */
if (!ECORE_IS_CMT(p_hwfn->p_dev) || !IS_LEAD_HWFN(p_hwfn))
STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);
rc = ecore_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id,
hw_mode);
@ -3959,7 +3973,6 @@ void ecore_prepare_hibernate(struct ecore_dev *p_dev)
"Mark hw/fw uninitialized\n");
p_hwfn->hw_init_done = false;
p_hwfn->first_on_engine = false;
ecore_ptt_invalidate(p_hwfn);
}

245
drivers/net/qede/base/ecore_hsi_common.h
View File

@ -618,7 +618,7 @@ struct ustorm_core_conn_st_ctx {
/*
* core connection context
*/
struct core_conn_context {
struct e4_core_conn_context {
/* ystorm storm context */
struct ystorm_core_conn_st_ctx ystorm_st_context;
struct regpair ystorm_st_padding[2] /* padding */;
@ -661,6 +661,7 @@ enum core_event_opcode {
CORE_EVENT_RX_QUEUE_START,
CORE_EVENT_RX_QUEUE_STOP,
CORE_EVENT_RX_QUEUE_FLUSH,
CORE_EVENT_TX_QUEUE_UPDATE,
MAX_CORE_EVENT_OPCODE
};
@ -745,6 +746,7 @@ enum core_ramrod_cmd_id {
CORE_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */,
CORE_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */,
CORE_RAMROD_RX_QUEUE_FLUSH /* RX Flush queue Ramrod */,
CORE_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */,
MAX_CORE_RAMROD_CMD_ID
};
@ -858,7 +860,8 @@ struct core_rx_gsi_offload_cqe {
__le16 src_mac_addrlo /* lo 2 bytes of source mac address */;
/* These are the lower 16 bit of QP id in RoCE BTH header */
__le16 qp_id;
__le32 gid_dst[4] /* Gid destination address */;
__le32 src_qp /* Source QP from DETH header */;
__le32 reserved[3];
};
/*
@ -899,7 +902,10 @@ struct core_rx_start_ramrod_data {
u8 drop_ttl0_flg /* drop packet with ttl0 if set */;
__le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
/* if set, 802.1q tags will be removed and copied to CQE */
u8 inner_vlan_removal_en;
/* if set, 802.1q tags will be removed and copied to CQE */
u8 inner_vlan_stripping_en;
/* if set, outer tag wont be stripped, valid only in MF OVLAN. */
u8 outer_vlan_stripping_dis;
u8 queue_id /* Light L2 RX Queue ID */;
u8 main_func_queue /* Is this the main queue for the PF */;
/* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if
@ -916,7 +922,7 @@ struct core_rx_start_ramrod_data {
struct core_rx_action_on_error action_on_error;
/* set when in GSI offload mode on ROCE connection */
u8 gsi_offload_flag;
u8 reserved[7];
u8 reserved[6];
};
@ -938,48 +944,51 @@ struct core_rx_stop_ramrod_data {
struct core_tx_bd_data {
__le16 as_bitfield;
/* Do not allow additional VLAN manipulations on this packet (DCB) */
#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1
#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0
/* Insert VLAN into packet */
#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1
#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1
/* This is the first BD of the packet (for debug) */
#define CORE_TX_BD_DATA_START_BD_MASK 0x1
#define CORE_TX_BD_DATA_START_BD_SHIFT 2
#define CORE_TX_BD_DATA_START_BD_MASK 0x1
#define CORE_TX_BD_DATA_START_BD_SHIFT 2
/* Calculate the IP checksum for the packet */
#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1
#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3
/* Calculate the L4 checksum for the packet */
#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1
#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4
/* Packet is IPv6 with extensions */
#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1
#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5
/* If IPv6+ext, and if l4_csum is 1, than this field indicates L4 protocol:
* 0-TCP, 1-UDP
*/
#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1
#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6
/* The pseudo checksum mode to place in the L4 checksum field. Required only
* when IPv6+ext and l4_csum is set. (use enum core_l4_pseudo_checksum_mode)
*/
#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1
#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7
/* Number of BDs that make up one packet - width wide enough to present
* CORE_LL2_TX_MAX_BDS_PER_PACKET
*/
#define CORE_TX_BD_DATA_NBDS_MASK 0xF
#define CORE_TX_BD_DATA_NBDS_SHIFT 8
#define CORE_TX_BD_DATA_NBDS_MASK 0xF
#define CORE_TX_BD_DATA_NBDS_SHIFT 8
/* Use roce_flavor enum - Differentiate between Roce flavors is valid when
* connType is ROCE (use enum core_roce_flavor_type)
*/
#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1
#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12
/* Calculate ip length */
#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
#define CORE_TX_BD_DATA_RESERVED0_MASK 0x3
#define CORE_TX_BD_DATA_RESERVED0_SHIFT 14
#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1
#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13
/* disables the STAG insertion, relevant only in MF OVLAN mode. */
#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1
#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14
#define CORE_TX_BD_DATA_RESERVED0_MASK 0x1
#define CORE_TX_BD_DATA_RESERVED0_SHIFT 15
};
/*
@ -1045,6 +1054,17 @@ struct core_tx_stop_ramrod_data {
};
/*
* Ramrod data for tx queue update ramrod
*/
struct core_tx_update_ramrod_data {
u8 update_qm_pq_id_flg /* Flag to Update QM PQ ID */;
u8 reserved0;
__le16 qm_pq_id /* Updated QM PQ ID */;
__le32 reserved1[1];
};
/*
* Enum flag for what type of dcb data to update
*/
@ -1181,6 +1201,63 @@ struct eth_ustorm_per_queue_stat {
};
/*
* Event Ring VF-PF Channel data
*/
struct vf_pf_channel_eqe_data {
struct regpair msg_addr /* VF-PF message address */;
};
/*
* Event Ring malicious VF data
*/
struct malicious_vf_eqe_data {
u8 vf_id /* Malicious VF ID */;
u8 err_id /* Malicious VF error (use enum malicious_vf_error_id) */;
__le16 reserved[3];
};
/*
* Event Ring initial cleanup data
*/
struct initial_cleanup_eqe_data {
u8 vf_id /* VF ID */;
u8 reserved[7];
};
/*
* Event Data Union
*/
union event_ring_data {
u8 bytes[8] /* Byte Array */;
struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */;
struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */;
/* Dedicated fields to iscsi connect done results */
struct iscsi_connect_done_results iscsi_conn_done_info;
struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */;
/* VF Initial Cleanup data */
struct initial_cleanup_eqe_data vf_init_cleanup;
};
/*
* Event Ring Entry
*/
struct event_ring_entry {
u8 protocol_id /* Event Protocol ID (use enum protocol_type) */;
u8 opcode /* Event Opcode */;
__le16 reserved0 /* Reserved */;
__le16 echo /* Echo value from ramrod data on the host */;
u8 fw_return_code /* FW return code for SP ramrods */;
u8 flags;
/* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */
#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
union event_ring_data data;
};
/*
* Event Ring Next Page Address
*/
@ -1210,6 +1287,18 @@ enum fw_flow_ctrl_mode {
};
/*
* GFT profile type.
*/
enum gft_profile_type {
GFT_PROFILE_TYPE_4_TUPLE /* 4 tuple, IP type and L4 type match. */,
/* L4 destination port, IP type and L4 type match. */
GFT_PROFILE_TYPE_L4_DST_PORT,
GFT_PROFILE_TYPE_IP_DST_PORT /* IP destination port and IP type. */,
MAX_GFT_PROFILE_TYPE
};
/*
* Major and Minor hsi Versions
*/
@ -1310,6 +1399,34 @@ struct mstorm_vf_zone {
};
/*
* vlan header including TPID and TCI fields
*/
struct vlan_header {
__le16 tpid /* Tag Protocol Identifier */;
__le16 tci /* Tag Control Information */;
};
/*
* outer tag configurations
*/
struct outer_tag_config_struct {
/* Enables the STAG Priority Change , Should be 1 for Bette Davis and UFP with
* Host Control mode. Else - 0
*/
u8 enable_stag_pri_change;
/* If inner_to_outer_pri_map is initialize then set pri_map_valid */
u8 pri_map_valid;
u8 reserved[2];
/* In case mf_mode is MF_OVLAN, this field specifies the outer tag protocol
* identifier and outer tag control information
*/
struct vlan_header outer_tag;
/* Map from inner to outer priority. Set pri_map_valid when init map */
u8 inner_to_outer_pri_map[8];
};
/*
* personality per PF
*/
@ -1361,7 +1478,6 @@ struct pf_start_ramrod_data {
struct regpair consolid_q_pbl_addr;
/* tunnel configuration. */
struct pf_start_tunnel_config tunnel_config;
__le32 reserved;
__le16 event_ring_sb_id /* Status block ID */;
/* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */
u8 base_vf_id;
@ -1381,16 +1497,11 @@ struct pf_start_ramrod_data {
u8 integ_phase /* Integration phase */;
/* If set, inter-pf tx switching is allowed in Switch Independent func mode */
u8 allow_npar_tx_switching;
/* Map from inner to outer priority. Set pri_map_valid when init map */
u8 inner_to_outer_pri_map[8];
/* If inner_to_outer_pri_map is initialize then set pri_map_valid */
u8 pri_map_valid;
/* In case mf_mode is MF_OVLAN, this field specifies the outer vlan
* (lower 16 bits) and ethType to use (higher 16 bits)
*/
__le32 outer_tag;
u8 reserved0;
/* FP HSI version to be used by FW */
struct hsi_fp_ver_struct hsi_fp_ver;
/* Outer tag configurations */
struct outer_tag_config_struct outer_tag_config;
};
@ -1441,15 +1552,19 @@ struct pf_update_tunnel_config {
* Data for port update ramrod
*/
struct pf_update_ramrod_data {
u8 pf_id;
u8 update_eth_dcb_data_mode /* Update Eth DCB data indication */;
u8 update_fcoe_dcb_data_mode /* Update FCOE DCB data indication */;
u8 update_iscsi_dcb_data_mode /* Update iSCSI DCB data indication */;
/* Update Eth DCB data indication (use enum dcb_dscp_update_mode) */
u8 update_eth_dcb_data_mode;
/* Update FCOE DCB data indication (use enum dcb_dscp_update_mode) */
u8 update_fcoe_dcb_data_mode;
/* Update iSCSI DCB data indication (use enum dcb_dscp_update_mode) */
u8 update_iscsi_dcb_data_mode;
u8 update_roce_dcb_data_mode /* Update ROCE DCB data indication */;
/* Update RROCE (RoceV2) DCB data indication */
u8 update_rroce_dcb_data_mode;
u8 update_iwarp_dcb_data_mode /* Update IWARP DCB data indication */;
u8 update_mf_vlan_flag /* Update MF outer vlan Id */;
/* Update Enable STAG Priority Change indication */
u8 update_enable_stag_pri_change;
struct protocol_dcb_data eth_dcb_data /* core eth related fields */;
struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */;
/* core iscsi related fields */
@ -1460,7 +1575,11 @@ struct pf_update_ramrod_data {
/* core iwarp related fields */
struct protocol_dcb_data iwarp_dcb_data;
__le16 mf_vlan /* new outer vlan id value */;
__le16 reserved;
/* enables the inner to outer TAG priority mapping. Should be 1 for Bette Davis
* and UFP with Host Control mode, else - 0.
*/
u8 enable_stag_pri_change;
u8 reserved;
/* tunnel configuration. */
struct pf_update_tunnel_config tunnel_config;
};
@ -1745,6 +1864,7 @@ enum vf_zone_size_mode {
/*
* Attentions status block
*/
@ -1757,17 +1877,6 @@ struct atten_status_block {
};
/*
* Igu cleanup bit values to distinguish between clean or producer consumer
* update.
*/
enum command_type_bit {
IGU_COMMAND_TYPE_NOP = 0,
IGU_COMMAND_TYPE_SET = 1,
MAX_COMMAND_TYPE_BIT
};
/*
* DMAE command
*/
@ -2200,23 +2309,23 @@ struct qm_rf_opportunistic_mask {
/*
* QM hardware structure of QM map memory
*/
struct qm_rf_pq_map {
struct qm_rf_pq_map_e4 {
__le32 reg;
#define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 /* PQ active */
#define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0
#define QM_RF_PQ_MAP_RL_ID_MASK 0xFF /* RL ID */
#define QM_RF_PQ_MAP_RL_ID_SHIFT 1
#define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1 /* PQ active */
#define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0
#define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF /* RL ID */
#define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1
/* the first PQ associated with the VPORT and VOQ of this PQ */
#define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF
#define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9
#define QM_RF_PQ_MAP_VOQ_MASK 0x1F /* VOQ */
#define QM_RF_PQ_MAP_VOQ_SHIFT 18
#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
#define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23
#define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 /* RL active */
#define QM_RF_PQ_MAP_RL_VALID_SHIFT 25
#define QM_RF_PQ_MAP_RESERVED_MASK 0x3F
#define QM_RF_PQ_MAP_RESERVED_SHIFT 26
#define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF
#define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9
#define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F /* VOQ */
#define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18
#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */
#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23
#define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1 /* RL active */
#define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25
#define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F
#define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26
};

6
drivers/net/qede/base/ecore_hsi_debug_tools.h
View File

@ -1053,7 +1053,7 @@ enum dbg_status {
DBG_STATUS_MCP_TRACE_NO_META,
DBG_STATUS_MCP_COULD_NOT_HALT,
DBG_STATUS_MCP_COULD_NOT_RESUME,
DBG_STATUS_DMAE_FAILED,
DBG_STATUS_RESERVED2,
DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
DBG_STATUS_IGU_FIFO_BAD_DATA,
DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
@ -1107,7 +1107,9 @@ struct dbg_tools_data {
u8 chip_id /* Chip ID (from enum chip_ids) */;
u8 platform_id /* Platform ID */;
u8 initialized /* Indicates if the data was initialized */;
u8 reserved;
u8 use_dmae /* Indicates if DMAE should be used */;
/* Numbers of registers that were read since last log */
__le32 num_regs_read;
};

63
drivers/net/qede/base/ecore_hsi_eth.h
View File

@ -669,7 +669,7 @@ struct mstorm_eth_conn_st_ctx {
/*
* eth connection context
*/
struct eth_conn_context {
struct e4_eth_conn_context {
/* tstorm storm context */
struct tstorm_eth_conn_st_ctx tstorm_st_context;
struct regpair tstorm_st_padding[2] /* padding */;
@ -765,6 +765,7 @@ enum eth_event_opcode {
ETH_EVENT_RX_DELETE_UDP_FILTER,
ETH_EVENT_RX_CREATE_GFT_ACTION,
ETH_EVENT_RX_GFT_UPDATE_FILTER,
ETH_EVENT_TX_QUEUE_UPDATE,
MAX_ETH_EVENT_OPCODE
};
@ -882,6 +883,7 @@ enum eth_ramrod_cmd_id {
ETH_RAMROD_RX_CREATE_GFT_ACTION /* RX - Create a Gft Action */,
/* RX - Add/Delete a GFT Filter to the Searcher */
ETH_RAMROD_GFT_UPDATE_FILTER,
ETH_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */,
MAX_ETH_RAMROD_CMD_ID
};
@ -1092,7 +1094,7 @@ struct eth_vport_tx_mode {
/*
* Ramrod data for rx create gft action
* GFT filter update action type.
*/
enum gft_filter_update_action {
GFT_ADD_FILTER,
@ -1101,16 +1103,6 @@ enum gft_filter_update_action {
};
/*
* Ramrod data for rx create gft action
*/
enum gft_logic_filter_type {
GFT_FILTER_TYPE /* flow FW is GFT-logic as well */,
RFS_FILTER_TYPE /* flow FW is A-RFS-logic */,
MAX_GFT_LOGIC_FILTER_TYPE
};
/*
@ -1166,7 +1158,7 @@ struct rx_create_openflow_action_data {
*/
struct rx_queue_start_ramrod_data {
__le16 rx_queue_id /* ID of RX queue */;
__le16 num_of_pbl_pages /* Num of pages in CQE PBL */;
__le16 num_of_pbl_pages /* Number of pages in CQE PBL */;
__le16 bd_max_bytes /* maximal bytes that can be places on the bd */;
__le16 sb_id /* Status block ID */;
u8 sb_index /* index of the protocol index */;
@ -1254,26 +1246,34 @@ struct rx_udp_filter_data {
/*
* Ramrod to add filter - filter is packet headr of type of packet wished to
* pass certin FW flow
* add or delete GFT filter - filter is packet header of type of packet wished
* to pass certain FW flow
*/
struct rx_update_gft_filter_data {
/* Pointer to Packet Header That Defines GFT Filter */
struct regpair pkt_hdr_addr;
__le16 pkt_hdr_length /* Packet Header Length */;
/* If is_rfs flag is set: Queue Id to associate filter with else: action icid */
__le16 rx_qid_or_action_icid;
/* Field is used if is_rfs flag is set: vport Id of which to associate filter
* with
/* Action icid. Valid if action_icid_valid flag set. */
__le16 action_icid;
__le16 rx_qid /* RX queue ID. Valid if rx_qid_valid set. */;
__le16 flow_id /* RX flow ID. Valid if flow_id_valid set. */;
u8 vport_id /* RX vport Id. */;
/* If set, action_icid will used for GFT filter update. */
u8 action_icid_valid;
/* If set, rx_qid will used for traffic steering, in additional to vport_id.
* flow_id_valid must be cleared. If cleared, queue ID will selected by RSS.
*/
u8 vport_id;
/* Use enum to set type of flow using gft HW logic blocks */
u8 filter_type;
u8 rx_qid_valid;
/* If set, flow_id will reported by CQE, rx_qid_valid must be cleared. If
* cleared, flow_id 0 will reported by CQE.
*/
u8 flow_id_valid;
u8 filter_action /* Use to set type of action on filter */;
/* 0 - dont assert in case of error. Just return an error code. 1 - assert in
* case of error.
*/
u8 assert_on_error;
u8 reserved[2];
};
@ -1344,6 +1344,17 @@ struct tx_queue_stop_ramrod_data {
};
/*
* Ramrod data for tx queue update ramrod
*/
struct tx_queue_update_ramrod_data {
__le16 update_qm_pq_id_flg /* Flag to Update QM PQ ID */;
__le16 qm_pq_id /* Updated QM PQ ID */;
__le32 reserved0;
struct regpair reserved1[5];
};
/*
* Ramrod data for vport update ramrod
@ -1388,9 +1399,9 @@ struct vport_start_ramrod_data {
/* If set, ETH header padding will not inserted. placement_offset will be zero.
*/
u8 zero_placement_offset;
/* If set, Contorl frames will be filtered according to MAC check. */
/* If set, control frames will be filtered according to MAC check. */
u8 ctl_frame_mac_check_en;
/* If set, Contorl frames will be filtered according to ethtype check. */
/* If set, control frames will be filtered according to ethtype check. */
u8 ctl_frame_ethtype_check_en;
u8 reserved[5];
};
@ -1456,9 +1467,9 @@ struct vport_update_ramrod_data_cmn {
* updated
*/
u8 update_ctl_frame_checks_en_flg;
/* If set, Contorl frames will be filtered according to MAC check. */
/* If set, control frames will be filtered according to MAC check. */
u8 ctl_frame_mac_check_en;
/* If set, Contorl frames will be filtered according to ethtype check. */
/* If set, control frames will be filtered according to ethtype check. */
u8 ctl_frame_ethtype_check_en;
u8 reserved[15];
};

451
drivers/net/qede/base/ecore_init_fw_funcs.c
View File

@ -20,12 +20,12 @@
#define CDU_VALIDATION_DEFAULT_CFG 61
static u16 con_region_offsets[3][E4_NUM_OF_CONNECTION_TYPES] = {
static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES_E4] = {
{ 400, 336, 352, 304, 304, 384, 416, 352}, /* region 3 offsets */
{ 528, 496, 416, 448, 448, 512, 544, 480}, /* region 4 offsets */
{ 608, 544, 496, 512, 576, 592, 624, 560} /* region 5 offsets */
};
static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = {
static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES_E4] = {
{ 240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
};
@ -43,6 +43,9 @@ static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = {
/* Other PQ constants */
#define QM_OTHER_PQS_PER_PF 4
/* VOQ constants */
#define QM_E5_NUM_EXT_VOQ (MAX_NUM_PORTS_E5 * NUM_OF_TCS)
/* WFQ constants: */
/* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
@ -52,37 +55,52 @@ static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = {
#define QM_WFQ_VP_PQ_VOQ_SHIFT 0
/* Bit of PF in WFQ VP PQ map */
#define QM_WFQ_VP_PQ_PF_SHIFT 5
#define QM_WFQ_VP_PQ_PF_E4_SHIFT 5
#define QM_WFQ_VP_PQ_PF_E5_SHIFT 6
/* 0x9000 = 4*9*1024 */
#define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
/* 0.7 * upper bound (62500000) */
#define QM_WFQ_MAX_INC_VAL 43750000
/* Max WFQ increment value is 0.7 * upper bound */
#define QM_WFQ_MAX_INC_VAL ((QM_WFQ_UPPER_BOUND * 7) / 10)
/* Number of VOQs in E5 QmWfqCrd register */
#define QM_WFQ_CRD_E5_NUM_VOQS 16
/* RL constants: */
/* Upper bound is set to 10 * burst size of 1ms in 50Gbps */
#define QM_RL_UPPER_BOUND 62500000
/* Period in us */
#define QM_RL_PERIOD 5
/* Period in 25MHz cycles */
#define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
/* 0.7 * upper bound (62500000) */
#define QM_RL_MAX_INC_VAL 43750000
/* RL increment value - rate is specified in mbps. the factor of 1.01 was
* added after seeing only 99% factor reached in a 25Gbps port with DPDK RFC
* 2544 test. In this scenario the PF RL was reducing the line rate to 99%
* although the credit increment value was the correct one and FW calculated
* correct packet sizes. The reason for the inaccuracy of the RL is unknown at
* this point.
*/
#define QM_RL_INC_VAL(rate) OSAL_MAX_T(u32, (u32)(((rate ? rate : 1000000) * \
QM_RL_PERIOD * 101) / (8 * 100)), 1)
* added after seeing only 99% factor reached in a 25Gbps port with DPDK RFC
* 2544 test. In this scenario the PF RL was reducing the line rate to 99%
* although the credit increment value was the correct one and FW calculated
* correct packet sizes. The reason for the inaccuracy of the RL is unknown at
* this point.
*/
#define QM_RL_INC_VAL(rate) \
OSAL_MAX_T(u32, (u32)(((rate ? rate : 100000) * QM_RL_PERIOD * 101) / \
(8 * 100)), 1)
/* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */
#define QM_PF_RL_UPPER_BOUND 62500000
/* Max PF RL increment value is 0.7 * upper bound */
#define QM_PF_RL_MAX_INC_VAL ((QM_PF_RL_UPPER_BOUND * 7) / 10)
/* Vport RL Upper bound, link speed is in Mpbs */
#define QM_VP_RL_UPPER_BOUND(speed) \
((u32)OSAL_MAX_T(u32, QM_RL_INC_VAL(speed), 9700 + 1000))
/* Max Vport RL increment value is the Vport RL upper bound */
#define QM_VP_RL_MAX_INC_VAL(speed) QM_VP_RL_UPPER_BOUND(speed)
/* Vport RL credit threshold in case of QM bypass */
#define QM_VP_RL_BYPASS_THRESH_SPEED (QM_VP_RL_UPPER_BOUND(10000) - 1)
/* AFullOprtnstcCrdMask constants */
#define QM_OPPOR_LINE_VOQ_DEF 1
@ -94,13 +112,17 @@ static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = {
/* Pure LB CmdQ lines (+spare) */
#define PBF_CMDQ_PURE_LB_LINES 150
#define PBF_CMDQ_LINES_RT_OFFSET(voq) \
(PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + voq * \
#define PBF_CMDQ_LINES_E5_RSVD_RATIO 8
#define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \
(PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \
ext_voq * \
(PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \
PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
#define PBF_BTB_GUARANTEED_RT_OFFSET(voq) \
(PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + voq * \
#define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \
(PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \
ext_voq * \
(PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \
PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
@ -140,25 +162,58 @@ static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = {
#define QM_CMD_SET_FIELD(var, cmd, field, value) \
SET_FIELD(var[cmd##_##field##_OFFSET], cmd##_##field, value)
/* QM: VOQ macros */
#define PHYS_VOQ(port, tc, max_phys_tcs_per_port) \
((port) * (max_phys_tcs_per_port) + (tc))
#define LB_VOQ(port) (MAX_PHYS_VOQS + (port))
#define VOQ(port, tc, max_phys_tcs_per_port) \
((tc) < LB_TC ? PHYS_VOQ(port, tc, max_phys_tcs_per_port) : \
LB_VOQ(port))
#define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, rl_valid, \
vp_pq_id, rl_id, ext_voq, wrr) \
do { \
OSAL_MEMSET(&map, 0, sizeof(map)); \
SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_PQ_VALID, 1); \
SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_VALID, rl_valid); \
SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VP_PQ_ID, vp_pq_id); \
SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_ID, rl_id); \
SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VOQ, ext_voq); \
SET_FIELD(map.reg, \
QM_RF_PQ_MAP_##chip##_WRR_WEIGHT_GROUP, wrr); \
STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id, \
*((u32 *)&map)); \
} while (0)
#define WRITE_PQ_INFO_TO_RAM 1
#define PQ_INFO_ELEMENT(vp, pf, tc, port, rl_valid, rl) \
(((vp) << 0) | ((pf) << 12) | ((tc) << 16) | \
((port) << 20) | ((rl_valid) << 22) | ((rl) << 24))
#define PQ_INFO_RAM_GRC_ADDRESS(pq_id) \
(XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 21768 + (pq_id) * 4)
/******************** INTERNAL IMPLEMENTATION *********************/
/* Returns the external VOQ number */
static u8 ecore_get_ext_voq(struct ecore_hwfn *p_hwfn,
u8 port_id,
u8 tc,
u8 max_phys_tcs_per_port)
{
if (tc == PURE_LB_TC)
return NUM_OF_PHYS_TCS * (MAX_NUM_PORTS_BB) + port_id;
else
return port_id * (max_phys_tcs_per_port) + tc;
}
/* Prepare PF RL enable/disable runtime init values */
static void ecore_enable_pf_rl(struct ecore_hwfn *p_hwfn, bool pf_rl_en)
{
STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
if (pf_rl_en) {
u8 num_ext_voqs = MAX_NUM_VOQS_E4;
u64 voq_bit_mask = ((u64)1 << num_ext_voqs) - 1;
/* Enable RLs for all VOQs */
STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET,
(1 << MAX_NUM_VOQS) - 1);
(u32)voq_bit_mask);
#ifdef QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET
if (num_ext_voqs >= 32)
STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET,
(u32)(voq_bit_mask >> 32));
#endif
/* Write RL period */
STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIOD_RT_OFFSET,
@ -169,7 +224,7 @@ static void ecore_enable_pf_rl(struct ecore_hwfn *p_hwfn, bool pf_rl_en)
/* Set credit threshold for QM bypass flow */
if (QM_BYPASS_EN)
STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET,
QM_RL_UPPER_BOUND);
QM_PF_RL_UPPER_BOUND);
}
}
@ -200,7 +255,7 @@ static void ecore_enable_vport_rl(struct ecore_hwfn *p_hwfn, bool vport_rl_en)
if (QM_BYPASS_EN)
STORE_RT_REG(p_hwfn,
QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET,
QM_RL_UPPER_BOUND);
QM_VP_RL_BYPASS_THRESH_SPEED);
}
}
@ -220,17 +275,19 @@ static void ecore_enable_vport_wfq(struct ecore_hwfn *p_hwfn, bool vport_wfq_en)
* the specified VOQ
*/
static void ecore_cmdq_lines_voq_rt_init(struct ecore_hwfn *p_hwfn,
u8 voq, u16 cmdq_lines)
u8 ext_voq,
u16 cmdq_lines)
{
u32 qm_line_crd;
qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq),
OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq),
(u32)cmdq_lines);
STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + voq, qm_line_crd);
STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + voq,
qm_line_crd);
STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + ext_voq,
qm_line_crd);
STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + ext_voq,
qm_line_crd);
}
/* Prepare runtime init values to allocate PBF command queue lines. */
@ -240,11 +297,12 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
struct init_qm_port_params
port_params[MAX_NUM_PORTS])
{
u8 tc, voq, port_id, num_tcs_in_port;
u8 tc, ext_voq, port_id, num_tcs_in_port;
u8 num_ext_voqs = MAX_NUM_VOQS_E4;
/* Clear PBF lines for all VOQs */
for (voq = 0; voq < MAX_NUM_VOQS; voq++)
STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0);
/* Clear PBF lines of all VOQs */
for (ext_voq = 0; ext_voq < num_ext_voqs; ext_voq++)
STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq), 0);
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
u16 phys_lines, phys_lines_per_tc;
@ -252,31 +310,35 @@ static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
if (!port_params[port_id].active)
continue;
/* Find #lines to divide between the active physical TCs */
phys_lines = port_params[port_id].num_pbf_cmd_lines -
PBF_CMDQ_PURE_LB_LINES;
/* Find number of command queue lines to divide between the
* active physical TCs. In E5, 1/8 of the lines are reserved.
* the lines for pure LB TC are subtracted.
*/
phys_lines = port_params[port_id].num_pbf_cmd_lines;
phys_lines -= PBF_CMDQ_PURE_LB_LINES;
/* Find #lines per active physical TC */
num_tcs_in_port = 0;
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
for (tc = 0; tc < max_phys_tcs_per_port; tc++)
if (((port_params[port_id].active_phys_tcs >> tc) &
0x1) == 1)
num_tcs_in_port++;
phys_lines_per_tc = phys_lines / num_tcs_in_port;
/* Init registers per active TC */
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
for (tc = 0; tc < max_phys_tcs_per_port; tc++) {
ext_voq = ecore_get_ext_voq(p_hwfn, port_id, tc,
max_phys_tcs_per_port);
if (((port_params[port_id].active_phys_tcs >> tc) &
0x1) == 1) {
voq = PHYS_VOQ(port_id, tc,
max_phys_tcs_per_port);
ecore_cmdq_lines_voq_rt_init(p_hwfn, voq,
0x1) == 1)
ecore_cmdq_lines_voq_rt_init(p_hwfn, ext_voq,
phys_lines_per_tc);
}
}
/* Init registers for pure LB TC */
ecore_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id),
ext_voq = ecore_get_ext_voq(p_hwfn, port_id, PURE_LB_TC,
max_phys_tcs_per_port);
ecore_cmdq_lines_voq_rt_init(p_hwfn, ext_voq,
PBF_CMDQ_PURE_LB_LINES);
}
}
@ -308,7 +370,7 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
port_params[MAX_NUM_PORTS])
{
u32 usable_blocks, pure_lb_blocks, phys_blocks;
u8 tc, voq, port_id, num_tcs_in_port;
u8 tc, ext_voq, port_id, num_tcs_in_port;
for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
if (!port_params[port_id].active)
@ -339,18 +401,19 @@ static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
/* Init physical TCs */
for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
if (((port_params[port_id].active_phys_tcs >> tc) &
0x1) == 1) {
voq = PHYS_VOQ(port_id, tc,
max_phys_tcs_per_port);
0x1) == 1) {
ext_voq = ecore_get_ext_voq(p_hwfn, port_id, tc,
max_phys_tcs_per_port);
STORE_RT_REG(p_hwfn,
PBF_BTB_GUARANTEED_RT_OFFSET(voq),
phys_blocks);
PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq),
phys_blocks);
}
}
/* Init pure LB TC */
STORE_RT_REG(p_hwfn,
PBF_BTB_GUARANTEED_RT_OFFSET(LB_VOQ(port_id)),
ext_voq = ecore_get_ext_voq(p_hwfn, port_id, PURE_LB_TC,
max_phys_tcs_per_port);
STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq),
pure_lb_blocks);
}
}
@ -400,12 +463,12 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
/* Go over all Tx PQs */
for (i = 0, pq_id = start_pq; i < num_pqs; i++, pq_id++) {
u32 max_qm_global_rls = MAX_QM_GLOBAL_RLS;
struct qm_rf_pq_map tx_pq_map;
u8 ext_voq, vport_id_in_pf;
bool is_vf_pq, rl_valid;
u8 voq, vport_id_in_pf;
u16 first_tx_pq_id;
voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
ext_voq = ecore_get_ext_voq(p_hwfn, port_id, pq_params[i].tc_id,
max_phys_tcs_per_port);
is_vf_pq = (i >= num_pf_pqs);
rl_valid = pq_params[i].rl_valid && pq_params[i].vport_id <
max_qm_global_rls;
@ -415,16 +478,17 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
first_tx_pq_id =
vport_params[vport_id_in_pf].first_tx_pq_id[pq_params[i].tc_id];
if (first_tx_pq_id == QM_INVALID_PQ_ID) {
u32 map_val = (ext_voq << QM_WFQ_VP_PQ_VOQ_SHIFT) |
(pf_id << (QM_WFQ_VP_PQ_PF_E4_SHIFT));
/* Create new VP PQ */
vport_params[vport_id_in_pf].
first_tx_pq_id[pq_params[i].tc_id] = pq_id;
first_tx_pq_id = pq_id;
/* Map VP PQ to VOQ and PF */
STORE_RT_REG(p_hwfn,
QM_REG_WFQVPMAP_RT_OFFSET + first_tx_pq_id,
(voq << QM_WFQ_VP_PQ_VOQ_SHIFT) | (pf_id <<
QM_WFQ_VP_PQ_PF_SHIFT));
STORE_RT_REG(p_hwfn, QM_REG_WFQVPMAP_RT_OFFSET +
first_tx_pq_id, map_val);
}
/* Check RL ID */
@ -433,26 +497,29 @@ static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
DP_NOTICE(p_hwfn, true,
"Invalid VPORT ID for rate limiter config\n");
/* Fill PQ map entry */
OSAL_MEMSET(&tx_pq_map, 0, sizeof(tx_pq_map));
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_VALID,
rl_valid ? 1 : 0);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID,
rl_valid ? pq_params[i].vport_id : 0);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq);
SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP,
pq_params[i].wrr_group);
/* Write PQ map entry to CAM */
STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id,
*((u32 *)&tx_pq_map));
/* Prepare PQ map entry */
struct qm_rf_pq_map_e4 tx_pq_map;
QM_INIT_TX_PQ_MAP(p_hwfn, tx_pq_map, E4, pq_id, rl_valid ?
1 : 0,
first_tx_pq_id, rl_valid ?
pq_params[i].vport_id : 0,
ext_voq, pq_params[i].wrr_group);
/* Set base address */
STORE_RT_REG(p_hwfn, QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id,
mem_addr_4kb);
/* Write PQ info to RAM */
if (WRITE_PQ_INFO_TO_RAM != 0) {
u32 pq_info = 0;
pq_info = PQ_INFO_ELEMENT(first_tx_pq_id, pf_id,
pq_params[i].tc_id, port_id,
rl_valid ? 1 : 0, rl_valid ?
pq_params[i].vport_id : 0);
ecore_wr(p_hwfn, p_ptt, PQ_INFO_RAM_GRC_ADDRESS(pq_id),
pq_info);
}
/* If VF PQ, add indication to PQ VF mask */
if (is_vf_pq) {
tx_pq_vf_mask[pq_id / QM_PF_QUEUE_GROUP_SIZE] |=
@ -517,13 +584,9 @@ static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn,
struct init_qm_pq_params *pq_params)
{
u32 inc_val, crd_reg_offset;
u8 voq;
u8 ext_voq;
u16 i;
crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ? QM_REG_WFQPFCRD_RT_OFFSET :
QM_REG_WFQPFCRD_MSB_RT_OFFSET) +
(pf_id % MAX_NUM_PFS_BB);
inc_val = QM_WFQ_INC_VAL(pf_wfq);
if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, true,
@ -532,14 +595,21 @@ static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn,
}
for (i = 0; i < num_tx_pqs; i++) {
voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
OVERWRITE_RT_REG(p_hwfn, crd_reg_offset + voq * MAX_NUM_PFS_BB,
ext_voq = ecore_get_ext_voq(p_hwfn, port_id, pq_params[i].tc_id,
max_phys_tcs_per_port);
crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ?
QM_REG_WFQPFCRD_RT_OFFSET :
QM_REG_WFQPFCRD_MSB_RT_OFFSET) +
ext_voq * MAX_NUM_PFS_BB +
(pf_id % MAX_NUM_PFS_BB);
OVERWRITE_RT_REG(p_hwfn, crd_reg_offset,
(u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id,
QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id,
inc_val);
}
STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id,
QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val);
return 0;
}
@ -551,7 +621,7 @@ static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
u32 inc_val;
inc_val = QM_RL_INC_VAL(pf_rl);
if (inc_val > QM_RL_MAX_INC_VAL) {
if (inc_val > QM_PF_RL_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, true,
"Invalid PF rate limit configuration\n");
return -1;
@ -560,7 +630,7 @@ static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn, u8 pf_id, u32 pf_rl)
STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id,
(u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id,
QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
QM_PF_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
return 0;
@ -611,6 +681,7 @@ static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,
static int ecore_vport_rl_rt_init(struct ecore_hwfn *p_hwfn,
u8 start_vport,
u8 num_vports,
u32 link_speed,
struct init_qm_vport_params *vport_params)
{
u8 i, vport_id;
@ -624,8 +695,9 @@ static int ecore_vport_rl_rt_init(struct ecore_hwfn *p_hwfn,
/* Go over all PF VPORTs */
for (i = 0, vport_id = start_vport; i < num_vports; i++, vport_id++) {
u32 inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl);
if (inc_val > QM_RL_MAX_INC_VAL) {
inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl ?
vport_params[i].vport_rl : link_speed);
if (inc_val > QM_VP_RL_MAX_INC_VAL(link_speed)) {
DP_NOTICE(p_hwfn, true,
"Invalid VPORT rate-limit configuration\n");
return -1;
@ -635,7 +707,8 @@ static int ecore_vport_rl_rt_init(struct ecore_hwfn *p_hwfn,
(u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn,
QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + vport_id,
QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
QM_VP_RL_UPPER_BOUND(link_speed) |
(u32)QM_RL_CRD_REG_SIGN_BIT);
STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id,
inc_val);
}
@ -666,7 +739,9 @@ static bool ecore_poll_on_qm_cmd_ready(struct ecore_hwfn *p_hwfn,
static bool ecore_send_qm_cmd(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u32 cmd_addr, u32 cmd_data_lsb, u32 cmd_data_msb)
u32 cmd_addr,
u32 cmd_data_lsb,
u32 cmd_data_msb)
{
if (!ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt))
return false;
@ -684,10 +759,10 @@ static bool ecore_send_qm_cmd(struct ecore_hwfn *p_hwfn,
/******************** INTERFACE IMPLEMENTATION *********************/
u32 ecore_qm_pf_mem_size(u32 num_pf_cids,
u32 num_vf_cids,
u32 num_tids,
u16 num_pf_pqs,
u16 num_vf_pqs)
u32 num_vf_cids,
u32 num_tids,
u16 num_pf_pqs,
u16 num_vf_pqs)
{
return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs +
QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs +
@ -758,6 +833,7 @@ int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
u8 num_vports,
u16 pf_wfq,
u32 pf_rl,
u32 link_speed,
struct init_qm_pq_params *pq_params,
struct init_qm_vport_params *vport_params)
{
@ -800,7 +876,7 @@ int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
/* Set VPORT RL */
if (ecore_vport_rl_rt_init
(p_hwfn, start_vport, num_vports, vport_params))
(p_hwfn, start_vport, num_vports, link_speed, vport_params))
return -1;
return 0;
@ -829,7 +905,7 @@ int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,
u32 inc_val;
inc_val = QM_RL_INC_VAL(pf_rl);
if (inc_val > QM_RL_MAX_INC_VAL) {
if (inc_val > QM_PF_RL_MAX_INC_VAL) {
DP_NOTICE(p_hwfn, true,
"Invalid PF rate limit configuration\n");
return -1;
@ -869,7 +945,9 @@ int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
}
int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt, u8 vport_id, u32 vport_rl)
struct ecore_ptt *p_ptt, u8 vport_id,
u32 vport_rl,
u32 link_speed)
{
u32 inc_val, max_qm_global_rls = MAX_QM_GLOBAL_RLS;
@ -879,8 +957,8 @@ int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
return -1;
}
inc_val = QM_RL_INC_VAL(vport_rl);
if (inc_val > QM_RL_MAX_INC_VAL) {
inc_val = QM_RL_INC_VAL(vport_rl ? vport_rl : link_speed);
if (inc_val > QM_VP_RL_MAX_INC_VAL(link_speed)) {
DP_NOTICE(p_hwfn, true,
"Invalid VPORT rate-limit configuration\n");
return -1;
@ -1479,35 +1557,23 @@ void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
#define RAM_LINE_SIZE sizeof(u64)
#define REG_SIZE sizeof(u32)
void ecore_set_rfs_mode_disable(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 pf_id)
void ecore_gft_disable(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 pf_id)
{
union gft_cam_line_union cam_line;
struct gft_ram_line ram_line;
u32 i, *ram_line_ptr;
ram_line_ptr = (u32 *)&ram_line;
/* Stop using gft logic, disable gft search */
/* disable gft search for PF */
ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0);
ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, 0x0);
/* Clean ram & cam for next rfs/gft session*/
/* Clean ram & cam for next gft session*/
/* Zero camline */
OSAL_MEMSET(&cam_line, 0, sizeof(cam_line));
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
cam_line.cam_line_mapped.camline);
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 0);
/* Zero ramline */
OSAL_MEMSET(&ram_line, 0, sizeof(ram_line));
/* Each iteration write to reg */
for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM +
RAM_LINE_SIZE * pf_id +
i * REG_SIZE, *(ram_line_ptr + i));
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM +
RAM_LINE_SIZE * pf_id, 0);
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM +
RAM_LINE_SIZE * pf_id + REG_SIZE, 0);
}
@ -1525,115 +1591,110 @@ void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn,
ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
}
void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn,
void ecore_gft_config(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 pf_id,
bool tcp,
bool udp,
bool ipv4,
bool ipv6)
bool ipv6,
enum gft_profile_type profile_type)
{
u32 rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
union gft_cam_line_union camLine;
struct gft_ram_line ramLine;
u32 *ramLinePointer = (u32 *)&ramLine;
int i;
u32 reg_val, cam_line, ram_line_lo, ram_line_hi;
if (!ipv6 && !ipv4)
DP_NOTICE(p_hwfn, true,
"set_rfs_mode_enable: must accept at "
"least on of - ipv4 or ipv6");
DP_NOTICE(p_hwfn, true, "gft_config: must accept at least on of - ipv4 or ipv6'\n");
if (!tcp && !udp)
DP_NOTICE(p_hwfn, true,
"set_rfs_mode_enable: must accept at "
"least on of - udp or tcp");
DP_NOTICE(p_hwfn, true, "gft_config: must accept at least on of - udp or tcp\n");
if (profile_type >= MAX_GFT_PROFILE_TYPE)
DP_NOTICE(p_hwfn, true, "gft_config: unsupported gft_profile_type\n");
/* Set RFS event ID to be awakened i Tstorm By Prs */
rfs_cm_hdr_event_id |= T_ETH_PACKET_MATCH_RFS_EVENTID <<
PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
rfs_cm_hdr_event_id |= PARSER_ETH_CONN_CM_HDR <<
PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID <<
PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val);
/* Configure Registers for RFS mode */
/* Do not load context only cid in PRS on match. */
ecore_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0);
/* Enable gft search */
ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
ecore_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0); /* do not load
* context only cid
* in PRS on match
*/
camLine.cam_line_mapped.camline = 0;
/* Do not use tenant ID exist bit for gft search*/
ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TENANT_ID, 0);
/* Cam line is now valid!! */
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_VALID, 1);
/* Set Cam */
cam_line = 0;
SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_VALID, 1);
/* Filters are per PF!! */
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_PF_ID_MASK,
SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID_MASK,
GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK);
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
if (!(tcp && udp)) {
SET_FIELD(camLine.cam_line_mapped.camline,
SET_FIELD(cam_line,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK);
if (tcp)
SET_FIELD(camLine.cam_line_mapped.camline,
SET_FIELD(cam_line,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
GFT_PROFILE_TCP_PROTOCOL);
else
SET_FIELD(camLine.cam_line_mapped.camline,
SET_FIELD(cam_line,
GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE,
GFT_PROFILE_UDP_PROTOCOL);
}
if (!(ipv4 && ipv6)) {
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
if (ipv4)
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_IP_VERSION,
SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION,
GFT_PROFILE_IPV4);
else
SET_FIELD(camLine.cam_line_mapped.camline,
GFT_CAM_LINE_MAPPED_IP_VERSION,
SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION,
GFT_PROFILE_IPV6);
}
/* Write characteristics to cam */
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id,
camLine.cam_line_mapped.camline);
camLine.cam_line_mapped.camline =
ecore_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
cam_line);
cam_line = ecore_rd(p_hwfn, p_ptt,
PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id);
/* Write line to RAM - compare to filter 4 tuple */
ramLine.lo = 0;
ramLine.hi = 0;
SET_FIELD(ramLine.hi, GFT_RAM_LINE_DST_IP, 1);
SET_FIELD(ramLine.hi, GFT_RAM_LINE_SRC_IP, 1);
SET_FIELD(ramLine.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
SET_FIELD(ramLine.lo, GFT_RAM_LINE_ETHERTYPE, 1);
SET_FIELD(ramLine.lo, GFT_RAM_LINE_SRC_PORT, 1);
SET_FIELD(ramLine.lo, GFT_RAM_LINE_DST_PORT, 1);
ram_line_lo = 0;
ram_line_hi = 0;
/* Each iteration write to reg */
for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM +
RAM_LINE_SIZE * pf_id +
i * REG_SIZE, *(ramLinePointer + i));
if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) {
SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1);
SET_FIELD(ram_line_hi, GFT_RAM_LINE_SRC_IP, 1);
SET_FIELD(ram_line_hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);
SET_FIELD(ram_line_lo, GFT_RAM_LINE_SRC_PORT, 1);
SET_FIELD(ram_line_lo, GFT_RAM_LINE_DST_PORT, 1);
} else if (profile_type == GFT_PROFILE_TYPE_L4_DST_PORT) {
SET_FIELD(ram_line_hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);
SET_FIELD(ram_line_lo, GFT_RAM_LINE_DST_PORT, 1);
} else if (profile_type == GFT_PROFILE_TYPE_IP_DST_PORT) {
SET_FIELD(ram_line_hi, GFT_RAM_LINE_DST_IP, 1);
SET_FIELD(ram_line_lo, GFT_RAM_LINE_ETHERTYPE, 1);
}
ecore_wr(p_hwfn, p_ptt,
PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id,
ram_line_lo);
ecore_wr(p_hwfn, p_ptt,
PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id +
REG_SIZE, ram_line_hi);
/* Set default profile so that no filter match will happen */
ramLine.lo = 0xffffffff;
ramLine.hi = 0x3ff;
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
PRS_GFT_CAM_LINES_NO_MATCH, 0xffffffff);
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE *
PRS_GFT_CAM_LINES_NO_MATCH + REG_SIZE, 0x3ff);
for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM +
RAM_LINE_SIZE * PRS_GFT_CAM_LINES_NO_MATCH +
i * REG_SIZE, *(ramLinePointer + i));
/* Enable gft search */
ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
}
/* Configure VF zone size mode */

56
drivers/net/qede/base/ecore_init_fw_funcs.h
View File

@ -27,10 +27,10 @@ struct init_qm_pq_params;
* @return The required host memory size in 4KB units.
*/
u32 ecore_qm_pf_mem_size(u32 num_pf_cids,
u32 num_vf_cids,
u32 num_tids,
u16 num_pf_pqs,
u16 num_vf_pqs);
u32 num_vf_cids,
u32 num_tids,
u16 num_pf_pqs,
u16 num_vf_pqs);
/**
* @brief ecore_qm_common_rt_init - Prepare QM runtime init values for engine
@ -77,6 +77,7 @@ int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
* be 0. otherwise, the weight must be non-zero.
* @param pf_rl - rate limit in Mb/sec units. a value of 0 means don't
* configure. ignored if PF RL is globally disabled.
* @param link_speed - link speed in Mbps.
* @param pq_params - array of size (num_pf_pqs+num_vf_pqs) with parameters for
* each Tx PQ associated with the specified PF.
* @param vport_params - array of size num_vports with parameters for each
@ -99,6 +100,7 @@ int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
u8 num_vports,
u16 pf_wfq,
u32 pf_rl,
u32 link_speed,
struct init_qm_pq_params *pq_params,
struct init_qm_vport_params *vport_params);
@ -153,17 +155,19 @@ int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
* @brief ecore_init_vport_rl - Initializes the rate limit of the specified
* VPORT.
*
* @param p_hwfn - HW device data
* @param p_ptt - ptt window used for writing the registers
* @param vport_id - VPORT ID
* @param vport_rl - rate limit in Mb/sec units
* @param p_hwfn - HW device data
* @param p_ptt - ptt window used for writing the registers
* @param vport_id - VPORT ID
* @param vport_rl - rate limit in Mb/sec units
* @param link_speed - link speed in Mbps.
*
* @return 0 on success, -1 on error.
*/
int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u8 vport_id,
u32 vport_rl);
u32 vport_rl,
u32 link_speed);
/**
* @brief ecore_send_qm_stop_cmd Sends a stop command to the QM
@ -264,7 +268,8 @@ void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn,
* @param p_hwfn - HW device data
* @param ethType - etherType to configure
*/
void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn, u32 ethType);
void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
u32 ethType);
#endif /* UNUSED_HSI_FUNC */
/**
@ -333,33 +338,35 @@ void ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt);
/**
* @brief ecore_set_rfs_mode_disable - Disable and configure HW for RFS
* @brief ecore_gft_disable - Disable and GFT
*
* @param p_hwfn - HW device data
* @param p_ptt - ptt window used for writing the registers.
* @param pf_id - pf on which to disable RFS.
* @param pf_id - pf on which to disable GFT.
*/
void ecore_set_rfs_mode_disable(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 pf_id);
void ecore_gft_disable(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 pf_id);
/**
* @brief ecore_set_rfs_mode_enable - enable and configure HW for RFS
* @brief ecore_gft_config - Enable and configure HW for GFT
*
* @param p_ptt - ptt window used for writing the registers.
* @param pf_id - pf on which to enable RFS.
* @param pf_id - pf on which to enable GFT.
* @param tcp - set profile tcp packets.
* @param udp - set profile udp packet.
* @param ipv4 - set profile ipv4 packet.
* @param ipv6 - set profile ipv6 packet.
* @param profile_type - define packet same fields. Use enum gft_profile_type.
*/
void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn,
void ecore_gft_config(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
u16 pf_id,
bool tcp,
bool udp,
bool ipv4,
bool ipv6);
bool ipv6,
enum gft_profile_type profile_type);
#endif /* UNUSED_HSI_FUNC */
/**
@ -413,8 +420,10 @@ void ecore_enable_context_validation(struct ecore_hwfn *p_hwfn,
* @param ctx_type - context type.
* @param cid - context cid.
*/
void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size,
u8 ctx_type, u32 cid);
void ecore_calc_session_ctx_validation(void *p_ctx_mem,
u16 ctx_size,
u8 ctx_type,
u32 cid);
/**
* @brief ecore_calc_task_ctx_validation - Calcualte validation byte for task
@ -425,8 +434,11 @@ void ecore_calc_session_ctx_validation(void *p_ctx_mem, u16 ctx_size,
* @param ctx_type - context type.
* @param tid - context tid.
*/
void ecore_calc_task_ctx_validation(void *p_ctx_mem, u16 ctx_size, u8 ctx_type,
void ecore_calc_task_ctx_validation(void *p_ctx_mem,
u16 ctx_size,
u8 ctx_type,
u32 tid);
/**
* @brief ecore_memset_session_ctx - Memset session context to 0 while
* preserving validation bytes.

9
drivers/net/qede/base/ecore_int.c
View File

@ -30,7 +30,7 @@ struct ecore_pi_info {
struct ecore_sb_sp_info {
struct ecore_sb_info sb_info;
/* per protocol index data */
struct ecore_pi_info pi_info_arr[PIS_PER_SB];
struct ecore_pi_info pi_info_arr[PIS_PER_SB_E4];
};
enum ecore_attention_type {
@ -1492,7 +1492,7 @@ static void _ecore_int_cau_conf_pi(struct ecore_hwfn *p_hwfn,
if (IS_VF(p_hwfn->p_dev))
return;/* @@@TBD MichalK- VF CAU... */
sb_offset = igu_sb_id * PIS_PER_SB;
sb_offset = igu_sb_id * PIS_PER_SB_E4;
OSAL_MEMSET(&pi_entry, 0, sizeof(struct cau_pi_entry));
SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
@ -2677,10 +2677,11 @@ enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
p_info->igu_cons = ecore_rd(p_hwfn, p_ptt,
IGU_REG_CONSUMER_MEM + sbid * 4);
for (i = 0; i < PIS_PER_SB; i++)
for (i = 0; i < PIS_PER_SB_E4; i++)
p_info->pi[i] = (u16)ecore_rd(p_hwfn, p_ptt,
CAU_REG_PI_MEMORY +
sbid * 4 * PIS_PER_SB + i * 4);
sbid * 4 * PIS_PER_SB_E4 +
i * 4);
return ECORE_SUCCESS;
}

2
drivers/net/qede/base/ecore_int.h
View File

@ -19,7 +19,7 @@
#define ECORE_SB_EVENT_MASK 0x0003
#define SB_ALIGNED_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(struct status_block, p_hwfn)
ALIGNED_TYPE_SIZE(struct status_block_e4, p_hwfn)
#define ECORE_SB_INVALID_IDX 0xffff

6
drivers/net/qede/base/ecore_int_api.h
View File

@ -26,7 +26,7 @@ enum ecore_int_mode {
#endif
struct ecore_sb_info {
struct status_block *sb_virt;
struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
u32 sb_ack; /* Last given ack */
u16 igu_sb_id;
@ -44,7 +44,7 @@ struct ecore_sb_info {
struct ecore_sb_info_dbg {
u32 igu_prod;
u32 igu_cons;
u16 pi[PIS_PER_SB];
u16 pi[PIS_PER_SB_E4];
};
struct ecore_sb_cnt_info {
@ -67,7 +67,7 @@ static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)
/* barrier(); status block is written to by the chip */
/* FIXME: need some sort of barrier. */
prod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) &
STATUS_BLOCK_PROD_INDEX_MASK;
STATUS_BLOCK_E4_PROD_INDEX_MASK;
if (sb_info->sb_ack != prod) {
sb_info->sb_ack = prod;
rc |= ECORE_SB_IDX;

4
drivers/net/qede/base/ecore_iov_api.h
View File

@ -714,7 +714,7 @@ ecore_iov_pf_configure_vf_queue_coalesce(struct ecore_hwfn *p_hwfn,
* @param p_hwfn
* @param rel_vf_id
*
* @return E4_MAX_NUM_VFS in case no further active VFs, otherwise index.
* @return MAX_NUM_VFS_E4 in case no further active VFs, otherwise index.
*/
u16 ecore_iov_get_next_active_vf(struct ecore_hwfn *p_hwfn, u16 rel_vf_id);
@ -724,7 +724,7 @@ void ecore_iov_bulletin_set_udp_ports(struct ecore_hwfn *p_hwfn, int vfid,
#define ecore_for_each_vf(_p_hwfn, _i) \
for (_i = ecore_iov_get_next_active_vf(_p_hwfn, 0); \
_i < E4_MAX_NUM_VFS; \
_i < MAX_NUM_VFS_E4; \
_i = ecore_iov_get_next_active_vf(_p_hwfn, _i + 1))
#endif

8
drivers/net/qede/base/ecore_iro.h
View File

@ -193,5 +193,13 @@
#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) (IRO[48].base + \
((roce_pf_id) * IRO[48].m1))
#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[48].size)
/* DCQCN Received Statistics */
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) (IRO[49].base + \
((roce_pf_id) * IRO[49].m1))
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[49].size)
/* DCQCN Sent Statistics */
#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) (IRO[50].base + \
((roce_pf_id) * IRO[50].m1))
#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[50].size)
#endif /* __IRO_H__ */

44
drivers/net/qede/base/ecore_iro_values.h
View File

@ -9,13 +9,13 @@
#ifndef __IRO_VALUES_H__
#define __IRO_VALUES_H__
static const struct iro iro_arr[49] = {
static const struct iro iro_arr[51] = {
/* YSTORM_FLOW_CONTROL_MODE_OFFSET */
{ 0x0, 0x0, 0x0, 0x0, 0x8},
/* TSTORM_PORT_STAT_OFFSET(port_id) */
{ 0x4cb0, 0x80, 0x0, 0x0, 0x80},
/* TSTORM_LL2_PORT_STAT_OFFSET(port_id) */
{ 0x6518, 0x20, 0x0, 0x0, 0x20},
{ 0x6508, 0x20, 0x0, 0x0, 0x20},
/* USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) */
{ 0xb00, 0x8, 0x0, 0x0, 0x4},
/* USTORM_FLR_FINAL_ACK_OFFSET(pf_id) */
@ -29,9 +29,9 @@ static const struct iro iro_arr[49] = {
/* XSTORM_INTEG_TEST_DATA_OFFSET */
{ 0x4c40, 0x0, 0x0, 0x0, 0x78},
/* YSTORM_INTEG_TEST_DATA_OFFSET */
{ 0x3df0, 0x0, 0x0, 0x0, 0x78},
{ 0x3e10, 0x0, 0x0, 0x0, 0x78},
/* PSTORM_INTEG_TEST_DATA_OFFSET */
{ 0x29b0, 0x0, 0x0, 0x0, 0x78},
{ 0x2b50, 0x0, 0x0, 0x0, 0x78},
/* TSTORM_INTEG_TEST_DATA_OFFSET */
{ 0x4c38, 0x0, 0x0, 0x0, 0x78},
/* MSTORM_INTEG_TEST_DATA_OFFSET */
@ -41,11 +41,11 @@ static const struct iro iro_arr[49] = {
/* TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) */
{ 0xa28, 0x8, 0x0, 0x0, 0x8},
/* CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */
{ 0x61f8, 0x10, 0x0, 0x0, 0x10},
{ 0x61e8, 0x10, 0x0, 0x0, 0x10},
/* CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) */
{ 0xbd20, 0x30, 0x0, 0x0, 0x30},
{ 0xb820, 0x30, 0x0, 0x0, 0x30},
/* CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) */
{ 0x95b8, 0x30, 0x0, 0x0, 0x30},
{ 0x96b8, 0x30, 0x0, 0x0, 0x30},
/* MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
{ 0x4b60, 0x80, 0x0, 0x0, 0x40},
/* MSTORM_ETH_PF_PRODS_OFFSET(queue_id) */
@ -59,11 +59,11 @@ static const struct iro iro_arr[49] = {
/* USTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
{ 0x8150, 0x40, 0x0, 0x0, 0x30},
/* USTORM_ETH_PF_STAT_OFFSET(pf_id) */
{ 0xec70, 0x60, 0x0, 0x0, 0x60},
{ 0xe770, 0x60, 0x0, 0x0, 0x60},
/* PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) */
{ 0x2b48, 0x80, 0x0, 0x0, 0x38},
{ 0x2ce8, 0x80, 0x0, 0x0, 0x38},
/* PSTORM_ETH_PF_STAT_OFFSET(pf_id) */
{ 0xf1b0, 0x78, 0x0, 0x0, 0x78},
{ 0xf2b0, 0x78, 0x0, 0x0, 0x78},
/* PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethType_id) */
{ 0x1f8, 0x4, 0x0, 0x0, 0x4},
/* TSTORM_ETH_PRS_INPUT_OFFSET */
@ -81,33 +81,37 @@ static const struct iro iro_arr[49] = {
/* TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) */
{ 0x0, 0x8, 0x0, 0x0, 0x8},
/* TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */
{ 0x200, 0x10, 0x8, 0x0, 0x8},
{ 0x200, 0x18, 0x8, 0x0, 0x8},
/* MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id,bdq_id) */
{ 0xb78, 0x10, 0x8, 0x0, 0x2},
{ 0xb78, 0x18, 0x8, 0x0, 0x2},
/* TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
{ 0xd9a8, 0x38, 0x0, 0x0, 0x24},
{ 0xd878, 0x50, 0x0, 0x0, 0x3c},
/* MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
{ 0x12988, 0x10, 0x0, 0x0, 0x8},
{ 0x12908, 0x18, 0x0, 0x0, 0x10},
/* USTORM_ISCSI_RX_STATS_OFFSET(pf_id) */
{ 0x11fa0, 0x38, 0x0, 0x0, 0x18},
{ 0x11aa8, 0x40, 0x0, 0x0, 0x18},
/* XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
{ 0xa8c0, 0x38, 0x0, 0x0, 0x10},
{ 0xa580, 0x50, 0x0, 0x0, 0x20},
/* YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
{ 0x86f8, 0x30, 0x0, 0x0, 0x18},
{ 0x86f8, 0x40, 0x0, 0x0, 0x28},
/* PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) */
{ 0x101f8, 0x10, 0x0, 0x0, 0x10},
{ 0x102f8, 0x18, 0x0, 0x0, 0x10},
/* TSTORM_FCOE_RX_STATS_OFFSET(pf_id) */
{ 0xde28, 0x48, 0x0, 0x0, 0x38},
/* PSTORM_FCOE_TX_STATS_OFFSET(pf_id) */
{ 0x10660, 0x20, 0x0, 0x0, 0x20},
{ 0x10760, 0x20, 0x0, 0x0, 0x20},
/* PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */
{ 0x2b80, 0x80, 0x0, 0x0, 0x10},
{ 0x2d20, 0x80, 0x0, 0x0, 0x10},
/* TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) */
{ 0x5020, 0x10, 0x0, 0x0, 0x10},
/* XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) */
{ 0xc9b0, 0x30, 0x0, 0x0, 0x10},
/* TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) */
{ 0xeec0, 0x10, 0x0, 0x0, 0x10},
/* YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) */
{ 0xa398, 0x10, 0x0, 0x0, 0x10},
/* PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) */
{ 0x13100, 0x8, 0x0, 0x0, 0x8},
};
#endif /* __IRO_VALUES_H__ */

25
drivers/net/qede/base/ecore_l2.c
View File

@ -2073,11 +2073,12 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
struct ecore_arfs_config_params *p_cfg_params)
{
if (p_cfg_params->arfs_enable) {
ecore_set_rfs_mode_enable(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
p_cfg_params->tcp,
p_cfg_params->udp,
p_cfg_params->ipv4,
p_cfg_params->ipv6);
ecore_gft_config(p_hwfn, p_ptt, p_hwfn->rel_pf_id,
p_cfg_params->tcp,
p_cfg_params->udp,
p_cfg_params->ipv4,
p_cfg_params->ipv6,
GFT_PROFILE_TYPE_4_TUPLE);
DP_VERBOSE(p_hwfn, ECORE_MSG_SP,
"tcp = %s, udp = %s, ipv4 = %s, ipv6 =%s\n",
p_cfg_params->tcp ? "Enable" : "Disable",
@ -2085,7 +2086,7 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
p_cfg_params->ipv4 ? "Enable" : "Disable",
p_cfg_params->ipv6 ? "Enable" : "Disable");
} else {
ecore_set_rfs_mode_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
ecore_gft_disable(p_hwfn, p_ptt, p_hwfn->rel_pf_id);
}
DP_VERBOSE(p_hwfn, ECORE_MSG_SP, "Configured ARFS mode : %s\n",
p_cfg_params->arfs_enable ? "Enable" : "Disable");
@ -2136,9 +2137,17 @@ ecore_configure_rfs_ntuple_filter(struct ecore_hwfn *p_hwfn,
DMA_REGPAIR_LE(p_ramrod->pkt_hdr_addr, p_addr);
p_ramrod->pkt_hdr_length = OSAL_CPU_TO_LE16(length);
p_ramrod->rx_qid_or_action_icid = OSAL_CPU_TO_LE16(abs_rx_q_id);
p_ramrod->action_icid_valid = 0;
p_ramrod->action_icid = 0;
p_ramrod->rx_qid_valid = 1;
p_ramrod->rx_qid = OSAL_CPU_TO_LE16(abs_rx_q_id);
p_ramrod->flow_id_valid = 0;
p_ramrod->flow_id = 0;
p_ramrod->vport_id = abs_vport_id;
p_ramrod->filter_type = RFS_FILTER_TYPE;
p_ramrod->filter_action = b_is_add ? GFT_ADD_FILTER
: GFT_DELETE_FILTER;

1
drivers/net/qede/base/ecore_proto_if.h
View File

@ -71,6 +71,7 @@ struct ecore_iscsi_pf_params {
u8 is_target;
u8 bdq_pbl_num_entries[2];
u8 disable_stats_collection;
};
enum ecore_rdma_protocol {

858
drivers/net/qede/base/ecore_rt_defs.h
View File

@ -28,424 +28,506 @@
#define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15
#define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16
#define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17
#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18
#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19
#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20
#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21
#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22
#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23
#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24
#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761
#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736
#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497
#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736
#define CAU_REG_PI_MEMORY_RT_OFFSET 2233
#define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET 18
#define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET 19
#define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET 20
#define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET 21
#define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET 22
#define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET 23
#define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET 24
#define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET 25
#define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET 26
#define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET 27
#define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET 28
#define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET 29
#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET 30
#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET 31
#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET 32
#define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET 33
#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET 34
#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET 35
#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET 36
#define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET 37
#define IGU_REG_PF_CONFIGURATION_RT_OFFSET 38
#define IGU_REG_VF_CONFIGURATION_RT_OFFSET 39
#define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 40
#define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 41
#define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 42
#define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 43
#define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 44
#define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 45
#define CAU_REG_SB_VAR_MEMORY_RT_SIZE 1024
#define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1069
#define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 1024
#define CAU_REG_PI_MEMORY_RT_OFFSET 2093
#define CAU_REG_PI_MEMORY_RT_SIZE 4416
#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649
#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650
#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651
#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652
#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653
#define PRS_REG_SEARCH_TCP_RT_OFFSET 6654
#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655
#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656
#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657
#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658
#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659
#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660
#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661
#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662
#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663
#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664
#define SRC_REG_FIRSTFREE_RT_OFFSET 6665
#define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6509
#define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6510
#define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6511
#define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6512
#define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6513
#define PRS_REG_SEARCH_TCP_RT_OFFSET 6514
#define PRS_REG_SEARCH_FCOE_RT_OFFSET 6515
#define PRS_REG_SEARCH_ROCE_RT_OFFSET 6516
#define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6517
#define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6518
#define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6519
#define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6520
#define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6521
#define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6522
#define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6523
#define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6524
#define SRC_REG_FIRSTFREE_RT_OFFSET 6525
#define SRC_REG_FIRSTFREE_RT_SIZE 2
#define SRC_REG_LASTFREE_RT_OFFSET 6667
#define SRC_REG_LASTFREE_RT_OFFSET 6527
#define SRC_REG_LASTFREE_RT_SIZE 2
#define SRC_REG_COUNTFREE_RT_OFFSET 6669
#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670
#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671
#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672
#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673
#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674
#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675
#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676
#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677
#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678
#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679
#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680
#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681
#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682
#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683
#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684
#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685
#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686
#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687
#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688
#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689
#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690
#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691
#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692
#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693
#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694
#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695
#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696
#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697
#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698
#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699
#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6700
#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6701
#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6702
#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000
#define PGLUE_REG_B_VF_BASE_RT_OFFSET 28702
#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28703
#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28704
#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705
#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706
#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707
#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708
#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709
#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710
#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711
#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712
#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713
#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714
#define SRC_REG_COUNTFREE_RT_OFFSET 6529
#define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6530
#define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6531
#define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6532
#define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6533
#define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6534
#define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6535
#define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6536
#define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6537
#define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6538
#define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6539
#define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6540
#define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6541
#define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6542
#define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6543
#define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6544
#define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6545
#define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6546
#define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6547
#define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6548
#define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6549
#define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6550
#define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6551
#define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6552
#define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6553
#define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6554
#define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6555
#define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6556
#define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6557
#define PSWRQ2_REG_VF_BASE_RT_OFFSET 6558
#define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6559
#define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6560
#define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6561
#define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET 6562
#define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET 6563
#define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET 6564
#define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET 6565
#define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6566
#define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 26414
#define PGLUE_REG_B_VF_BASE_RT_OFFSET 32980
#define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 32981
#define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 32982
#define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 32983
#define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 32984
#define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 32985
#define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 32986
#define TM_REG_VF_ENABLE_CONN_RT_OFFSET 32987
#define TM_REG_PF_ENABLE_CONN_RT_OFFSET 32988
#define TM_REG_PF_ENABLE_TASK_RT_OFFSET 32989
#define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 32990
#define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 32991
#define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 32992
#define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416
#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130
#define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 33408
#define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608
#define QM_REG_MAXPQSIZE_0_RT_OFFSET 29738
#define QM_REG_MAXPQSIZE_1_RT_OFFSET 29739
#define QM_REG_MAXPQSIZE_2_RT_OFFSET 29740
#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29741
#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29742
#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29743
#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29744
#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29745
#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29746
#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29747
#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29748
#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29749
#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29750
#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29751
#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29752
#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29753
#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29754
#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29755
#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29756
#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29757
#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29758
#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29759
#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29760
#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29761
#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29762
#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29763
#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29764
#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29765
#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29766
#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29767
#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29768
#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29769
#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29770
#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29771
#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29772
#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29773
#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29774
#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29775
#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29776
#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29777
#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29778
#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29779
#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29780
#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29781
#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29782
#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29783
#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29784
#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29785
#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29786
#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29787
#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29788
#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29789
#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29790
#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29791
#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29792
#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29793
#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29794
#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29795
#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29796
#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29797
#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29798
#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29799
#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29800
#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29801
#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29802
#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29803
#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29804
#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29805
#define QM_REG_MAXPQSIZE_0_RT_OFFSET 34016
#define QM_REG_MAXPQSIZE_1_RT_OFFSET 34017
#define QM_REG_MAXPQSIZE_2_RT_OFFSET 34018
#define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 34019
#define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 34020
#define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 34021
#define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 34022
#define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 34023
#define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 34024
#define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 34025
#define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 34026
#define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 34027
#define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 34028
#define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 34029
#define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 34030
#define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 34031
#define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 34032
#define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 34033
#define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 34034
#define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 34035
#define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 34036
#define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 34037
#define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 34038
#define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 34039
#define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 34040
#define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 34041
#define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 34042
#define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 34043
#define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 34044
#define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 34045
#define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 34046
#define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 34047
#define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 34048
#define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 34049
#define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 34050
#define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 34051
#define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 34052
#define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 34053
#define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 34054
#define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 34055
#define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 34056
#define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 34057
#define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 34058
#define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 34059
#define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 34060
#define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 34061
#define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 34062
#define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 34063
#define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 34064
#define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 34065
#define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 34066
#define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 34067
#define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 34068
#define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 34069
#define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 34070
#define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 34071
#define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 34072
#define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 34073
#define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 34074
#define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 34075
#define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 34076
#define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 34077
#define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 34078
#define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 34079
#define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 34080
#define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 34081
#define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 34082
#define QM_REG_BASEADDROTHERPQ_RT_OFFSET 34083
#define QM_REG_BASEADDROTHERPQ_RT_SIZE 128
#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29933
#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29934
#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29935
#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29936
#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29937
#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29938
#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29939
#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29940
#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29941
#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29942
#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29943
#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29944
#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29945
#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29946
#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29947
#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29948
#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29949
#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29950
#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29951
#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29952
#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29953
#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29954
#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29955
#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29956
#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29957
#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29958
#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29959
#define QM_REG_PQTX2PF_0_RT_OFFSET 29960
#define QM_REG_PQTX2PF_1_RT_OFFSET 29961
#define QM_REG_PQTX2PF_2_RT_OFFSET 29962
#define QM_REG_PQTX2PF_3_RT_OFFSET 29963
#define QM_REG_PQTX2PF_4_RT_OFFSET 29964
#define QM_REG_PQTX2PF_5_RT_OFFSET 29965
#define QM_REG_PQTX2PF_6_RT_OFFSET 29966
#define QM_REG_PQTX2PF_7_RT_OFFSET 29967
#define QM_REG_PQTX2PF_8_RT_OFFSET 29968
#define QM_REG_PQTX2PF_9_RT_OFFSET 29969
#define QM_REG_PQTX2PF_10_RT_OFFSET 29970
#define QM_REG_PQTX2PF_11_RT_OFFSET 29971
#define QM_REG_PQTX2PF_12_RT_OFFSET 29972
#define QM_REG_PQTX2PF_13_RT_OFFSET 29973
#define QM_REG_PQTX2PF_14_RT_OFFSET 29974
#define QM_REG_PQTX2PF_15_RT_OFFSET 29975
#define QM_REG_PQTX2PF_16_RT_OFFSET 29976
#define QM_REG_PQTX2PF_17_RT_OFFSET 29977
#define QM_REG_PQTX2PF_18_RT_OFFSET 29978
#define QM_REG_PQTX2PF_19_RT_OFFSET 29979
#define QM_REG_PQTX2PF_20_RT_OFFSET 29980
#define QM_REG_PQTX2PF_21_RT_OFFSET 29981
#define QM_REG_PQTX2PF_22_RT_OFFSET 29982
#define QM_REG_PQTX2PF_23_RT_OFFSET 29983
#define QM_REG_PQTX2PF_24_RT_OFFSET 29984
#define QM_REG_PQTX2PF_25_RT_OFFSET 29985
#define QM_REG_PQTX2PF_26_RT_OFFSET 29986
#define QM_REG_PQTX2PF_27_RT_OFFSET 29987
#define QM_REG_PQTX2PF_28_RT_OFFSET 29988
#define QM_REG_PQTX2PF_29_RT_OFFSET 29989
#define QM_REG_PQTX2PF_30_RT_OFFSET 29990
#define QM_REG_PQTX2PF_31_RT_OFFSET 29991
#define QM_REG_PQTX2PF_32_RT_OFFSET 29992
#define QM_REG_PQTX2PF_33_RT_OFFSET 29993
#define QM_REG_PQTX2PF_34_RT_OFFSET 29994
#define QM_REG_PQTX2PF_35_RT_OFFSET 29995
#define QM_REG_PQTX2PF_36_RT_OFFSET 29996
#define QM_REG_PQTX2PF_37_RT_OFFSET 29997
#define QM_REG_PQTX2PF_38_RT_OFFSET 29998
#define QM_REG_PQTX2PF_39_RT_OFFSET 29999
#define QM_REG_PQTX2PF_40_RT_OFFSET 30000
#define QM_REG_PQTX2PF_41_RT_OFFSET 30001
#define QM_REG_PQTX2PF_42_RT_OFFSET 30002
#define QM_REG_PQTX2PF_43_RT_OFFSET 30003
#define QM_REG_PQTX2PF_44_RT_OFFSET 30004
#define QM_REG_PQTX2PF_45_RT_OFFSET 30005
#define QM_REG_PQTX2PF_46_RT_OFFSET 30006
#define QM_REG_PQTX2PF_47_RT_OFFSET 30007
#define QM_REG_PQTX2PF_48_RT_OFFSET 30008
#define QM_REG_PQTX2PF_49_RT_OFFSET 30009
#define QM_REG_PQTX2PF_50_RT_OFFSET 30010
#define QM_REG_PQTX2PF_51_RT_OFFSET 30011
#define QM_REG_PQTX2PF_52_RT_OFFSET 30012
#define QM_REG_PQTX2PF_53_RT_OFFSET 30013
#define QM_REG_PQTX2PF_54_RT_OFFSET 30014
#define QM_REG_PQTX2PF_55_RT_OFFSET 30015
#define QM_REG_PQTX2PF_56_RT_OFFSET 30016
#define QM_REG_PQTX2PF_57_RT_OFFSET 30017
#define QM_REG_PQTX2PF_58_RT_OFFSET 30018
#define QM_REG_PQTX2PF_59_RT_OFFSET 30019
#define QM_REG_PQTX2PF_60_RT_OFFSET 30020
#define QM_REG_PQTX2PF_61_RT_OFFSET 30021
#define QM_REG_PQTX2PF_62_RT_OFFSET 30022
#define QM_REG_PQTX2PF_63_RT_OFFSET 30023
#define QM_REG_PQOTHER2PF_0_RT_OFFSET 30024
#define QM_REG_PQOTHER2PF_1_RT_OFFSET 30025
#define QM_REG_PQOTHER2PF_2_RT_OFFSET 30026
#define QM_REG_PQOTHER2PF_3_RT_OFFSET 30027
#define QM_REG_PQOTHER2PF_4_RT_OFFSET 30028
#define QM_REG_PQOTHER2PF_5_RT_OFFSET 30029
#define QM_REG_PQOTHER2PF_6_RT_OFFSET 30030
#define QM_REG_PQOTHER2PF_7_RT_OFFSET 30031
#define QM_REG_PQOTHER2PF_8_RT_OFFSET 30032
#define QM_REG_PQOTHER2PF_9_RT_OFFSET 30033
#define QM_REG_PQOTHER2PF_10_RT_OFFSET 30034
#define QM_REG_PQOTHER2PF_11_RT_OFFSET 30035
#define QM_REG_PQOTHER2PF_12_RT_OFFSET 30036
#define QM_REG_PQOTHER2PF_13_RT_OFFSET 30037
#define QM_REG_PQOTHER2PF_14_RT_OFFSET 30038
#define QM_REG_PQOTHER2PF_15_RT_OFFSET 30039
#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 30040
#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 30041
#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 30042
#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 30043
#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 30044
#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 30045
#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 30046
#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 30047
#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 30048
#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 30049
#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 30050
#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 30051
#define QM_REG_RLGLBLINCVAL_RT_OFFSET 30052
#define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 34211
#define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 34212
#define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 34213
#define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 34214
#define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 34215
#define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 34216
#define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 34217
#define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 34218
#define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 34219
#define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 34220
#define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 34221
#define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 34222
#define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 34223
#define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 34224
#define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 34225
#define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 34226
#define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 34227
#define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 34228
#define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 34229
#define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 34230
#define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 34231
#define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 34232
#define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 34233
#define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 34234
#define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 34235
#define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 34236
#define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 34237
#define QM_REG_PQTX2PF_0_RT_OFFSET 34238
#define QM_REG_PQTX2PF_1_RT_OFFSET 34239
#define QM_REG_PQTX2PF_2_RT_OFFSET 34240
#define QM_REG_PQTX2PF_3_RT_OFFSET 34241
#define QM_REG_PQTX2PF_4_RT_OFFSET 34242
#define QM_REG_PQTX2PF_5_RT_OFFSET 34243
#define QM_REG_PQTX2PF_6_RT_OFFSET 34244
#define QM_REG_PQTX2PF_7_RT_OFFSET 34245
#define QM_REG_PQTX2PF_8_RT_OFFSET 34246
#define QM_REG_PQTX2PF_9_RT_OFFSET 34247
#define QM_REG_PQTX2PF_10_RT_OFFSET 34248
#define QM_REG_PQTX2PF_11_RT_OFFSET 34249
#define QM_REG_PQTX2PF_12_RT_OFFSET 34250
#define QM_REG_PQTX2PF_13_RT_OFFSET 34251
#define QM_REG_PQTX2PF_14_RT_OFFSET 34252
#define QM_REG_PQTX2PF_15_RT_OFFSET 34253
#define QM_REG_PQTX2PF_16_RT_OFFSET 34254
#define QM_REG_PQTX2PF_17_RT_OFFSET 34255
#define QM_REG_PQTX2PF_18_RT_OFFSET 34256
#define QM_REG_PQTX2PF_19_RT_OFFSET 34257
#define QM_REG_PQTX2PF_20_RT_OFFSET 34258
#define QM_REG_PQTX2PF_21_RT_OFFSET 34259
#define QM_REG_PQTX2PF_22_RT_OFFSET 34260
#define QM_REG_PQTX2PF_23_RT_OFFSET 34261
#define QM_REG_PQTX2PF_24_RT_OFFSET 34262
#define QM_REG_PQTX2PF_25_RT_OFFSET 34263
#define QM_REG_PQTX2PF_26_RT_OFFSET 34264
#define QM_REG_PQTX2PF_27_RT_OFFSET 34265
#define QM_REG_PQTX2PF_28_RT_OFFSET 34266
#define QM_REG_PQTX2PF_29_RT_OFFSET 34267
#define QM_REG_PQTX2PF_30_RT_OFFSET 34268
#define QM_REG_PQTX2PF_31_RT_OFFSET 34269
#define QM_REG_PQTX2PF_32_RT_OFFSET 34270
#define QM_REG_PQTX2PF_33_RT_OFFSET 34271
#define QM_REG_PQTX2PF_34_RT_OFFSET 34272
#define QM_REG_PQTX2PF_35_RT_OFFSET 34273
#define QM_REG_PQTX2PF_36_RT_OFFSET 34274
#define QM_REG_PQTX2PF_37_RT_OFFSET 34275
#define QM_REG_PQTX2PF_38_RT_OFFSET 34276
#define QM_REG_PQTX2PF_39_RT_OFFSET 34277
#define QM_REG_PQTX2PF_40_RT_OFFSET 34278
#define QM_REG_PQTX2PF_41_RT_OFFSET 34279
#define QM_REG_PQTX2PF_42_RT_OFFSET 34280
#define QM_REG_PQTX2PF_43_RT_OFFSET 34281
#define QM_REG_PQTX2PF_44_RT_OFFSET 34282
#define QM_REG_PQTX2PF_45_RT_OFFSET 34283
#define QM_REG_PQTX2PF_46_RT_OFFSET 34284
#define QM_REG_PQTX2PF_47_RT_OFFSET 34285
#define QM_REG_PQTX2PF_48_RT_OFFSET 34286
#define QM_REG_PQTX2PF_49_RT_OFFSET 34287
#define QM_REG_PQTX2PF_50_RT_OFFSET 34288
#define QM_REG_PQTX2PF_51_RT_OFFSET 34289
#define QM_REG_PQTX2PF_52_RT_OFFSET 34290
#define QM_REG_PQTX2PF_53_RT_OFFSET 34291
#define QM_REG_PQTX2PF_54_RT_OFFSET 34292
#define QM_REG_PQTX2PF_55_RT_OFFSET 34293
#define QM_REG_PQTX2PF_56_RT_OFFSET 34294
#define QM_REG_PQTX2PF_57_RT_OFFSET 34295
#define QM_REG_PQTX2PF_58_RT_OFFSET 34296
#define QM_REG_PQTX2PF_59_RT_OFFSET 34297
#define QM_REG_PQTX2PF_60_RT_OFFSET 34298
#define QM_REG_PQTX2PF_61_RT_OFFSET 34299
#define QM_REG_PQTX2PF_62_RT_OFFSET 34300
#define QM_REG_PQTX2PF_63_RT_OFFSET 34301
#define QM_REG_PQOTHER2PF_0_RT_OFFSET 34302
#define QM_REG_PQOTHER2PF_1_RT_OFFSET 34303
#define QM_REG_PQOTHER2PF_2_RT_OFFSET 34304
#define QM_REG_PQOTHER2PF_3_RT_OFFSET 34305
#define QM_REG_PQOTHER2PF_4_RT_OFFSET 34306
#define QM_REG_PQOTHER2PF_5_RT_OFFSET 34307
#define QM_REG_PQOTHER2PF_6_RT_OFFSET 34308
#define QM_REG_PQOTHER2PF_7_RT_OFFSET 34309
#define QM_REG_PQOTHER2PF_8_RT_OFFSET 34310
#define QM_REG_PQOTHER2PF_9_RT_OFFSET 34311
#define QM_REG_PQOTHER2PF_10_RT_OFFSET 34312
#define QM_REG_PQOTHER2PF_11_RT_OFFSET 34313
#define QM_REG_PQOTHER2PF_12_RT_OFFSET 34314
#define QM_REG_PQOTHER2PF_13_RT_OFFSET 34315
#define QM_REG_PQOTHER2PF_14_RT_OFFSET 34316
#define QM_REG_PQOTHER2PF_15_RT_OFFSET 34317
#define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 34318
#define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 34319
#define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 34320
#define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 34321
#define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 34322
#define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 34323
#define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 34324
#define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 34325
#define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 34326
#define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 34327
#define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 34328
#define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 34329
#define QM_REG_RLGLBLINCVAL_RT_OFFSET 34330
#define QM_REG_RLGLBLINCVAL_RT_SIZE 256
#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30308
#define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 34586
#define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256
#define QM_REG_RLGLBLCRD_RT_OFFSET 30564
#define QM_REG_RLGLBLCRD_RT_OFFSET 34842
#define QM_REG_RLGLBLCRD_RT_SIZE 256
#define QM_REG_RLGLBLENABLE_RT_OFFSET 30820
#define QM_REG_RLPFPERIOD_RT_OFFSET 30821
#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30822
#define QM_REG_RLPFINCVAL_RT_OFFSET 30823
#define QM_REG_RLGLBLENABLE_RT_OFFSET 35098
#define QM_REG_RLPFPERIOD_RT_OFFSET 35099
#define QM_REG_RLPFPERIODTIMER_RT_OFFSET 35100
#define QM_REG_RLPFINCVAL_RT_OFFSET 35101
#define QM_REG_RLPFINCVAL_RT_SIZE 16
#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30839
#define QM_REG_RLPFUPPERBOUND_RT_OFFSET 35117
#define QM_REG_RLPFUPPERBOUND_RT_SIZE 16
#define QM_REG_RLPFCRD_RT_OFFSET 30855
#define QM_REG_RLPFCRD_RT_OFFSET 35133
#define QM_REG_RLPFCRD_RT_SIZE 16
#define QM_REG_RLPFENABLE_RT_OFFSET 30871
#define QM_REG_RLPFVOQENABLE_RT_OFFSET 30872
#define QM_REG_WFQPFWEIGHT_RT_OFFSET 30873
#define QM_REG_RLPFENABLE_RT_OFFSET 35149
#define QM_REG_RLPFVOQENABLE_RT_OFFSET 35150
#define QM_REG_WFQPFWEIGHT_RT_OFFSET 35151
#define QM_REG_WFQPFWEIGHT_RT_SIZE 16
#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30889
#define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 35167
#define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16
#define QM_REG_WFQPFCRD_RT_OFFSET 30905
#define QM_REG_WFQPFCRD_RT_OFFSET 35183
#define QM_REG_WFQPFCRD_RT_SIZE 256
#define QM_REG_WFQPFENABLE_RT_OFFSET 31161
#define QM_REG_WFQVPENABLE_RT_OFFSET 31162
#define QM_REG_BASEADDRTXPQ_RT_OFFSET 31163
#define QM_REG_WFQPFENABLE_RT_OFFSET 35439
#define QM_REG_WFQVPENABLE_RT_OFFSET 35440
#define QM_REG_BASEADDRTXPQ_RT_OFFSET 35441
#define QM_REG_BASEADDRTXPQ_RT_SIZE 512
#define QM_REG_TXPQMAP_RT_OFFSET 31675
#define QM_REG_TXPQMAP_RT_OFFSET 35953
#define QM_REG_TXPQMAP_RT_SIZE 512
#define QM_REG_WFQVPWEIGHT_RT_OFFSET 32187
#define QM_REG_WFQVPWEIGHT_RT_OFFSET 36465
#define QM_REG_WFQVPWEIGHT_RT_SIZE 512
#define QM_REG_WFQVPCRD_RT_OFFSET 32699
#define QM_REG_WFQVPCRD_RT_OFFSET 36977
#define QM_REG_WFQVPCRD_RT_SIZE 512
#define QM_REG_WFQVPMAP_RT_OFFSET 33211
#define QM_REG_WFQVPMAP_RT_OFFSET 37489
#define QM_REG_WFQVPMAP_RT_SIZE 512
#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33723
#define QM_REG_WFQPFCRD_MSB_RT_OFFSET 38001
#define QM_REG_WFQPFCRD_MSB_RT_SIZE 320
#define QM_REG_VOQCRDLINE_RT_OFFSET 34043
#define QM_REG_VOQCRDLINE_RT_OFFSET 38321
#define QM_REG_VOQCRDLINE_RT_SIZE 36
#define QM_REG_VOQINITCRDLINE_RT_OFFSET 34079
#define QM_REG_VOQINITCRDLINE_RT_OFFSET 38357
#define QM_REG_VOQINITCRDLINE_RT_SIZE 36
#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34115
#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34116
#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34117
#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34118
#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34119
#define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34120
#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34121
#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34122
#define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET 38393
#define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 38394
#define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 38395
#define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 38396
#define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 38397
#define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 38398
#define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 38399
#define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 38400
#define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 38401
#define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34126
#define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34130
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 38405
#define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4
#define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34134
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34135
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 38409
#define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34167
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 38441
#define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34183
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 38457
#define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34199
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 38473
#define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34215
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 38489
#define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16
#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34231
#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 34232
#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34233
#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34234
#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34235
#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34236
#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34237
#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34238
#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34239
#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34240
#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34241
#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34242
#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34243
#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34244
#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34245
#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34246
#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34247
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34248
#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34249
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34250
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34251
#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34252
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34253
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34254
#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34255
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34256
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34257
#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34258
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34259
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34260
#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34261
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34262
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34263
#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34264
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34265
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34266
#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34267
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34268
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34269
#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34270
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34271
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34272
#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34273
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34274
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34275
#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34276
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34277
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34278
#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34279
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34280
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34281
#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34282
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34283
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34284
#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34285
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34286
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34287
#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34288
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34289
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34290
#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34291
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34292
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34293
#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34294
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34295
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34296
#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34297
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34298
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34299
#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34300
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34301
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34302
#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34303
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34304
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34305
#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34306
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34307
#define XCM_REG_CON_PHY_Q3_RT_OFFSET 34308
#define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 38505
#define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 38506
#define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 38507
#define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET 38515
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE 1024
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET 39539
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE 512
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET 40051
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE 512
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 40563
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 512
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET 41075
#define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE 512
#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET 41587
#define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE 32
#define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 41619
#define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 41620
#define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 41621
#define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 41622
#define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 41623
#define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 41624
#define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 41625
#define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 41626
#define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 41627
#define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 41628
#define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 41629
#define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 41630
#define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 41631
#define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 41632
#define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 41633
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 41634
#define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 41635
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 41636
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 41637
#define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 41638
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 41639
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 41640
#define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 41641
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 41642
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 41643
#define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 41644
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 41645
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 41646
#define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 41647
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 41648
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 41649
#define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 41650
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 41651
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 41652
#define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 41653
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 41654
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 41655
#define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 41656
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 41657
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 41658
#define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 41659
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 41660
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 41661
#define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 41662
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 41663
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 41664
#define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 41665
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 41666
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 41667
#define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 41668
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 41669
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 41670
#define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 41671
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 41672
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 41673
#define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 41674
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 41675
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 41676
#define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 41677
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 41678
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 41679
#define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 41680
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 41681
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 41682
#define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 41683
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 41684
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 41685
#define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 41686
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 41687
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 41688
#define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 41689
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 41690
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 41691
#define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 41692
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 41693
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET 41694
#define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET 41695
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET 41696
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET 41697
#define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET 41698
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET 41699
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET 41700
#define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET 41701
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET 41702
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET 41703
#define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET 41704
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET 41705
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET 41706
#define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET 41707
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET 41708
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET 41709
#define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET 41710
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET 41711
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET 41712
#define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET 41713
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET 41714
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET 41715
#define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET 41716
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET 41717
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET 41718
#define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET 41719
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET 41720
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET 41721
#define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET 41722
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET 41723
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET 41724
#define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET 41725
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET 41726
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET 41727
#define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET 41728
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET 41729
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET 41730
#define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET 41731
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET 41732
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET 41733
#define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET 41734
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET 41735
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET 41736
#define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET 41737
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET 41738
#define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET 41739
#define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET 41740
#define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET 41741
#define XCM_REG_CON_PHY_Q3_RT_OFFSET 41742
#define RUNTIME_ARRAY_SIZE 34309
#define RUNTIME_ARRAY_SIZE 41743
#endif /* __RT_DEFS_H__ */

4
drivers/net/qede/base/ecore_sp_commands.c
View File

@ -347,7 +347,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
"Unsupported MF mode, init as DEFAULT\n");
p_ramrod->mf_mode = MF_NPAR;
}
p_ramrod->outer_tag = p_hwfn->hw_info.ovlan;
p_ramrod->outer_tag_config.outer_tag.tpid = p_hwfn->hw_info.ovlan;
/* Place EQ address in RAMROD */
DMA_REGPAIR_LE(p_ramrod->event_ring_pbl_addr,
@ -387,7 +387,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
DP_VERBOSE(p_hwfn, ECORE_MSG_SPQ,
"Setting event_ring_sb [id %04x index %02x], outer_tag [%d]\n",
sb, sb_index, p_ramrod->outer_tag);
sb, sb_index, p_ramrod->outer_tag_config.outer_tag.tpid);
rc = ecore_spq_post(p_hwfn, p_ent, OSAL_NULL);

2
drivers/net/qede/base/ecore_spq.c
View File

@ -179,7 +179,7 @@ static void ecore_spq_hw_initialize(struct ecore_hwfn *p_hwfn,
struct ecore_spq *p_spq)
{
struct ecore_cxt_info cxt_info;
struct core_conn_context *p_cxt;
struct e4_core_conn_context *p_cxt;
enum _ecore_status_t rc;
u16 physical_q;

18
drivers/net/qede/base/ecore_sriov.c
View File

@ -1726,7 +1726,7 @@ static void ecore_iov_vf_mbx_acquire(struct ecore_hwfn *p_hwfn,
/* fill in pfdev info */
pfdev_info->chip_num = p_hwfn->p_dev->chip_num;
pfdev_info->db_size = 0; /* @@@ TBD MichalK Vf Doorbells */
pfdev_info->indices_per_sb = PIS_PER_SB;
pfdev_info->indices_per_sb = PIS_PER_SB_E4;
pfdev_info->capabilities = PFVF_ACQUIRE_CAP_DEFAULT_UNTAGGED |
PFVF_ACQUIRE_CAP_POST_FW_OVERRIDE;
@ -3734,11 +3734,11 @@ static enum _ecore_status_t
ecore_iov_vf_flr_poll_pbf(struct ecore_hwfn *p_hwfn,
struct ecore_vf_info *p_vf, struct ecore_ptt *p_ptt)
{
u32 cons[MAX_NUM_VOQS], distance[MAX_NUM_VOQS];
u32 cons[MAX_NUM_VOQS_E4], distance[MAX_NUM_VOQS_E4];
int i, cnt;
/* Read initial consumers & producers */
for (i = 0; i < MAX_NUM_VOQS; i++) {
for (i = 0; i < MAX_NUM_VOQS_E4; i++) {
u32 prod;
cons[i] = ecore_rd(p_hwfn, p_ptt,
@ -3753,7 +3753,7 @@ ecore_iov_vf_flr_poll_pbf(struct ecore_hwfn *p_hwfn,
/* Wait for consumers to pass the producers */
i = 0;
for (cnt = 0; cnt < 50; cnt++) {
for (; i < MAX_NUM_VOQS; i++) {
for (; i < MAX_NUM_VOQS_E4; i++) {
u32 tmp;
tmp = ecore_rd(p_hwfn, p_ptt,
@ -3763,7 +3763,7 @@ ecore_iov_vf_flr_poll_pbf(struct ecore_hwfn *p_hwfn,
break;
}
if (i == MAX_NUM_VOQS)
if (i == MAX_NUM_VOQS_E4)
break;
OSAL_MSLEEP(20);
@ -4255,7 +4255,7 @@ u16 ecore_iov_get_next_active_vf(struct ecore_hwfn *p_hwfn, u16 rel_vf_id)
return i;
out:
return E4_MAX_NUM_VFS;
return MAX_NUM_VFS_E4;
}
enum _ecore_status_t ecore_iov_copy_vf_msg(struct ecore_hwfn *p_hwfn,
@ -4624,6 +4624,7 @@ enum _ecore_status_t ecore_iov_configure_tx_rate(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
int vfid, int val)
{
struct ecore_mcp_link_state *p_link;
struct ecore_vf_info *vf;
u8 abs_vp_id = 0;
enum _ecore_status_t rc;
@ -4637,7 +4638,10 @@ enum _ecore_status_t ecore_iov_configure_tx_rate(struct ecore_hwfn *p_hwfn,
if (rc != ECORE_SUCCESS)
return rc;
return ecore_init_vport_rl(p_hwfn, p_ptt, abs_vp_id, (u32)val);
p_link = &ECORE_LEADING_HWFN(p_hwfn->p_dev)->mcp_info->link_output;
return ecore_init_vport_rl(p_hwfn, p_ptt, abs_vp_id, (u32)val,
p_link->speed);
}
enum _ecore_status_t ecore_iov_get_vf_stats(struct ecore_hwfn *p_hwfn,

4
drivers/net/qede/base/ecore_sriov.h
View File

@ -16,7 +16,7 @@
#include "ecore_l2.h"
#define ECORE_ETH_MAX_VF_NUM_VLAN_FILTERS \
(E4_MAX_NUM_VFS * ECORE_ETH_VF_NUM_VLAN_FILTERS)
(MAX_NUM_VFS_E4 * ECORE_ETH_VF_NUM_VLAN_FILTERS)
/* Represents a full message. Both the request filled by VF
* and the response filled by the PF. The VF needs one copy
@ -170,7 +170,7 @@ struct ecore_vf_info {
* capability enabled.
*/
struct ecore_pf_iov {
struct ecore_vf_info vfs_array[E4_MAX_NUM_VFS];
struct ecore_vf_info vfs_array[MAX_NUM_VFS_E4];
u64 pending_flr[ECORE_VF_ARRAY_LENGTH];
#ifndef REMOVE_DBG

2
drivers/net/qede/base/reg_addr.h
View File

@ -1220,3 +1220,5 @@
#define DORQ_REG_DB_DROP_DETAILS_REASON 0x100a20UL
#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL
#define MCP_REG_CPU_STATE_SOFT_HALTED (0x1 << 10)
#define PRS_REG_SEARCH_TENANT_ID 0x1f044cUL
#define PGLUE_B_REG_VF_BAR1_SIZE 0x2aae68UL

2
drivers/net/qede/qede_main.c
View File

@ -19,7 +19,7 @@
char fw_file[PATH_MAX];
const char *QEDE_DEFAULT_FIRMWARE =
"/lib/firmware/qed/qed_init_values-8.20.0.0.bin";
"/lib/firmware/qed/qed_init_values-8.30.12.0.bin";
static void
qed_update_pf_params(struct ecore_dev *edev, struct ecore_pf_params *params)

8
drivers/net/qede/qede_rxtx.c
View File

@ -364,12 +364,12 @@ qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
uint16_t sb_id)
{
struct ecore_dev *edev = QEDE_INIT_EDEV(qdev);
struct status_block *sb_virt;
struct status_block_e4 *sb_virt;
dma_addr_t sb_phys;
int rc;
sb_virt = OSAL_DMA_ALLOC_COHERENT(edev, &sb_phys,
sizeof(struct status_block));
sizeof(struct status_block_e4));
if (!sb_virt) {
DP_ERR(edev, "Status block allocation failed\n");
return -ENOMEM;
@ -379,7 +379,7 @@ qede_alloc_mem_sb(struct qede_dev *qdev, struct ecore_sb_info *sb_info,
if (rc) {
DP_ERR(edev, "Status block initialization failed\n");
OSAL_DMA_FREE_COHERENT(edev, sb_virt, sb_phys,
sizeof(struct status_block));
sizeof(struct status_block_e4));
return rc;
}
@ -453,7 +453,7 @@ void qede_dealloc_fp_resc(struct rte_eth_dev *eth_dev)
if (fp->sb_info) {
OSAL_DMA_FREE_COHERENT(edev, fp->sb_info->sb_virt,
fp->sb_info->sb_phys,
sizeof(struct status_block));
sizeof(struct status_block_e4));
rte_free(fp->sb_info);
fp->sb_info = NULL;
}