event/octeontx2: create and free timer adapter
When the application calls timer adapter create the following is used: - Allocate a TIM lf based on number of lf's provisioned. - Verify the config parameters supplied. - Allocate memory required for * Buckets based on min and max timeout supplied. * Allocate the chunk pool based on the number of timers. On Free: - Free the allocated bucket and chunk memory. - Free the TIM lf allocated. Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
This commit is contained in:
Pavan Nikhilesh
Jerin Jacob
parent
278821213a
commit
411c062505
@ -2,9 +2,263 @@
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include <rte_malloc.h>
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#include <rte_mbuf_pool_ops.h>
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#include "otx2_evdev.h"
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#include "otx2_tim_evdev.h"
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static struct rte_event_timer_adapter_ops otx2_tim_ops;
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static int
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tim_chnk_pool_create(struct otx2_tim_ring *tim_ring,
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struct rte_event_timer_adapter_conf *rcfg)
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{
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unsigned int cache_sz = (tim_ring->nb_chunks / 1.5);
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unsigned int mp_flags = 0;
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char pool_name[25];
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int rc;
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/* Create chunk pool. */
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if (rcfg->flags & RTE_EVENT_TIMER_ADAPTER_F_SP_PUT) {
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mp_flags = MEMPOOL_F_SP_PUT | MEMPOOL_F_SC_GET;
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otx2_tim_dbg("Using single producer mode");
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tim_ring->prod_type_sp = true;
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}
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snprintf(pool_name, sizeof(pool_name), "otx2_tim_chunk_pool%d",
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tim_ring->ring_id);
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if (cache_sz > RTE_MEMPOOL_CACHE_MAX_SIZE)
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cache_sz = RTE_MEMPOOL_CACHE_MAX_SIZE;
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/* NPA need not have cache as free is not visible to SW */
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tim_ring->chunk_pool = rte_mempool_create_empty(pool_name,
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tim_ring->nb_chunks,
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tim_ring->chunk_sz,
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0, 0, rte_socket_id(),
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mp_flags);
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if (tim_ring->chunk_pool == NULL) {
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otx2_err("Unable to create chunkpool.");
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return -ENOMEM;
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}
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rc = rte_mempool_set_ops_byname(tim_ring->chunk_pool,
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rte_mbuf_platform_mempool_ops(), NULL);
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if (rc < 0) {
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otx2_err("Unable to set chunkpool ops");
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goto free;
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}
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rc = rte_mempool_populate_default(tim_ring->chunk_pool);
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if (rc < 0) {
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otx2_err("Unable to set populate chunkpool.");
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goto free;
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}
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tim_ring->aura = npa_lf_aura_handle_to_aura(
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tim_ring->chunk_pool->pool_id);
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tim_ring->ena_dfb = 0;
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return 0;
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free:
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rte_mempool_free(tim_ring->chunk_pool);
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return rc;
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}
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static void
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tim_err_desc(int rc)
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{
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switch (rc) {
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case TIM_AF_NO_RINGS_LEFT:
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otx2_err("Unable to allocat new TIM ring.");
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break;
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case TIM_AF_INVALID_NPA_PF_FUNC:
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otx2_err("Invalid NPA pf func.");
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break;
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case TIM_AF_INVALID_SSO_PF_FUNC:
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otx2_err("Invalid SSO pf func.");
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break;
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case TIM_AF_RING_STILL_RUNNING:
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otx2_tim_dbg("Ring busy.");
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break;
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case TIM_AF_LF_INVALID:
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otx2_err("Invalid Ring id.");
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break;
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case TIM_AF_CSIZE_NOT_ALIGNED:
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otx2_err("Chunk size specified needs to be multiple of 16.");
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break;
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case TIM_AF_CSIZE_TOO_SMALL:
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otx2_err("Chunk size too small.");
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break;
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case TIM_AF_CSIZE_TOO_BIG:
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otx2_err("Chunk size too big.");
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break;
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case TIM_AF_INTERVAL_TOO_SMALL:
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otx2_err("Bucket traversal interval too small.");
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break;
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case TIM_AF_INVALID_BIG_ENDIAN_VALUE:
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otx2_err("Invalid Big endian value.");
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break;
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case TIM_AF_INVALID_CLOCK_SOURCE:
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otx2_err("Invalid Clock source specified.");
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break;
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case TIM_AF_GPIO_CLK_SRC_NOT_ENABLED:
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otx2_err("GPIO clock source not enabled.");
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break;
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case TIM_AF_INVALID_BSIZE:
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otx2_err("Invalid bucket size.");
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break;
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case TIM_AF_INVALID_ENABLE_PERIODIC:
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otx2_err("Invalid bucket size.");
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break;
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case TIM_AF_INVALID_ENABLE_DONTFREE:
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otx2_err("Invalid Don't free value.");
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break;
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case TIM_AF_ENA_DONTFRE_NSET_PERIODIC:
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otx2_err("Don't free bit not set when periodic is enabled.");
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break;
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case TIM_AF_RING_ALREADY_DISABLED:
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otx2_err("Ring already stopped");
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break;
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default:
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otx2_err("Unknown Error.");
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}
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}
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static int
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otx2_tim_ring_create(struct rte_event_timer_adapter *adptr)
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{
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struct rte_event_timer_adapter_conf *rcfg = &adptr->data->conf;
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struct otx2_tim_evdev *dev = tim_priv_get();
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struct otx2_tim_ring *tim_ring;
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struct tim_config_req *cfg_req;
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struct tim_ring_req *free_req;
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struct tim_lf_alloc_req *req;
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struct tim_lf_alloc_rsp *rsp;
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uint64_t nb_timers;
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int rc;
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if (dev == NULL)
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return -ENODEV;
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if (adptr->data->id >= dev->nb_rings)
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return -ENODEV;
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req = otx2_mbox_alloc_msg_tim_lf_alloc(dev->mbox);
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req->npa_pf_func = otx2_npa_pf_func_get();
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req->sso_pf_func = otx2_sso_pf_func_get();
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req->ring = adptr->data->id;
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rc = otx2_mbox_process_msg(dev->mbox, (void **)&rsp);
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if (rc < 0) {
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tim_err_desc(rc);
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return -ENODEV;
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}
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if (NSEC2TICK(RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10),
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rsp->tenns_clk) < OTX2_TIM_MIN_TMO_TKS) {
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rc = -ERANGE;
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goto rng_mem_err;
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}
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tim_ring = rte_zmalloc("otx2_tim_prv", sizeof(struct otx2_tim_ring), 0);
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if (tim_ring == NULL) {
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rc = -ENOMEM;
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goto rng_mem_err;
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}
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adptr->data->adapter_priv = tim_ring;
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tim_ring->tenns_clk_freq = rsp->tenns_clk;
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tim_ring->clk_src = (int)rcfg->clk_src;
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tim_ring->ring_id = adptr->data->id;
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tim_ring->tck_nsec = RTE_ALIGN_MUL_CEIL(rcfg->timer_tick_ns, 10);
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tim_ring->max_tout = rcfg->max_tmo_ns;
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tim_ring->nb_bkts = (tim_ring->max_tout / tim_ring->tck_nsec);
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tim_ring->chunk_sz = OTX2_TIM_RING_DEF_CHUNK_SZ;
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nb_timers = rcfg->nb_timers;
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tim_ring->nb_chunks = nb_timers / OTX2_TIM_NB_CHUNK_SLOTS(
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tim_ring->chunk_sz);
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tim_ring->nb_chunk_slots = OTX2_TIM_NB_CHUNK_SLOTS(tim_ring->chunk_sz);
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/* Create buckets. */
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tim_ring->bkt = rte_zmalloc("otx2_tim_bucket", (tim_ring->nb_bkts) *
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sizeof(struct otx2_tim_bkt),
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RTE_CACHE_LINE_SIZE);
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if (tim_ring->bkt == NULL)
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goto bkt_mem_err;
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rc = tim_chnk_pool_create(tim_ring, rcfg);
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if (rc < 0)
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goto chnk_mem_err;
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cfg_req = otx2_mbox_alloc_msg_tim_config_ring(dev->mbox);
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cfg_req->ring = tim_ring->ring_id;
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cfg_req->bigendian = false;
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cfg_req->clocksource = tim_ring->clk_src;
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cfg_req->enableperiodic = false;
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cfg_req->enabledontfreebuffer = tim_ring->ena_dfb;
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cfg_req->bucketsize = tim_ring->nb_bkts;
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cfg_req->chunksize = tim_ring->chunk_sz;
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cfg_req->interval = NSEC2TICK(tim_ring->tck_nsec,
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tim_ring->tenns_clk_freq);
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rc = otx2_mbox_process(dev->mbox);
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if (rc < 0) {
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tim_err_desc(rc);
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goto chnk_mem_err;
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}
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tim_ring->base = dev->bar2 +
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(RVU_BLOCK_ADDR_TIM << 20 | tim_ring->ring_id << 12);
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otx2_write64((uint64_t)tim_ring->bkt,
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tim_ring->base + TIM_LF_RING_BASE);
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otx2_write64(tim_ring->aura, tim_ring->base + TIM_LF_RING_AURA);
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return rc;
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chnk_mem_err:
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rte_free(tim_ring->bkt);
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bkt_mem_err:
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rte_free(tim_ring);
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rng_mem_err:
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free_req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
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free_req->ring = adptr->data->id;
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otx2_mbox_process(dev->mbox);
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return rc;
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}
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static int
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otx2_tim_ring_free(struct rte_event_timer_adapter *adptr)
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{
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struct otx2_tim_ring *tim_ring = adptr->data->adapter_priv;
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struct otx2_tim_evdev *dev = tim_priv_get();
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struct tim_ring_req *req;
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int rc;
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if (dev == NULL)
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return -ENODEV;
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req = otx2_mbox_alloc_msg_tim_lf_free(dev->mbox);
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req->ring = tim_ring->ring_id;
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rc = otx2_mbox_process(dev->mbox);
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if (rc < 0) {
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tim_err_desc(rc);
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return -EBUSY;
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}
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rte_free(tim_ring->bkt);
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rte_mempool_free(tim_ring->chunk_pool);
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rte_free(adptr->data->adapter_priv);
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return 0;
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}
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int
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otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
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uint32_t *caps,
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@ -13,13 +267,16 @@ otx2_tim_caps_get(const struct rte_eventdev *evdev, uint64_t flags,
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struct otx2_tim_evdev *dev = tim_priv_get();
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RTE_SET_USED(flags);
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RTE_SET_USED(ops);
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if (dev == NULL)
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return -ENODEV;
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otx2_tim_ops.init = otx2_tim_ring_create;
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otx2_tim_ops.uninit = otx2_tim_ring_free;
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/* Store evdev pointer for later use. */
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dev->event_dev = (struct rte_eventdev *)(uintptr_t)evdev;
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*caps = RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT;
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*ops = &otx2_tim_ops;
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return 0;
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}
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@ -6,11 +6,47 @@
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#define __OTX2_TIM_EVDEV_H__
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#include <rte_event_timer_adapter.h>
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#include <rte_event_timer_adapter_pmd.h>
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#include "otx2_dev.h"
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#define OTX2_TIM_EVDEV_NAME otx2_tim_eventdev
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#define otx2_tim_func_trace otx2_tim_dbg
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#define TIM_LF_RING_AURA (0x0)
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#define TIM_LF_RING_BASE (0x130)
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#define OTX2_TIM_RING_DEF_CHUNK_SZ (4096)
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#define OTX2_TIM_CHUNK_ALIGNMENT (16)
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#define OTX2_TIM_NB_CHUNK_SLOTS(sz) (((sz) / OTX2_TIM_CHUNK_ALIGNMENT) - 1)
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#define OTX2_TIM_MIN_TMO_TKS (256)
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enum otx2_tim_clk_src {
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OTX2_TIM_CLK_SRC_10NS = RTE_EVENT_TIMER_ADAPTER_CPU_CLK,
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OTX2_TIM_CLK_SRC_GPIO = RTE_EVENT_TIMER_ADAPTER_EXT_CLK0,
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OTX2_TIM_CLK_SRC_GTI = RTE_EVENT_TIMER_ADAPTER_EXT_CLK1,
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OTX2_TIM_CLK_SRC_PTP = RTE_EVENT_TIMER_ADAPTER_EXT_CLK2,
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};
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struct otx2_tim_bkt {
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uint64_t first_chunk;
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union {
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uint64_t w1;
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struct {
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uint32_t nb_entry;
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uint8_t sbt:1;
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uint8_t hbt:1;
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uint8_t bsk:1;
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uint8_t rsvd:5;
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uint8_t lock;
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int16_t chunk_remainder;
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};
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};
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uint64_t current_chunk;
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uint64_t pad;
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} __rte_packed __rte_aligned(32);
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struct otx2_tim_evdev {
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struct rte_pci_device *pci_dev;
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struct rte_eventdev *event_dev;
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@ -19,6 +55,25 @@ struct otx2_tim_evdev {
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uintptr_t bar2;
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};
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struct otx2_tim_ring {
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uintptr_t base;
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uint16_t nb_chunk_slots;
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uint32_t nb_bkts;
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struct otx2_tim_bkt *bkt;
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struct rte_mempool *chunk_pool;
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uint64_t tck_int;
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uint8_t prod_type_sp;
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uint8_t ena_dfb;
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uint16_t ring_id;
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uint32_t aura;
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uint64_t tck_nsec;
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uint64_t max_tout;
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uint64_t nb_chunks;
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uint64_t chunk_sz;
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uint64_t tenns_clk_freq;
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enum otx2_tim_clk_src clk_src;
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} __rte_cache_aligned;
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static inline struct otx2_tim_evdev *
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tim_priv_get(void)
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{
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