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crypto/mlx5: fix queue indexing

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The crypto QP consumer (ci) and producer (pi) indexes are increased
with each successful enqueue/dequeue operations.

However the QP pi index is calculated with a wraparound the number
of elements while the QP ci does not.

This is causing incorrect engine calculation for encqueued WQ values
(wq->pi - wq->ci) and eventually the device stops accepting new enqueue
operations.

Fixed by removing the wraparound on QP pi and using a temp calculation
where wraparound values are needed.

Fixes: 8e196c08ab ("crypto/mlx5: support enqueue/dequeue operations")
Cc: stable@dpdk.org

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
This commit is contained in:
Tal Shnaiderman 2021-09-13 17:02:24 +03:00 committed by Akhil Goyal
parent c9902a15bd
commit 427ec3346d
1 changed files with 5 additions and 3 deletions
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8
drivers/crypto/mlx5/mlx5_crypto.c
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@ -494,6 +494,7 @@ mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
struct rte_crypto_op *op;
uint16_t mask = qp->entries_n - 1;
uint16_t remain = qp->entries_n - (qp->pi - qp->ci);
uint32_t idx;
if (remain < nb_ops)
nb_ops = remain;
@ -502,8 +503,9 @@ mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
if (unlikely(remain == 0))
return 0;
do {
idx = qp->pi & mask;
op = *ops++;
umr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * qp->pi);
umr = RTE_PTR_ADD(qp->umem_buf, priv->wqe_set_size * idx);
if (unlikely(mlx5_crypto_wqe_set(priv, qp, op, umr) == 0)) {
qp->stats.enqueue_err_count++;
if (remain != nb_ops) {
@ -512,8 +514,8 @@ mlx5_crypto_enqueue_burst(void *queue_pair, struct rte_crypto_op **ops,
}
return 0;
}
qp->ops[qp->pi] = op;
qp->pi = (qp->pi + 1) & mask;
qp->ops[idx] = op;
qp->pi++;
} while (--remain);
qp->stats.enqueued_count += nb_ops;
rte_io_wmb();