net/hns3: get device capability from firmware
This patch adds getting device capabilities from firmware, so driver can supply different capabilities and specifications to upper level applications base on different versions of hardware network engine. Signed-off-by: Wei Hu (Xavier) <xavier.huwei@huawei.com>
This commit is contained in:
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126a2c485c
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4387523581
@ -426,8 +426,29 @@ hns3_cmd_send(struct hns3_hw *hw, struct hns3_cmd_desc *desc, int num)
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return retval;
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return retval;
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}
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}
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static void hns3_parse_capability(struct hns3_hw *hw,
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struct hns3_query_version_cmd *cmd)
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{
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uint32_t caps = rte_le_to_cpu_32(cmd->caps[0]);
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if (hns3_get_bit(caps, HNS3_CAPS_UDP_GSO_B))
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hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_UDP_GSO_B, 1);
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if (hns3_get_bit(caps, HNS3_CAPS_ADQ_B))
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hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_ADQ_B, 1);
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if (hns3_get_bit(caps, HNS3_CAPS_PTP_B))
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hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_PTP_B, 1);
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if (hns3_get_bit(caps, HNS3_CAPS_TX_PUSH_B))
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hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_TX_PUSH_B, 1);
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if (hns3_get_bit(caps, HNS3_CAPS_PHY_IMP_B))
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hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1);
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if (hns3_get_bit(caps, HNS3_CAPS_TQP_TXRX_INDEP_B))
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hns3_set_bit(hw->capability, HNS3_CAPS_TQP_TXRX_INDEP_B, 1);
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if (hns3_get_bit(caps, HNS3_CAPS_STASH_B))
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hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_STASH_B, 1);
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}
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static enum hns3_cmd_status
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static enum hns3_cmd_status
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hns3_cmd_query_firmware_version(struct hns3_hw *hw, uint32_t *version)
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hns3_cmd_query_firmware_version_and_capability(struct hns3_hw *hw)
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{
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{
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struct hns3_query_version_cmd *resp;
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struct hns3_query_version_cmd *resp;
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struct hns3_cmd_desc desc;
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struct hns3_cmd_desc desc;
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@ -438,10 +459,13 @@ hns3_cmd_query_firmware_version(struct hns3_hw *hw, uint32_t *version)
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/* Initialize the cmd function */
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/* Initialize the cmd function */
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ret = hns3_cmd_send(hw, &desc, 1);
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ret = hns3_cmd_send(hw, &desc, 1);
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if (ret == 0)
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if (ret)
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*version = rte_le_to_cpu_32(resp->firmware);
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return ret;
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return ret;
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hw->fw_version = rte_le_to_cpu_32(resp->firmware);
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hns3_parse_capability(hw, resp);
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return 0;
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}
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}
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int
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int
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@ -519,13 +543,13 @@ hns3_cmd_init(struct hns3_hw *hw)
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}
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}
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rte_atomic16_clear(&hw->reset.disable_cmd);
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rte_atomic16_clear(&hw->reset.disable_cmd);
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ret = hns3_cmd_query_firmware_version(hw, &version);
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ret = hns3_cmd_query_firmware_version_and_capability(hw);
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if (ret) {
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if (ret) {
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PMD_INIT_LOG(ERR, "firmware version query failed %d", ret);
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PMD_INIT_LOG(ERR, "firmware version query failed %d", ret);
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goto err_cmd_init;
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goto err_cmd_init;
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}
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}
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hw->fw_version = version;
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version = hw->fw_version;
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PMD_INIT_LOG(INFO, "The firmware version is %lu.%lu.%lu.%lu",
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PMD_INIT_LOG(INFO, "The firmware version is %lu.%lu.%lu.%lu",
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hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
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hns3_get_field(version, HNS3_FW_VERSION_BYTE3_M,
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HNS3_FW_VERSION_BYTE3_S),
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HNS3_FW_VERSION_BYTE3_S),
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@ -264,9 +264,26 @@ struct hns3_rx_priv_buff_cmd {
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#define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
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#define HNS3_FW_VERSION_BYTE1_M GENMASK(15, 8)
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#define HNS3_FW_VERSION_BYTE0_S 0
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#define HNS3_FW_VERSION_BYTE0_S 0
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#define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
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#define HNS3_FW_VERSION_BYTE0_M GENMASK(7, 0)
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enum HNS3_CAPS_BITS {
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HNS3_CAPS_UDP_GSO_B,
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HNS3_CAPS_ATR_B,
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HNS3_CAPS_ADQ_B,
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HNS3_CAPS_PTP_B,
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HNS3_CAPS_INT_QL_B,
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HNS3_CAPS_SIMPLE_BD_B,
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HNS3_CAPS_TX_PUSH_B,
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HNS3_CAPS_PHY_IMP_B,
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HNS3_CAPS_TQP_TXRX_INDEP_B,
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HNS3_CAPS_HW_PAD_B,
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HNS3_CAPS_STASH_B,
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};
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#define HNS3_QUERY_CAP_LENGTH 3
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struct hns3_query_version_cmd {
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struct hns3_query_version_cmd {
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uint32_t firmware;
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uint32_t firmware;
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uint32_t firmware_rsv[5];
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uint32_t hardware;
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uint32_t rsv;
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uint32_t caps[HNS3_QUERY_CAP_LENGTH]; /* capabilities of device */
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};
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};
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#define HNS3_RX_PRIV_EN_B 15
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#define HNS3_RX_PRIV_EN_B 15
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@ -2837,9 +2837,6 @@ hns3_get_capability(struct hns3_hw *hw)
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}
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}
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hw->revision = revision;
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hw->revision = revision;
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if (revision >= PCI_REVISION_ID_HIP09_A)
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hns3_set_bit(hw->capability, HNS3_DEV_SUPPORT_COPPER_B, 1);
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return 0;
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return 0;
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}
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}
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@ -535,13 +535,42 @@ struct hns3_adapter {
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#define HNS3_DEV_SUPPORT_DCB_B 0x0
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#define HNS3_DEV_SUPPORT_DCB_B 0x0
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#define HNS3_DEV_SUPPORT_COPPER_B 0x1
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#define HNS3_DEV_SUPPORT_COPPER_B 0x1
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#define HNS3_DEV_SUPPORT_UDP_GSO_B 0x2
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#define HNS3_DEV_SUPPORT_ADQ_B 0x3
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#define HNS3_DEV_SUPPORT_PTP_B 0x4
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#define HNS3_DEV_SUPPORT_TX_PUSH_B 0x5
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#define HNS3_DEV_SUPPORT_INDEP_TXRX_B 0x6
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#define HNS3_DEV_SUPPORT_STASH_B 0x7
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#define hns3_dev_dcb_supported(hw) \
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#define hns3_dev_dcb_supported(hw) \
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_DCB_B)
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/* Support copper media type */
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#define hns3_dev_copper_supported(hw) \
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#define hns3_dev_copper_supported(hw) \
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_COPPER_B)
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/* Support UDP GSO offload */
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#define hns3_dev_udp_gso_supported(hw) \
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_UDP_GSO_B)
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/* Support Application Device Queue */
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#define hns3_dev_adq_supported(hw) \
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_ADQ_B)
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/* Support PTP timestamp offload */
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#define hns3_dev_ptp_supported(hw) \
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_PTP_B)
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#define hns3_dev_tx_push_supported(hw) \
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_TX_PUSH_B)
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/* Support to Independently enable/disable/reset Tx or Rx queues */
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#define hns3_dev_indep_txrx_supported(hw) \
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_INDEP_TXRX_B)
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#define hns3_dev_stash_supported(hw) \
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hns3_get_bit((hw)->capability, HNS3_DEV_SUPPORT_STASH_B)
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#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
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#define HNS3_DEV_PRIVATE_TO_HW(adapter) \
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(&((struct hns3_adapter *)adapter)->hw)
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(&((struct hns3_adapter *)adapter)->hw)
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#define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
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#define HNS3_DEV_PRIVATE_TO_ADAPTER(adapter) \
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