net/i40e: enable PCI bus master after reset
The VF reset can be triggered by the PF reset event, then the PCI bus master will be cleared, the VF will be not allowed to issue any Memory or I/O Requests. So after the reset event is detected, always enable the PCI bus master. And if failed, the device or system may be in an invalid state, so keep the VF reset state to mark it as I/O error. Signed-off-by: Haiyue Wang <haiyue.wang@intel.com> Acked-by: Beilei Xing <beilei.xing@intel.com>
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@ -1213,7 +1213,6 @@ i40evf_check_vf_reset_done(struct rte_eth_dev *dev)
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if (i >= MAX_RESET_WAIT_CNT)
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return -1;
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vf->vf_reset = false;
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vf->pend_msg &= ~PFMSG_RESET_IMPENDING;
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return 0;
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@ -1392,6 +1391,7 @@ i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
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switch (pf_msg->event) {
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case VIRTCHNL_EVENT_RESET_IMPENDING:
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PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
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vf->vf_reset = true;
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rte_eth_dev_callback_process(dev,
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RTE_ETH_EVENT_INTR_RESET, NULL);
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break;
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@ -2468,6 +2468,7 @@ i40evf_dev_close(struct rte_eth_dev *dev)
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{
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struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
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struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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int ret;
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if (rte_eal_process_type() != RTE_PROC_PRIMARY)
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@ -2490,6 +2491,16 @@ i40evf_dev_close(struct rte_eth_dev *dev)
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i40e_shutdown_adminq(hw);
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i40evf_disable_irq0(hw);
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/*
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* If the VF is reset via VFLR, the device will be knocked out of bus
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* master mode, and the driver will fail to recover from the reset. Fix
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* this by enabling bus mastering after every reset. In a non-VFLR case,
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* the bus master bit will not be disabled, and this call will have no
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* effect.
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*/
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if (vf->vf_reset && !rte_pci_set_bus_master(pci_dev, true))
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vf->vf_reset = false;
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rte_free(vf->vf_res);
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vf->vf_res = NULL;
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rte_free(vf->aq_resp);
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