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net/ionic: do minor logging fixups

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Expose ionic_opcode_to_str() so it can be used for dev cmds, too.
Store the device name in struct adapter.

Switch to memcpy() to work around gcc false positives.

Signed-off-by: Andrew Boyer <aboyer@pensando.io>
Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Andrew Boyer 2020-12-09 18:57:37 -08:00 committed by Ferruh Yigit
parent 75f9690223
commit 4ae96cb88f
7 changed files with 64 additions and 49 deletions
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1
drivers/net/ionic/ionic.h
View File

@ -48,6 +48,7 @@ struct ionic_hw {
struct ionic_adapter {
struct ionic_hw hw;
struct ionic_dev idev;
const char *name;
struct ionic_dev_bar bars[IONIC_BARS_MAX];
struct ionic_identity ident;
struct ionic_lif *lifs[IONIC_LIFS_MAX];

5
drivers/net/ionic/ionic_dev.c
View File

@ -102,6 +102,9 @@ ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd)
uint32_t cmd_size = sizeof(cmd->words) /
sizeof(cmd->words[0]);
IONIC_PRINT(DEBUG, "Sending %s (%d) via dev_cmd",
ionic_opcode_to_str(cmd->cmd.opcode), cmd->cmd.opcode);
for (i = 0; i < cmd_size; i++)
iowrite32(cmd->words[i], &idev->dev_cmd->cmd.words[i]);
@ -348,6 +351,8 @@ ionic_dev_cmd_adminq_init(struct ionic_dev *idev,
.q_init.cq_ring_base = cq->base_pa,
};
IONIC_PRINT(DEBUG, "adminq.q_init.ver %u", cmd.q_init.ver);
ionic_dev_cmd_go(idev, &cmd);
}

2
drivers/net/ionic/ionic_dev.h
View File

@ -205,6 +205,8 @@ struct ionic_qcq;
void ionic_intr_init(struct ionic_dev *idev, struct ionic_intr_info *intr,
unsigned long index);
const char *ionic_opcode_to_str(enum ionic_cmd_opcode opcode);
int ionic_dev_setup(struct ionic_adapter *adapter);
void ionic_dev_cmd_go(struct ionic_dev *idev, union ionic_dev_cmd *cmd);

4
drivers/net/ionic/ionic_ethdev.c
View File

@ -571,7 +571,7 @@ ionic_dev_rss_reta_update(struct rte_eth_dev *eth_dev,
if (reta_size != ident->lif.eth.rss_ind_tbl_sz) {
IONIC_PRINT(ERR, "The size of hash lookup table configured "
"(%d) doesn't match the number hardware can supported "
"(%d) does not match the number hardware can support "
"(%d)",
reta_size, ident->lif.eth.rss_ind_tbl_sz);
return -EINVAL;
@ -605,7 +605,7 @@ ionic_dev_rss_reta_query(struct rte_eth_dev *eth_dev,
if (reta_size != ident->lif.eth.rss_ind_tbl_sz) {
IONIC_PRINT(ERR, "The size of hash lookup table configured "
"(%d) doesn't match the number hardware can supported "
"(%d) does not match the number hardware can support "
"(%d)",
reta_size, ident->lif.eth.rss_ind_tbl_sz);
return -EINVAL;

28
drivers/net/ionic/ionic_lif.c
View File

@ -84,7 +84,7 @@ ionic_lif_reset(struct ionic_lif *lif)
ionic_dev_cmd_lif_reset(idev, lif->index);
err = ionic_dev_cmd_wait_check(idev, IONIC_DEVCMD_TIMEOUT);
if (err)
IONIC_PRINT(WARNING, "Failed to reset lif");
IONIC_PRINT(WARNING, "Failed to reset %s", lif->name);
}
static void
@ -554,7 +554,7 @@ ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
/*
* Note: interrupt handler is called for index = 0 only
* (we use interrupts for the notifyq only anyway,
* which hash index = 0)
* which has index = 0)
*/
for (index = 0; index < adapter->nintrs; index++)
@ -687,8 +687,8 @@ ionic_qcq_alloc(struct ionic_lif *lif, uint8_t type,
ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
}
IONIC_PRINT(DEBUG, "Q-Base-PA = %ju CQ-Base-PA = %ju "
"SG-base-PA = %ju",
IONIC_PRINT(DEBUG, "Q-Base-PA = %#jx CQ-Base-PA = %#jx "
"SG-base-PA = %#jx",
q_base_pa, cq_base_pa, sg_base_pa);
ionic_q_map(&new->q, q_base, q_base_pa);
@ -827,7 +827,13 @@ ionic_lif_alloc(struct ionic_lif *lif)
int dbpage_num;
int err;
snprintf(lif->name, sizeof(lif->name), "lif%u", lif->index);
/*
* lif->name was zeroed on allocation.
* Copy (sizeof() - 1) bytes to ensure that it is NULL terminated.
*/
memcpy(lif->name, lif->eth_dev->data->name, sizeof(lif->name) - 1);
IONIC_PRINT(DEBUG, "LIF: %s", lif->name);
IONIC_PRINT(DEBUG, "Allocating Lif Info");
@ -868,8 +874,6 @@ ionic_lif_alloc(struct ionic_lif *lif)
IONIC_PRINT(DEBUG, "Allocating Admin Queue");
IONIC_PRINT(DEBUG, "Allocating Admin Queue");
err = ionic_admin_qcq_alloc(lif);
if (err) {
IONIC_PRINT(ERR, "Cannot allocate admin queue");
@ -1223,6 +1227,7 @@ ionic_lif_notifyq_init(struct ionic_lif *lif)
ctx.cmd.q_init.ring_base);
IONIC_PRINT(DEBUG, "notifyq_init.ring_size %d",
ctx.cmd.q_init.ring_size);
IONIC_PRINT(DEBUG, "notifyq_init.ver %u", ctx.cmd.q_init.ver);
err = ionic_adminq_post_wait(lif, &ctx);
if (err)
@ -1332,6 +1337,7 @@ ionic_lif_txq_init(struct ionic_qcq *qcq)
ctx.cmd.q_init.ring_base);
IONIC_PRINT(DEBUG, "txq_init.ring_size %d",
ctx.cmd.q_init.ring_size);
IONIC_PRINT(DEBUG, "txq_init.ver %u", ctx.cmd.q_init.ver);
err = ionic_adminq_post_wait(qcq->lif, &ctx);
if (err)
@ -1378,6 +1384,7 @@ ionic_lif_rxq_init(struct ionic_qcq *qcq)
ctx.cmd.q_init.ring_base);
IONIC_PRINT(DEBUG, "rxq_init.ring_size %d",
ctx.cmd.q_init.ring_size);
IONIC_PRINT(DEBUG, "rxq_init.ver %u", ctx.cmd.q_init.ver);
err = ionic_adminq_post_wait(qcq->lif, &ctx);
if (err)
@ -1448,8 +1455,8 @@ ionic_lif_set_name(struct ionic_lif *lif)
},
};
snprintf(ctx.cmd.lif_setattr.name, sizeof(ctx.cmd.lif_setattr.name),
"%d", lif->port_id);
memcpy(ctx.cmd.lif_setattr.name, lif->name,
sizeof(ctx.cmd.lif_setattr.name) - 1);
ionic_adminq_post_wait(lif, &ctx);
}
@ -1680,7 +1687,8 @@ ionic_lifs_size(struct ionic_adapter *adapter)
nintrs = nlifs * 1 /* notifyq */;
if (nintrs > dev_nintrs) {
IONIC_PRINT(ERR, "At most %d intr queues supported, minimum required is %u",
IONIC_PRINT(ERR,
"At most %d intr supported, minimum req'd is %u",
dev_nintrs, nintrs);
return -ENOSPC;
}

32
drivers/net/ionic/ionic_main.c
View File

@ -61,7 +61,7 @@ ionic_error_to_str(enum ionic_status_code code)
}
}
static const char *
const char *
ionic_opcode_to_str(enum ionic_cmd_opcode opcode)
{
switch (opcode) {
@ -107,6 +107,8 @@ ionic_opcode_to_str(enum ionic_cmd_opcode opcode)
return "IONIC_CMD_Q_INIT";
case IONIC_CMD_Q_CONTROL:
return "IONIC_CMD_Q_CONTROL";
case IONIC_CMD_Q_IDENTIFY:
return "IONIC_CMD_Q_IDENTIFY";
case IONIC_CMD_RDMA_RESET_LIF:
return "IONIC_CMD_RDMA_RESET_LIF";
case IONIC_CMD_RDMA_CREATE_EQ:
@ -126,8 +128,9 @@ ionic_adminq_check_err(struct ionic_admin_ctx *ctx, bool timeout)
const char *name;
const char *status;
name = ionic_opcode_to_str(ctx->cmd.cmd.opcode);
if (ctx->comp.comp.status || timeout) {
name = ionic_opcode_to_str(ctx->cmd.cmd.opcode);
status = ionic_error_to_str(ctx->comp.comp.status);
IONIC_PRINT(ERR, "%s (%d) failed: %s (%d)",
name,
@ -137,6 +140,8 @@ ionic_adminq_check_err(struct ionic_admin_ctx *ctx, bool timeout)
return -EIO;
}
IONIC_PRINT(DEBUG, "%s (%d) succeeded", name, ctx->cmd.cmd.opcode);
return 0;
}
@ -174,14 +179,13 @@ ionic_adminq_post_wait(struct ionic_lif *lif, struct ionic_admin_ctx *ctx)
bool done;
int err;
IONIC_PRINT(DEBUG, "Sending %s to the admin queue",
ionic_opcode_to_str(ctx->cmd.cmd.opcode));
IONIC_PRINT(DEBUG, "Sending %s (%d) via the admin queue",
ionic_opcode_to_str(ctx->cmd.cmd.opcode), ctx->cmd.cmd.opcode);
err = ionic_adminq_post(lif, ctx);
if (err) {
IONIC_PRINT(ERR, "Failure posting to the admin queue %d (%d)",
IONIC_PRINT(ERR, "Failure posting %d to the admin queue (%d)",
ctx->cmd.cmd.opcode, err);
return err;
}
@ -244,6 +248,7 @@ ionic_dev_cmd_wait_check(struct ionic_dev *idev, unsigned long max_wait)
if (!err)
err = ionic_dev_cmd_check_error(idev);
IONIC_PRINT(DEBUG, "dev_cmd returned %d", err);
return err;
}
@ -335,12 +340,12 @@ ionic_port_identify(struct ionic_adapter *adapter)
ioread32(&idev->dev_cmd->data[i]);
}
IONIC_PRINT(INFO, "speed %d ", ident->port.config.speed);
IONIC_PRINT(INFO, "mtu %d ", ident->port.config.mtu);
IONIC_PRINT(INFO, "state %d ", ident->port.config.state);
IONIC_PRINT(INFO, "an_enable %d ", ident->port.config.an_enable);
IONIC_PRINT(INFO, "fec_type %d ", ident->port.config.fec_type);
IONIC_PRINT(INFO, "pause_type %d ", ident->port.config.pause_type);
IONIC_PRINT(INFO, "speed %d", ident->port.config.speed);
IONIC_PRINT(INFO, "mtu %d", ident->port.config.mtu);
IONIC_PRINT(INFO, "state %d", ident->port.config.state);
IONIC_PRINT(INFO, "an_enable %d", ident->port.config.an_enable);
IONIC_PRINT(INFO, "fec_type %d", ident->port.config.fec_type);
IONIC_PRINT(INFO, "pause_type %d", ident->port.config.pause_type);
IONIC_PRINT(INFO, "loopback_mode %d",
ident->port.config.loopback_mode);
@ -381,8 +386,7 @@ ionic_port_init(struct ionic_adapter *adapter)
idev->port_info_sz = RTE_ALIGN(sizeof(*idev->port_info), PAGE_SIZE);
snprintf(z_name, sizeof(z_name), "%s_port_%s_info",
IONIC_DRV_NAME,
adapter->pci_dev->device.name);
IONIC_DRV_NAME, adapter->name);
idev->port_info_z = ionic_memzone_reserve(z_name, idev->port_info_sz,
SOCKET_ID_ANY);

41
drivers/net/ionic/ionic_rxtx.c
View File

@ -133,7 +133,7 @@ ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
{
struct ionic_qcq *txq;
IONIC_PRINT_CALL();
IONIC_PRINT(DEBUG, "Stopping TX queue %u", tx_queue_id);
txq = eth_dev->data->tx_queues[tx_queue_id];
@ -156,7 +156,7 @@ ionic_dev_tx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
int __rte_cold
ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id,
uint16_t nb_desc, uint32_t socket_id __rte_unused,
uint16_t nb_desc, uint32_t socket_id,
const struct rte_eth_txconf *tx_conf)
{
struct ionic_lif *lif = IONIC_ETH_DEV_TO_LIF(eth_dev);
@ -164,11 +164,6 @@ ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id,
uint64_t offloads;
int err;
IONIC_PRINT_CALL();
IONIC_PRINT(DEBUG, "Configuring TX queue %u with %u buffers",
tx_queue_id, nb_desc);
if (tx_queue_id >= lif->ntxqcqs) {
IONIC_PRINT(DEBUG, "Queue index %u not available "
"(max %u queues)",
@ -177,6 +172,9 @@ ionic_dev_tx_queue_setup(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id,
}
offloads = tx_conf->offloads | eth_dev->data->dev_conf.txmode.offloads;
IONIC_PRINT(DEBUG,
"Configuring skt %u TX queue %u with %u buffers, offloads %jx",
socket_id, tx_queue_id, nb_desc, offloads);
/* Validate number of receive descriptors */
if (!rte_is_power_of_2(nb_desc) || nb_desc < IONIC_MIN_RING_DESC)
@ -215,10 +213,11 @@ ionic_dev_tx_queue_start(struct rte_eth_dev *eth_dev, uint16_t tx_queue_id)
struct ionic_qcq *txq;
int err;
IONIC_PRINT_CALL();
txq = eth_dev->data->tx_queues[tx_queue_id];
IONIC_PRINT(DEBUG, "Starting TX queue %u, %u descs",
tx_queue_id, txq->q.num_descs);
err = ionic_lif_txq_init(txq);
if (err)
return err;
@ -642,7 +641,7 @@ int __rte_cold
ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
uint16_t rx_queue_id,
uint16_t nb_desc,
uint32_t socket_id __rte_unused,
uint32_t socket_id,
const struct rte_eth_rxconf *rx_conf,
struct rte_mempool *mp)
{
@ -651,11 +650,6 @@ ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
uint64_t offloads;
int err;
IONIC_PRINT_CALL();
IONIC_PRINT(DEBUG, "Configuring RX queue %u with %u buffers",
rx_queue_id, nb_desc);
if (rx_queue_id >= lif->nrxqcqs) {
IONIC_PRINT(ERR,
"Queue index %u not available (max %u queues)",
@ -664,13 +658,16 @@ ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
}
offloads = rx_conf->offloads | eth_dev->data->dev_conf.rxmode.offloads;
IONIC_PRINT(DEBUG,
"Configuring skt %u RX queue %u with %u buffers, offloads %jx",
socket_id, rx_queue_id, nb_desc, offloads);
/* Validate number of receive descriptors */
if (!rte_is_power_of_2(nb_desc) ||
nb_desc < IONIC_MIN_RING_DESC ||
nb_desc > IONIC_MAX_RING_DESC) {
IONIC_PRINT(ERR,
"Bad number of descriptors (%u) for queue %u (min: %u)",
"Bad descriptor count (%u) for queue %u (min: %u)",
nb_desc, rx_queue_id, IONIC_MIN_RING_DESC);
return -EINVAL; /* or use IONIC_DEFAULT_RING_DESC */
}
@ -687,7 +684,7 @@ ionic_dev_rx_queue_setup(struct rte_eth_dev *eth_dev,
err = ionic_rx_qcq_alloc(lif, rx_queue_id, nb_desc, &rxq);
if (err) {
IONIC_PRINT(ERR, "Queue allocation failure");
IONIC_PRINT(ERR, "Queue %d allocation failure", rx_queue_id);
return -EINVAL;
}
@ -959,13 +956,11 @@ ionic_dev_rx_queue_start(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
struct ionic_qcq *rxq;
int err;
IONIC_PRINT_CALL();
IONIC_PRINT(DEBUG, "Allocating RX queue buffers (size: %u)",
frame_size);
rxq = eth_dev->data->rx_queues[rx_queue_id];
IONIC_PRINT(DEBUG, "Starting RX queue %u, %u descs (size: %u)",
rx_queue_id, rxq->q.num_descs, frame_size);
err = ionic_lif_rxq_init(rxq);
if (err)
return err;
@ -1045,7 +1040,7 @@ ionic_dev_rx_queue_stop(struct rte_eth_dev *eth_dev, uint16_t rx_queue_id)
{
struct ionic_qcq *rxq;
IONIC_PRINT_CALL();
IONIC_PRINT(DEBUG, "Stopping RX queue %u", rx_queue_id);
rxq = eth_dev->data->rx_queues[rx_queue_id];