dma/hisilicon: introduce driver skeleton
Add the basic device probe and remove functions and initial documentation for new hisilicon DMA drivers. Signed-off-by: Chengwen Feng <fengchengwen@huawei.com>
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@ -1206,6 +1206,11 @@ M: Conor Walsh <conor.walsh@intel.com>
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F: drivers/dma/ioat/
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F: doc/guides/dmadevs/ioat.rst
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HiSilicon DMA
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M: Chengwen Feng <fengchengwen@huawei.com>
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F: drivers/dma/hisilicon/
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F: doc/guides/dmadevs/hisilicon.rst
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RegEx Drivers
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-------------
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22
doc/guides/dmadevs/hisilicon.rst
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22
doc/guides/dmadevs/hisilicon.rst
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.. SPDX-License-Identifier: BSD-3-Clause
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Copyright(c) 2021 HiSilicon Limited.
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HISILICON Kunpeng DMA Driver
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============================
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Kunpeng SoC has an internal DMA unit which can be used by application
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to accelerate data copies.
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The DMA PF function supports multiple DMA channels.
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Supported Kunpeng SoCs
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----------------------
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* Kunpeng 920
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Device Setup
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-------------
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Kunpeng DMA devices will need to be bound to a suitable DPDK-supported
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user-space IO driver such as ``vfio-pci`` in order to be used by DPDK.
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@ -11,5 +11,6 @@ an application through DMA API.
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:maxdepth: 2
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:numbered:
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hisilicon
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idxd
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ioat
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@ -75,6 +75,11 @@ New Features
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operations.
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* Added multi-process support.
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* **Added HiSilicon DMA driver.**
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The HiSilicon DMA driver provides device drivers for the Kunpeng's DMA devices.
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This device driver can be used through the generic dmadev API.
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* **Added IDXD dmadev driver implementation.**
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The IDXD dmadev driver provide device drivers for the Intel DSA devices.
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119
drivers/dma/hisilicon/hisi_dmadev.c
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119
drivers/dma/hisilicon/hisi_dmadev.c
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2021 HiSilicon Limited
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*/
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#include <inttypes.h>
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#include <string.h>
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#include <rte_bus_pci.h>
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#include <rte_eal.h>
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#include <rte_log.h>
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#include <rte_pci.h>
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#include <rte_dmadev_pmd.h>
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#include "hisi_dmadev.h"
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RTE_LOG_REGISTER_DEFAULT(hisi_dma_logtype, INFO);
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#define HISI_DMA_LOG(level, fmt, args...) \
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rte_log(RTE_LOG_ ## level, hisi_dma_logtype, \
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"%s(): " fmt "\n", __func__, ##args)
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#define HISI_DMA_LOG_RAW(hw, level, fmt, args...) \
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rte_log(RTE_LOG_ ## level, hisi_dma_logtype, \
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"%s %s(): " fmt "\n", (hw)->data->dev_name, \
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__func__, ##args)
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#define HISI_DMA_DEBUG(hw, fmt, args...) \
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HISI_DMA_LOG_RAW(hw, DEBUG, fmt, ## args)
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#define HISI_DMA_INFO(hw, fmt, args...) \
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HISI_DMA_LOG_RAW(hw, INFO, fmt, ## args)
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#define HISI_DMA_WARN(hw, fmt, args...) \
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HISI_DMA_LOG_RAW(hw, WARNING, fmt, ## args)
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#define HISI_DMA_ERR(hw, fmt, args...) \
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HISI_DMA_LOG_RAW(hw, ERR, fmt, ## args)
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static uint8_t
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hisi_dma_reg_layout(uint8_t revision)
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{
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if (revision == HISI_DMA_REVISION_HIP08B)
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return HISI_DMA_REG_LAYOUT_HIP08;
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else
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return HISI_DMA_REG_LAYOUT_INVALID;
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}
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static void
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hisi_dma_gen_pci_device_name(const struct rte_pci_device *pci_dev,
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char *name, size_t size)
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{
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memset(name, 0, size);
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(void)snprintf(name, size, "%x:%x.%x",
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pci_dev->addr.bus, pci_dev->addr.devid,
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pci_dev->addr.function);
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}
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static int
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hisi_dma_check_revision(struct rte_pci_device *pci_dev, const char *name,
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uint8_t *out_revision)
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{
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uint8_t revision;
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int ret;
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ret = rte_pci_read_config(pci_dev, &revision, 1,
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HISI_DMA_PCI_REVISION_ID_REG);
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if (ret != 1) {
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HISI_DMA_LOG(ERR, "%s read PCI revision failed!", name);
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return -EINVAL;
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}
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if (hisi_dma_reg_layout(revision) == HISI_DMA_REG_LAYOUT_INVALID) {
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HISI_DMA_LOG(ERR, "%s revision: 0x%x not supported!",
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name, revision);
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return -EINVAL;
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}
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*out_revision = revision;
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return 0;
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}
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static int
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hisi_dma_probe(struct rte_pci_driver *pci_drv __rte_unused,
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struct rte_pci_device *pci_dev)
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{
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char name[RTE_DEV_NAME_MAX_LEN] = { 0 };
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uint8_t revision;
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int ret;
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hisi_dma_gen_pci_device_name(pci_dev, name, sizeof(name));
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if (pci_dev->mem_resource[2].addr == NULL) {
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HISI_DMA_LOG(ERR, "%s BAR2 is NULL!\n", name);
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return -ENODEV;
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}
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ret = hisi_dma_check_revision(pci_dev, name, &revision);
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if (ret)
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return ret;
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HISI_DMA_LOG(DEBUG, "%s read PCI revision: 0x%x", name, revision);
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return ret;
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}
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static int
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hisi_dma_remove(struct rte_pci_device *pci_dev)
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{
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RTE_SET_USED(pci_dev);
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return 0;
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}
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static const struct rte_pci_id pci_id_hisi_dma_map[] = {
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{ RTE_PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, HISI_DMA_DEVICE_ID) },
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{ .vendor_id = 0, }, /* sentinel */
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};
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static struct rte_pci_driver hisi_dma_pmd_drv = {
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.id_table = pci_id_hisi_dma_map,
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.drv_flags = RTE_PCI_DRV_NEED_MAPPING,
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.probe = hisi_dma_probe,
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.remove = hisi_dma_remove,
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};
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RTE_PMD_REGISTER_PCI(dma_hisilicon, hisi_dma_pmd_drv);
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RTE_PMD_REGISTER_PCI_TABLE(dma_hisilicon, pci_id_hisi_dma_map);
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RTE_PMD_REGISTER_KMOD_DEP(dma_hisilicon, "vfio-pci");
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24
drivers/dma/hisilicon/hisi_dmadev.h
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24
drivers/dma/hisilicon/hisi_dmadev.h
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2021 HiSilicon Limited
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*/
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#ifndef HISI_DMADEV_H
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#define HISI_DMADEV_H
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#define PCI_VENDOR_ID_HUAWEI 0x19e5
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#define HISI_DMA_DEVICE_ID 0xA122
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#define HISI_DMA_PCI_REVISION_ID_REG 0x08
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#define HISI_DMA_REVISION_HIP08B 0x21
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/**
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* The HIP08B(HiSilicon IP08) and later Chip(e.g. HiSilicon IP09) are DMA iEPs,
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* they have the same pci device id but with different pci revision.
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* Unfortunately, they have different register layouts, so the layout
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* enumerations are defined.
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*/
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enum {
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HISI_DMA_REG_LAYOUT_INVALID = 0,
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HISI_DMA_REG_LAYOUT_HIP08
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};
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#endif /* HISI_DMADEV_H */
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19
drivers/dma/hisilicon/meson.build
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19
drivers/dma/hisilicon/meson.build
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# SPDX-License-Identifier: BSD-3-Clause
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# Copyright(c) 2021 HiSilicon Limited
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if not is_linux
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build = false
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reason = 'only supported on Linux'
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subdir_done()
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endif
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if (arch_subdir != 'x86' and arch_subdir != 'arm') or (not dpdk_conf.get('RTE_ARCH_64'))
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build = false
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reason = 'only supported on x86_64 and aarch64'
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subdir_done()
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endif
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deps += ['bus_pci', 'dmadev']
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sources = files(
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'hisi_dmadev.c',
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)
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3
drivers/dma/hisilicon/version.map
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3
drivers/dma/hisilicon/version.map
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DPDK_22 {
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local: *;
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};
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# Copyright 2021 HiSilicon Limited
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drivers = [
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'hisilicon',
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'idxd',
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'ioat',
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'skeleton',
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