ipsec: implement SA data-path API
Provide implementation for rte_ipsec_pkt_crypto_prepare() and rte_ipsec_pkt_process(). Current implementation: - supports ESP protocol tunnel mode. - supports ESP protocol transport mode. - supports ESN and replay window. - supports algorithms: AES-CBC, AES-GCM, HMAC-SHA1, NULL. - covers all currently defined security session types: - RTE_SECURITY_ACTION_TYPE_NONE - RTE_SECURITY_ACTION_TYPE_INLINE_CRYPTO - RTE_SECURITY_ACTION_TYPE_INLINE_PROTOCOL - RTE_SECURITY_ACTION_TYPE_LOOKASIDE_PROTOCOL For first two types SQN check/update is done by SW (inside the library). For last two type it is HW/PMD responsibility. Signed-off-by: Mohammad Abdul Awal <mohammad.abdul.awal@intel.com> Signed-off-by: Konstantin Ananyev <konstantin.ananyev@intel.com> Acked-by: Declan Doherty <declan.doherty@intel.com> Acked-by: Akhil Goyal <akhil.goyal@nxp.com>
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123
lib/librte_ipsec/crypto.h
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123
lib/librte_ipsec/crypto.h
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Intel Corporation
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*/
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#ifndef _CRYPTO_H_
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#define _CRYPTO_H_
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/**
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* @file crypto.h
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* Contains crypto specific functions/structures/macros used internally
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* by ipsec library.
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*/
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/*
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* AES-GCM devices have some specific requirements for IV and AAD formats.
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* Ideally that to be done by the driver itself.
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*/
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struct aead_gcm_iv {
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uint32_t salt;
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uint64_t iv;
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uint32_t cnt;
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} __attribute__((packed));
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struct aead_gcm_aad {
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uint32_t spi;
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/*
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* RFC 4106, section 5:
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* Two formats of the AAD are defined:
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* one for 32-bit sequence numbers, and one for 64-bit ESN.
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*/
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union {
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uint32_t u32[2];
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uint64_t u64;
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} sqn;
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uint32_t align0; /* align to 16B boundary */
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} __attribute__((packed));
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struct gcm_esph_iv {
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struct esp_hdr esph;
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uint64_t iv;
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} __attribute__((packed));
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static inline void
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aead_gcm_iv_fill(struct aead_gcm_iv *gcm, uint64_t iv, uint32_t salt)
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{
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gcm->salt = salt;
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gcm->iv = iv;
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gcm->cnt = rte_cpu_to_be_32(1);
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}
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/*
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* RFC 4106, 5 AAD Construction
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* spi and sqn should already be converted into network byte order.
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* Make sure that not used bytes are zeroed.
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*/
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static inline void
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aead_gcm_aad_fill(struct aead_gcm_aad *aad, rte_be32_t spi, rte_be64_t sqn,
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int esn)
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{
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aad->spi = spi;
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if (esn)
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aad->sqn.u64 = sqn;
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else {
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aad->sqn.u32[0] = sqn_low32(sqn);
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aad->sqn.u32[1] = 0;
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}
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aad->align0 = 0;
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}
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static inline void
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gen_iv(uint64_t iv[IPSEC_MAX_IV_QWORD], rte_be64_t sqn)
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{
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iv[0] = sqn;
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iv[1] = 0;
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}
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/*
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* from RFC 4303 3.3.2.1.4:
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* If the ESN option is enabled for the SA, the high-order 32
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* bits of the sequence number are appended after the Next Header field
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* for purposes of this computation, but are not transmitted.
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*/
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/*
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* Helper function that moves ICV by 4B below, and inserts SQN.hibits.
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* icv parameter points to the new start of ICV.
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*/
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static inline void
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insert_sqh(uint32_t sqh, void *picv, uint32_t icv_len)
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{
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uint32_t *icv;
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int32_t i;
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RTE_ASSERT(icv_len % sizeof(uint32_t) == 0);
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icv = picv;
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icv_len = icv_len / sizeof(uint32_t);
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for (i = icv_len; i-- != 0; icv[i] = icv[i - 1])
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;
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icv[i] = sqh;
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}
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/*
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* Helper function that moves ICV by 4B up, and removes SQN.hibits.
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* icv parameter points to the new start of ICV.
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*/
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static inline void
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remove_sqh(void *picv, uint32_t icv_len)
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{
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uint32_t i, *icv;
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RTE_ASSERT(icv_len % sizeof(uint32_t) == 0);
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icv = picv;
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icv_len = icv_len / sizeof(uint32_t);
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for (i = 0; i != icv_len; i++)
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icv[i] = icv[i + 1];
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}
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#endif /* _CRYPTO_H_ */
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84
lib/librte_ipsec/iph.h
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84
lib/librte_ipsec/iph.h
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Intel Corporation
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*/
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#ifndef _IPH_H_
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#define _IPH_H_
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/**
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* @file iph.h
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* Contains functions/structures/macros to manipulate IPv4/IPv6 headers
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* used internally by ipsec library.
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*/
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/*
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* Move preceding (L3) headers down to remove ESP header and IV.
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*/
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static inline void
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remove_esph(char *np, char *op, uint32_t hlen)
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{
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uint32_t i;
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for (i = hlen; i-- != 0; np[i] = op[i])
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;
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}
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/*
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* Move preceding (L3) headers up to free space for ESP header and IV.
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*/
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static inline void
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insert_esph(char *np, char *op, uint32_t hlen)
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{
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uint32_t i;
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for (i = 0; i != hlen; i++)
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np[i] = op[i];
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}
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/* update original ip header fields for transport case */
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static inline int
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update_trs_l3hdr(const struct rte_ipsec_sa *sa, void *p, uint32_t plen,
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uint32_t l2len, uint32_t l3len, uint8_t proto)
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{
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struct ipv4_hdr *v4h;
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struct ipv6_hdr *v6h;
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int32_t rc;
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if ((sa->type & RTE_IPSEC_SATP_IPV_MASK) == RTE_IPSEC_SATP_IPV4) {
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v4h = p;
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rc = v4h->next_proto_id;
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v4h->next_proto_id = proto;
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v4h->total_length = rte_cpu_to_be_16(plen - l2len);
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} else if (l3len == sizeof(*v6h)) {
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v6h = p;
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rc = v6h->proto;
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v6h->proto = proto;
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v6h->payload_len = rte_cpu_to_be_16(plen - l2len -
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sizeof(*v6h));
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/* need to add support for IPv6 with options */
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} else
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rc = -ENOTSUP;
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return rc;
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}
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/* update original and new ip header fields for tunnel case */
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static inline void
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update_tun_l3hdr(const struct rte_ipsec_sa *sa, void *p, uint32_t plen,
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uint32_t l2len, rte_be16_t pid)
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{
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struct ipv4_hdr *v4h;
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struct ipv6_hdr *v6h;
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if (sa->type & RTE_IPSEC_SATP_MODE_TUNLV4) {
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v4h = p;
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v4h->packet_id = pid;
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v4h->total_length = rte_cpu_to_be_16(plen - l2len);
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} else {
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v6h = p;
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v6h->payload_len = rte_cpu_to_be_16(plen - l2len -
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sizeof(*v6h));
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}
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}
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#endif /* _IPH_H_ */
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#define IS_ESN(sa) ((sa)->sqn_mask == UINT64_MAX)
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/*
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* gets SQN.hi32 bits, SQN supposed to be in network byte order.
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*/
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static inline rte_be32_t
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sqn_hi32(rte_be64_t sqn)
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{
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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return (sqn >> 32);
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#else
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return sqn;
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#endif
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}
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/*
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* gets SQN.low32 bits, SQN supposed to be in network byte order.
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*/
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static inline rte_be32_t
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sqn_low32(rte_be64_t sqn)
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{
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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return sqn;
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#else
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return (sqn >> 32);
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#endif
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}
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/*
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* gets SQN.low16 bits, SQN supposed to be in network byte order.
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*/
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static inline rte_be16_t
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sqn_low16(rte_be64_t sqn)
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{
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#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN
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return sqn;
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#else
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return (sqn >> 48);
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#endif
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}
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/*
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* for given size, calculate required number of buckets.
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*/
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@ -30,6 +69,153 @@ replay_num_bucket(uint32_t wsz)
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return nb;
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}
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/*
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* According to RFC4303 A2.1, determine the high-order bit of sequence number.
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* use 32bit arithmetic inside, return uint64_t.
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*/
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static inline uint64_t
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reconstruct_esn(uint64_t t, uint32_t sqn, uint32_t w)
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{
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uint32_t th, tl, bl;
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tl = t;
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th = t >> 32;
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bl = tl - w + 1;
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/* case A: window is within one sequence number subspace */
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if (tl >= (w - 1))
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th += (sqn < bl);
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/* case B: window spans two sequence number subspaces */
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else if (th != 0)
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th -= (sqn >= bl);
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/* return constructed sequence with proper high-order bits */
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return (uint64_t)th << 32 | sqn;
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}
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/**
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* Perform the replay checking.
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*
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* struct rte_ipsec_sa contains the window and window related parameters,
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* such as the window size, bitmask, and the last acknowledged sequence number.
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*
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* Based on RFC 6479.
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* Blocks are 64 bits unsigned integers
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*/
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static inline int32_t
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esn_inb_check_sqn(const struct replay_sqn *rsn, const struct rte_ipsec_sa *sa,
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uint64_t sqn)
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{
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uint32_t bit, bucket;
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/* replay not enabled */
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if (sa->replay.win_sz == 0)
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return 0;
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/* seq is larger than lastseq */
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if (sqn > rsn->sqn)
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return 0;
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/* seq is outside window */
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if (sqn == 0 || sqn + sa->replay.win_sz < rsn->sqn)
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return -EINVAL;
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/* seq is inside the window */
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bit = sqn & WINDOW_BIT_LOC_MASK;
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bucket = (sqn >> WINDOW_BUCKET_BITS) & sa->replay.bucket_index_mask;
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/* already seen packet */
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if (rsn->window[bucket] & ((uint64_t)1 << bit))
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return -EINVAL;
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return 0;
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}
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/**
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* For outbound SA perform the sequence number update.
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*/
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static inline uint64_t
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esn_outb_update_sqn(struct rte_ipsec_sa *sa, uint32_t *num)
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{
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uint64_t n, s, sqn;
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n = *num;
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sqn = sa->sqn.outb + n;
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sa->sqn.outb = sqn;
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/* overflow */
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if (sqn > sa->sqn_mask) {
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s = sqn - sa->sqn_mask;
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*num = (s < n) ? n - s : 0;
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}
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return sqn - n;
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}
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/**
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* For inbound SA perform the sequence number and replay window update.
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*/
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static inline int32_t
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esn_inb_update_sqn(struct replay_sqn *rsn, const struct rte_ipsec_sa *sa,
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uint64_t sqn)
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{
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uint32_t bit, bucket, last_bucket, new_bucket, diff, i;
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/* replay not enabled */
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if (sa->replay.win_sz == 0)
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return 0;
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/* handle ESN */
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if (IS_ESN(sa))
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sqn = reconstruct_esn(rsn->sqn, sqn, sa->replay.win_sz);
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/* seq is outside window*/
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if (sqn == 0 || sqn + sa->replay.win_sz < rsn->sqn)
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return -EINVAL;
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/* update the bit */
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bucket = (sqn >> WINDOW_BUCKET_BITS);
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/* check if the seq is within the range */
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if (sqn > rsn->sqn) {
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last_bucket = rsn->sqn >> WINDOW_BUCKET_BITS;
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diff = bucket - last_bucket;
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/* seq is way after the range of WINDOW_SIZE */
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if (diff > sa->replay.nb_bucket)
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diff = sa->replay.nb_bucket;
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for (i = 0; i != diff; i++) {
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new_bucket = (i + last_bucket + 1) &
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sa->replay.bucket_index_mask;
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rsn->window[new_bucket] = 0;
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}
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rsn->sqn = sqn;
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}
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bucket &= sa->replay.bucket_index_mask;
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bit = (uint64_t)1 << (sqn & WINDOW_BIT_LOC_MASK);
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/* already seen packet */
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if (rsn->window[bucket] & bit)
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return -EINVAL;
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rsn->window[bucket] |= bit;
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return 0;
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}
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/**
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* To achieve ability to do multiple readers single writer for
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* SA replay window information and sequence number (RSN)
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* basic RCU schema is used:
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* SA have 2 copies of RSN (one for readers, another for writers).
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* Each RSN contains a rwlock that has to be grabbed (for read/write)
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* to avoid races between readers and writer.
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* Writer is responsible to make a copy or reader RSN, update it
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* and mark newly updated RSN as readers one.
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* That approach is intended to minimize contention and cache sharing
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* between writer and readers.
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*/
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/**
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* Based on number of buckets calculated required size for the
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* structure that holds replay window and sequence number (RSN) information.
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45
lib/librte_ipsec/pad.h
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45
lib/librte_ipsec/pad.h
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2018 Intel Corporation
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*/
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#ifndef _PAD_H_
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#define _PAD_H_
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#define IPSEC_MAX_PAD_SIZE UINT8_MAX
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static const uint8_t esp_pad_bytes[IPSEC_MAX_PAD_SIZE] = {
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1, 2, 3, 4, 5, 6, 7, 8,
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9, 10, 11, 12, 13, 14, 15, 16,
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17, 18, 19, 20, 21, 22, 23, 24,
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25, 26, 27, 28, 29, 30, 31, 32,
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33, 34, 35, 36, 37, 38, 39, 40,
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41, 42, 43, 44, 45, 46, 47, 48,
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49, 50, 51, 52, 53, 54, 55, 56,
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57, 58, 59, 60, 61, 62, 63, 64,
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65, 66, 67, 68, 69, 70, 71, 72,
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73, 74, 75, 76, 77, 78, 79, 80,
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81, 82, 83, 84, 85, 86, 87, 88,
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89, 90, 91, 92, 93, 94, 95, 96,
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97, 98, 99, 100, 101, 102, 103, 104,
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105, 106, 107, 108, 109, 110, 111, 112,
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113, 114, 115, 116, 117, 118, 119, 120,
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121, 122, 123, 124, 125, 126, 127, 128,
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129, 130, 131, 132, 133, 134, 135, 136,
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137, 138, 139, 140, 141, 142, 143, 144,
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145, 146, 147, 148, 149, 150, 151, 152,
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153, 154, 155, 156, 157, 158, 159, 160,
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161, 162, 163, 164, 165, 166, 167, 168,
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169, 170, 171, 172, 173, 174, 175, 176,
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177, 178, 179, 180, 181, 182, 183, 184,
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185, 186, 187, 188, 189, 190, 191, 192,
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193, 194, 195, 196, 197, 198, 199, 200,
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201, 202, 203, 204, 205, 206, 207, 208,
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209, 210, 211, 212, 213, 214, 215, 216,
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217, 218, 219, 220, 221, 222, 223, 224,
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225, 226, 227, 228, 229, 230, 231, 232,
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233, 234, 235, 236, 237, 238, 239, 240,
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241, 242, 243, 244, 245, 246, 247, 248,
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249, 250, 251, 252, 253, 254, 255,
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};
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#endif /* _PAD_H_ */
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