net/igc: implement device base operations
Bellow ops are implemented: dev_configure dev_start dev_stop dev_close dev_reset dev_set_link_up dev_set_link_down link_update fw_version_get dev_led_on dev_led_off Signed-off-by: Alvin Zhang <alvinx.zhang@intel.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Alvin Zhang
Ferruh Yigit
parent
8cb7c57d9b
commit
4f09bc55ac
@ -3,6 +3,11 @@
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; Refer to default.ini for the full list of available PMD features.
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;
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[Features]
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Speed capabilities = Y
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Link status = Y
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Link status event = Y
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FW version = Y
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LED = Y
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Linux UIO = Y
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Linux VFIO = Y
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x86-64 = Y
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@ -3,6 +3,7 @@
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*/
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#include <stdint.h>
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#include <string.h>
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#include <rte_pci.h>
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#include <rte_bus_pci.h>
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@ -15,7 +16,34 @@
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#define IGC_INTEL_VENDOR_ID 0x8086
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/*
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* The overhead from MTU to max frame size.
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* Considering VLAN so tag needs to be counted.
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*/
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#define IGC_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + \
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RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE)
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#define IGC_FC_PAUSE_TIME 0x0680
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#define IGC_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
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#define IGC_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
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#define IGC_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
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#define IGC_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
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#define IGC_MSIX_OTHER_INTR_VEC 0 /* MSI-X other interrupt vector */
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#define IGC_FLAG_NEED_LINK_UPDATE (1u << 0) /* need update link */
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#define IGC_DEFAULT_RX_FREE_THRESH 32
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#define IGC_DEFAULT_RX_PTHRESH 8
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#define IGC_DEFAULT_RX_HTHRESH 8
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#define IGC_DEFAULT_RX_WTHRESH 4
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#define IGC_DEFAULT_TX_PTHRESH 8
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#define IGC_DEFAULT_TX_HTHRESH 1
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#define IGC_DEFAULT_TX_WTHRESH 16
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/* MSI-X other interrupt vector */
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#define IGC_MSIX_OTHER_INTR_VEC 0
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static const struct rte_pci_id pci_id_igc_map[] = {
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{ RTE_PCI_DEVICE(IGC_INTEL_VENDOR_ID, IGC_DEV_ID_I225_LM) },
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@ -29,12 +57,20 @@ static int eth_igc_configure(struct rte_eth_dev *dev);
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static int eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete);
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static void eth_igc_stop(struct rte_eth_dev *dev);
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static int eth_igc_start(struct rte_eth_dev *dev);
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static int eth_igc_set_link_up(struct rte_eth_dev *dev);
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static int eth_igc_set_link_down(struct rte_eth_dev *dev);
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static void eth_igc_close(struct rte_eth_dev *dev);
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static int eth_igc_reset(struct rte_eth_dev *dev);
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static int eth_igc_promiscuous_enable(struct rte_eth_dev *dev);
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static int eth_igc_promiscuous_disable(struct rte_eth_dev *dev);
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static int eth_igc_fw_version_get(struct rte_eth_dev *dev,
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char *fw_version, size_t fw_size);
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static int eth_igc_infos_get(struct rte_eth_dev *dev,
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struct rte_eth_dev_info *dev_info);
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static int eth_igc_led_on(struct rte_eth_dev *dev);
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static int eth_igc_led_off(struct rte_eth_dev *dev);
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static void eth_igc_tx_queue_release(void *txq);
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static void eth_igc_rx_queue_release(void *rxq);
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static int
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eth_igc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
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uint16_t nb_rx_desc, unsigned int socket_id,
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@ -52,35 +88,394 @@ static const struct eth_dev_ops eth_igc_ops = {
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.dev_start = eth_igc_start,
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.dev_close = eth_igc_close,
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.dev_reset = eth_igc_reset,
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.dev_set_link_up = eth_igc_set_link_up,
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.dev_set_link_down = eth_igc_set_link_down,
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.promiscuous_enable = eth_igc_promiscuous_enable,
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.promiscuous_disable = eth_igc_promiscuous_disable,
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.fw_version_get = eth_igc_fw_version_get,
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.dev_infos_get = eth_igc_infos_get,
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.dev_led_on = eth_igc_led_on,
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.dev_led_off = eth_igc_led_off,
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.rx_queue_setup = eth_igc_rx_queue_setup,
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.rx_queue_release = eth_igc_rx_queue_release,
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.tx_queue_setup = eth_igc_tx_queue_setup,
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.tx_queue_release = eth_igc_tx_queue_release,
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};
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/*
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* multiple queue mode checking
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*/
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static int
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igc_check_mq_mode(struct rte_eth_dev *dev)
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{
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enum rte_eth_rx_mq_mode rx_mq_mode = dev->data->dev_conf.rxmode.mq_mode;
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enum rte_eth_tx_mq_mode tx_mq_mode = dev->data->dev_conf.txmode.mq_mode;
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if (RTE_ETH_DEV_SRIOV(dev).active != 0) {
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PMD_INIT_LOG(ERR, "SRIOV is not supported.");
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return -EINVAL;
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}
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if (rx_mq_mode != ETH_MQ_RX_NONE &&
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rx_mq_mode != ETH_MQ_RX_RSS) {
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/* RSS together with VMDq not supported*/
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PMD_INIT_LOG(ERR, "RX mode %d is not supported.",
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rx_mq_mode);
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return -EINVAL;
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}
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/* To no break software that set invalid mode, only display
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* warning if invalid mode is used.
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*/
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if (tx_mq_mode != ETH_MQ_TX_NONE)
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PMD_INIT_LOG(WARNING,
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"TX mode %d is not supported. Due to meaningless in this driver, just ignore",
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tx_mq_mode);
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return 0;
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}
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static int
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eth_igc_configure(struct rte_eth_dev *dev)
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{
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struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
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int ret;
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PMD_INIT_FUNC_TRACE();
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RTE_SET_USED(dev);
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ret = igc_check_mq_mode(dev);
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if (ret != 0)
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return ret;
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intr->flags |= IGC_FLAG_NEED_LINK_UPDATE;
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return 0;
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}
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static int
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eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete)
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eth_igc_set_link_up(struct rte_eth_dev *dev)
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{
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PMD_INIT_FUNC_TRACE();
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RTE_SET_USED(dev);
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RTE_SET_USED(wait_to_complete);
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struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
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if (hw->phy.media_type == igc_media_type_copper)
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igc_power_up_phy(hw);
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else
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igc_power_up_fiber_serdes_link(hw);
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return 0;
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}
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static int
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eth_igc_set_link_down(struct rte_eth_dev *dev)
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{
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struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
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if (hw->phy.media_type == igc_media_type_copper)
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igc_power_down_phy(hw);
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else
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igc_shutdown_fiber_serdes_link(hw);
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return 0;
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}
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/*
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* disable other interrupt
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*/
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static void
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igc_intr_other_disable(struct rte_eth_dev *dev)
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{
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struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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if (rte_intr_allow_others(intr_handle) &&
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dev->data->dev_conf.intr_conf.lsc) {
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IGC_WRITE_REG(hw, IGC_EIMC, 1u << IGC_MSIX_OTHER_INTR_VEC);
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}
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IGC_WRITE_REG(hw, IGC_IMC, ~0);
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IGC_WRITE_FLUSH(hw);
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}
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/*
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* enable other interrupt
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*/
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static inline void
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igc_intr_other_enable(struct rte_eth_dev *dev)
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{
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struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
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struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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if (rte_intr_allow_others(intr_handle) &&
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dev->data->dev_conf.intr_conf.lsc) {
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IGC_WRITE_REG(hw, IGC_EIMS, 1u << IGC_MSIX_OTHER_INTR_VEC);
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}
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IGC_WRITE_REG(hw, IGC_IMS, intr->mask);
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IGC_WRITE_FLUSH(hw);
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}
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/*
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* It reads ICR and gets interrupt causes, check it and set a bit flag
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* to update link status.
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*/
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static void
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eth_igc_interrupt_get_status(struct rte_eth_dev *dev)
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{
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uint32_t icr;
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struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
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struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
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/* read-on-clear nic registers here */
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icr = IGC_READ_REG(hw, IGC_ICR);
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intr->flags = 0;
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if (icr & IGC_ICR_LSC)
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intr->flags |= IGC_FLAG_NEED_LINK_UPDATE;
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}
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/* return 0 means link status changed, -1 means not changed */
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static int
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eth_igc_link_update(struct rte_eth_dev *dev, int wait_to_complete)
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{
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struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
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struct rte_eth_link link;
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int link_check, count;
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link_check = 0;
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hw->mac.get_link_status = 1;
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/* possible wait-to-complete in up to 9 seconds */
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for (count = 0; count < IGC_LINK_UPDATE_CHECK_TIMEOUT; count++) {
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/* Read the real link status */
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switch (hw->phy.media_type) {
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case igc_media_type_copper:
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/* Do the work to read phy */
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igc_check_for_link(hw);
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link_check = !hw->mac.get_link_status;
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break;
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case igc_media_type_fiber:
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igc_check_for_link(hw);
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link_check = (IGC_READ_REG(hw, IGC_STATUS) &
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IGC_STATUS_LU);
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break;
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case igc_media_type_internal_serdes:
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igc_check_for_link(hw);
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link_check = hw->mac.serdes_has_link;
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break;
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default:
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break;
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}
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if (link_check || wait_to_complete == 0)
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break;
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rte_delay_ms(IGC_LINK_UPDATE_CHECK_INTERVAL);
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}
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memset(&link, 0, sizeof(link));
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/* Now we check if a transition has happened */
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if (link_check) {
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uint16_t duplex, speed;
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hw->mac.ops.get_link_up_info(hw, &speed, &duplex);
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link.link_duplex = (duplex == FULL_DUPLEX) ?
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ETH_LINK_FULL_DUPLEX :
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ETH_LINK_HALF_DUPLEX;
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link.link_speed = speed;
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link.link_status = ETH_LINK_UP;
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link.link_autoneg = !(dev->data->dev_conf.link_speeds &
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ETH_LINK_SPEED_FIXED);
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if (speed == SPEED_2500) {
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uint32_t tipg = IGC_READ_REG(hw, IGC_TIPG);
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if ((tipg & IGC_TIPG_IPGT_MASK) != 0x0b) {
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tipg &= ~IGC_TIPG_IPGT_MASK;
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tipg |= 0x0b;
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IGC_WRITE_REG(hw, IGC_TIPG, tipg);
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}
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}
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} else {
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link.link_speed = 0;
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link.link_duplex = ETH_LINK_HALF_DUPLEX;
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link.link_status = ETH_LINK_DOWN;
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link.link_autoneg = ETH_LINK_FIXED;
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}
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return rte_eth_linkstatus_set(dev, &link);
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}
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/*
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* It executes link_update after knowing an interrupt is present.
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*/
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static void
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eth_igc_interrupt_action(struct rte_eth_dev *dev)
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{
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struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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struct rte_eth_link link;
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int ret;
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if (intr->flags & IGC_FLAG_NEED_LINK_UPDATE) {
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intr->flags &= ~IGC_FLAG_NEED_LINK_UPDATE;
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/* set get_link_status to check register later */
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ret = eth_igc_link_update(dev, 0);
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/* check if link has changed */
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if (ret < 0)
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return;
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rte_eth_linkstatus_get(dev, &link);
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if (link.link_status)
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PMD_DRV_LOG(INFO,
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" Port %d: Link Up - speed %u Mbps - %s",
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dev->data->port_id,
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(unsigned int)link.link_speed,
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link.link_duplex == ETH_LINK_FULL_DUPLEX ?
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"full-duplex" : "half-duplex");
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else
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PMD_DRV_LOG(INFO, " Port %d: Link Down",
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dev->data->port_id);
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PMD_DRV_LOG(DEBUG, "PCI Address: " PCI_PRI_FMT,
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pci_dev->addr.domain,
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pci_dev->addr.bus,
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pci_dev->addr.devid,
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pci_dev->addr.function);
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_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC,
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NULL);
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}
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}
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/*
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* Interrupt handler which shall be registered at first.
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*
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* @handle
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* Pointer to interrupt handle.
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* @param
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* The address of parameter (struct rte_eth_dev *) registered before.
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*/
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static void
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eth_igc_interrupt_handler(void *param)
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{
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struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
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eth_igc_interrupt_get_status(dev);
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eth_igc_interrupt_action(dev);
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}
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/*
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* This routine disables all traffic on the adapter by issuing a
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* global reset on the MAC.
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*/
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static void
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eth_igc_stop(struct rte_eth_dev *dev)
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{
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PMD_INIT_FUNC_TRACE();
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RTE_SET_USED(dev);
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struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
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struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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struct rte_eth_link link;
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adapter->stopped = 1;
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/* disable all MSI-X interrupts */
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IGC_WRITE_REG(hw, IGC_EIMC, 0x1f);
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IGC_WRITE_FLUSH(hw);
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/* clear all MSI-X interrupts */
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IGC_WRITE_REG(hw, IGC_EICR, 0x1f);
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igc_intr_other_disable(dev);
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/* disable intr eventfd mapping */
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rte_intr_disable(intr_handle);
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igc_reset_hw(hw);
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/* disable all wake up */
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IGC_WRITE_REG(hw, IGC_WUC, 0);
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/* Set bit for Go Link disconnect */
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igc_read_reg_check_set_bits(hw, IGC_82580_PHY_POWER_MGMT,
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IGC_82580_PM_GO_LINKD);
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/* Power down the phy. Needed to make the link go Down */
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eth_igc_set_link_down(dev);
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/* clear the recorded link status */
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memset(&link, 0, sizeof(link));
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rte_eth_linkstatus_set(dev, &link);
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if (!rte_intr_allow_others(intr_handle))
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/* resume to the default handler */
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rte_intr_callback_register(intr_handle,
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eth_igc_interrupt_handler,
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(void *)dev);
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/* Clean datapath event and queue/vec mapping */
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rte_intr_efd_disable(intr_handle);
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}
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/* Sets up the hardware to generate MSI-X interrupts properly
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* @hw
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* board private structure
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*/
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static void
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igc_configure_msix_intr(struct rte_eth_dev *dev)
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{
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struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
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struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
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struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
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uint32_t intr_mask;
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/* won't configure msix register if no mapping is done
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* between intr vector and event fd
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*/
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if (!rte_intr_dp_is_en(intr_handle) ||
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!dev->data->dev_conf.intr_conf.lsc)
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return;
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||||
|
||||
/* turn on MSI-X capability first */
|
||||
IGC_WRITE_REG(hw, IGC_GPIE, IGC_GPIE_MSIX_MODE |
|
||||
IGC_GPIE_PBA | IGC_GPIE_EIAME |
|
||||
IGC_GPIE_NSICR);
|
||||
|
||||
intr_mask = (1u << IGC_MSIX_OTHER_INTR_VEC);
|
||||
|
||||
/* enable msix auto-clear */
|
||||
igc_read_reg_check_set_bits(hw, IGC_EIAC, intr_mask);
|
||||
|
||||
/* set other cause interrupt vector */
|
||||
igc_read_reg_check_set_bits(hw, IGC_IVAR_MISC,
|
||||
(uint32_t)(IGC_MSIX_OTHER_INTR_VEC | IGC_IVAR_VALID) << 8);
|
||||
|
||||
/* enable auto-mask */
|
||||
igc_read_reg_check_set_bits(hw, IGC_EIAM, intr_mask);
|
||||
|
||||
IGC_WRITE_FLUSH(hw);
|
||||
}
|
||||
|
||||
/**
|
||||
* It enables the interrupt mask and then enable the interrupt.
|
||||
*
|
||||
* @dev
|
||||
* Pointer to struct rte_eth_dev.
|
||||
* @on
|
||||
* Enable or Disable
|
||||
*/
|
||||
static void
|
||||
igc_lsc_interrupt_setup(struct rte_eth_dev *dev, uint8_t on)
|
||||
{
|
||||
struct igc_interrupt *intr = IGC_DEV_PRIVATE_INTR(dev);
|
||||
|
||||
if (on)
|
||||
intr->mask |= IGC_ICR_LSC;
|
||||
else
|
||||
intr->mask &= ~IGC_ICR_LSC;
|
||||
}
|
||||
|
||||
/*
|
||||
@ -170,9 +565,134 @@ igc_hardware_init(struct igc_hw *hw)
|
||||
static int
|
||||
eth_igc_start(struct rte_eth_dev *dev)
|
||||
{
|
||||
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
|
||||
struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
|
||||
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
|
||||
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
|
||||
uint32_t *speeds;
|
||||
int num_speeds;
|
||||
bool autoneg;
|
||||
|
||||
PMD_INIT_FUNC_TRACE();
|
||||
RTE_SET_USED(dev);
|
||||
|
||||
/* disable all MSI-X interrupts */
|
||||
IGC_WRITE_REG(hw, IGC_EIMC, 0x1f);
|
||||
IGC_WRITE_FLUSH(hw);
|
||||
|
||||
/* clear all MSI-X interrupts */
|
||||
IGC_WRITE_REG(hw, IGC_EICR, 0x1f);
|
||||
|
||||
/* disable uio/vfio intr/eventfd mapping */
|
||||
if (!adapter->stopped)
|
||||
rte_intr_disable(intr_handle);
|
||||
|
||||
/* Power up the phy. Needed to make the link go Up */
|
||||
eth_igc_set_link_up(dev);
|
||||
|
||||
/* Put the address into the Receive Address Array */
|
||||
igc_rar_set(hw, hw->mac.addr, 0);
|
||||
|
||||
/* Initialize the hardware */
|
||||
if (igc_hardware_init(hw)) {
|
||||
PMD_DRV_LOG(ERR, "Unable to initialize the hardware");
|
||||
return -EIO;
|
||||
}
|
||||
adapter->stopped = 0;
|
||||
|
||||
/* confiugre msix for rx interrupt */
|
||||
igc_configure_msix_intr(dev);
|
||||
|
||||
igc_clear_hw_cntrs_base_generic(hw);
|
||||
|
||||
/* Setup link speed and duplex */
|
||||
speeds = &dev->data->dev_conf.link_speeds;
|
||||
if (*speeds == ETH_LINK_SPEED_AUTONEG) {
|
||||
hw->phy.autoneg_advertised = IGC_ALL_SPEED_DUPLEX_2500;
|
||||
hw->mac.autoneg = 1;
|
||||
} else {
|
||||
num_speeds = 0;
|
||||
autoneg = (*speeds & ETH_LINK_SPEED_FIXED) == 0;
|
||||
|
||||
/* Reset */
|
||||
hw->phy.autoneg_advertised = 0;
|
||||
|
||||
if (*speeds & ~(ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
|
||||
ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
|
||||
ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G |
|
||||
ETH_LINK_SPEED_FIXED)) {
|
||||
num_speeds = -1;
|
||||
goto error_invalid_config;
|
||||
}
|
||||
if (*speeds & ETH_LINK_SPEED_10M_HD) {
|
||||
hw->phy.autoneg_advertised |= ADVERTISE_10_HALF;
|
||||
num_speeds++;
|
||||
}
|
||||
if (*speeds & ETH_LINK_SPEED_10M) {
|
||||
hw->phy.autoneg_advertised |= ADVERTISE_10_FULL;
|
||||
num_speeds++;
|
||||
}
|
||||
if (*speeds & ETH_LINK_SPEED_100M_HD) {
|
||||
hw->phy.autoneg_advertised |= ADVERTISE_100_HALF;
|
||||
num_speeds++;
|
||||
}
|
||||
if (*speeds & ETH_LINK_SPEED_100M) {
|
||||
hw->phy.autoneg_advertised |= ADVERTISE_100_FULL;
|
||||
num_speeds++;
|
||||
}
|
||||
if (*speeds & ETH_LINK_SPEED_1G) {
|
||||
hw->phy.autoneg_advertised |= ADVERTISE_1000_FULL;
|
||||
num_speeds++;
|
||||
}
|
||||
if (*speeds & ETH_LINK_SPEED_2_5G) {
|
||||
hw->phy.autoneg_advertised |= ADVERTISE_2500_FULL;
|
||||
num_speeds++;
|
||||
}
|
||||
if (num_speeds == 0 || (!autoneg && num_speeds > 1))
|
||||
goto error_invalid_config;
|
||||
|
||||
/* Set/reset the mac.autoneg based on the link speed,
|
||||
* fixed or not
|
||||
*/
|
||||
if (!autoneg) {
|
||||
hw->mac.autoneg = 0;
|
||||
hw->mac.forced_speed_duplex =
|
||||
hw->phy.autoneg_advertised;
|
||||
} else {
|
||||
hw->mac.autoneg = 1;
|
||||
}
|
||||
}
|
||||
|
||||
igc_setup_link(hw);
|
||||
|
||||
if (rte_intr_allow_others(intr_handle)) {
|
||||
/* check if lsc interrupt is enabled */
|
||||
if (dev->data->dev_conf.intr_conf.lsc)
|
||||
igc_lsc_interrupt_setup(dev, 1);
|
||||
else
|
||||
igc_lsc_interrupt_setup(dev, 0);
|
||||
} else {
|
||||
rte_intr_callback_unregister(intr_handle,
|
||||
eth_igc_interrupt_handler,
|
||||
(void *)dev);
|
||||
if (dev->data->dev_conf.intr_conf.lsc)
|
||||
PMD_DRV_LOG(INFO,
|
||||
"LSC won't enable because of no intr multiplex");
|
||||
}
|
||||
|
||||
/* enable uio/vfio intr/eventfd mapping */
|
||||
rte_intr_enable(intr_handle);
|
||||
|
||||
/* resume enabled intr since hw reset */
|
||||
igc_intr_other_enable(dev);
|
||||
|
||||
eth_igc_link_update(dev, 0);
|
||||
|
||||
return 0;
|
||||
|
||||
error_invalid_config:
|
||||
PMD_DRV_LOG(ERR, "Invalid advertised speeds (%u) for port %u",
|
||||
dev->data->dev_conf.link_speeds, dev->data->port_id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
static int
|
||||
@ -232,10 +752,28 @@ igc_reset_swfw_lock(struct igc_hw *hw)
|
||||
static void
|
||||
eth_igc_close(struct rte_eth_dev *dev)
|
||||
{
|
||||
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
|
||||
struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
|
||||
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
|
||||
struct igc_adapter *adapter = IGC_DEV_PRIVATE(dev);
|
||||
int retry = 0;
|
||||
|
||||
PMD_INIT_FUNC_TRACE();
|
||||
|
||||
if (!adapter->stopped)
|
||||
eth_igc_stop(dev);
|
||||
|
||||
igc_intr_other_disable(dev);
|
||||
do {
|
||||
int ret = rte_intr_callback_unregister(intr_handle,
|
||||
eth_igc_interrupt_handler, dev);
|
||||
if (ret >= 0 || ret == -ENOENT || ret == -EINVAL)
|
||||
break;
|
||||
|
||||
PMD_DRV_LOG(ERR, "intr callback unregister failed: %d", ret);
|
||||
DELAY(200 * 1000); /* delay 200ms */
|
||||
} while (retry++ < 5);
|
||||
|
||||
igc_phy_hw_reset(hw);
|
||||
igc_hw_control_release(hw);
|
||||
|
||||
@ -258,6 +796,7 @@ static int
|
||||
eth_igc_dev_init(struct rte_eth_dev *dev)
|
||||
{
|
||||
struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
|
||||
struct igc_adapter *igc = IGC_DEV_PRIVATE(dev);
|
||||
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
|
||||
int error = 0;
|
||||
|
||||
@ -364,6 +903,7 @@ eth_igc_dev_init(struct rte_eth_dev *dev)
|
||||
dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
|
||||
|
||||
hw->mac.get_link_status = 1;
|
||||
igc->stopped = 0;
|
||||
|
||||
/* Indicate SOL/IDER usage */
|
||||
if (igc_check_reset_block(hw) < 0)
|
||||
@ -374,6 +914,15 @@ eth_igc_dev_init(struct rte_eth_dev *dev)
|
||||
dev->data->port_id, pci_dev->id.vendor_id,
|
||||
pci_dev->id.device_id);
|
||||
|
||||
rte_intr_callback_register(&pci_dev->intr_handle,
|
||||
eth_igc_interrupt_handler, (void *)dev);
|
||||
|
||||
/* enable uio/vfio intr/eventfd mapping */
|
||||
rte_intr_enable(&pci_dev->intr_handle);
|
||||
|
||||
/* enable support intr */
|
||||
igc_intr_other_enable(dev);
|
||||
|
||||
return 0;
|
||||
|
||||
err_late:
|
||||
@ -423,16 +972,81 @@ eth_igc_promiscuous_disable(struct rte_eth_dev *dev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
eth_igc_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
|
||||
size_t fw_size)
|
||||
{
|
||||
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
|
||||
struct igc_fw_version fw;
|
||||
int ret;
|
||||
|
||||
igc_get_fw_version(hw, &fw);
|
||||
|
||||
/* if option rom is valid, display its version too */
|
||||
if (fw.or_valid) {
|
||||
ret = snprintf(fw_version, fw_size,
|
||||
"%d.%d, 0x%08x, %d.%d.%d",
|
||||
fw.eep_major, fw.eep_minor, fw.etrack_id,
|
||||
fw.or_major, fw.or_build, fw.or_patch);
|
||||
/* no option rom */
|
||||
} else {
|
||||
if (fw.etrack_id != 0X0000) {
|
||||
ret = snprintf(fw_version, fw_size,
|
||||
"%d.%d, 0x%08x",
|
||||
fw.eep_major, fw.eep_minor,
|
||||
fw.etrack_id);
|
||||
} else {
|
||||
ret = snprintf(fw_version, fw_size,
|
||||
"%d.%d.%d",
|
||||
fw.eep_major, fw.eep_minor,
|
||||
fw.eep_build);
|
||||
}
|
||||
}
|
||||
|
||||
ret += 1; /* add the size of '\0' */
|
||||
if (fw_size < (u32)ret)
|
||||
return ret;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
eth_igc_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
|
||||
{
|
||||
PMD_INIT_FUNC_TRACE();
|
||||
RTE_SET_USED(dev);
|
||||
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
|
||||
|
||||
dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
|
||||
dev_info->max_rx_pktlen = MAX_RX_JUMBO_FRAME_SIZE;
|
||||
dev_info->max_mac_addrs = hw->mac.rar_entry_count;
|
||||
dev_info->max_rx_queues = IGC_QUEUE_PAIRS_NUM;
|
||||
dev_info->max_tx_queues = IGC_QUEUE_PAIRS_NUM;
|
||||
dev_info->max_vmdq_pools = 0;
|
||||
|
||||
dev_info->speed_capa = ETH_LINK_SPEED_10M_HD | ETH_LINK_SPEED_10M |
|
||||
ETH_LINK_SPEED_100M_HD | ETH_LINK_SPEED_100M |
|
||||
ETH_LINK_SPEED_1G | ETH_LINK_SPEED_2_5G;
|
||||
|
||||
dev_info->max_mtu = dev_info->max_rx_pktlen - IGC_ETH_OVERHEAD;
|
||||
dev_info->min_mtu = RTE_ETHER_MIN_MTU;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
eth_igc_led_on(struct rte_eth_dev *dev)
|
||||
{
|
||||
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
|
||||
|
||||
return igc_led_on(hw) == IGC_SUCCESS ? 0 : -ENOTSUP;
|
||||
}
|
||||
|
||||
static int
|
||||
eth_igc_led_off(struct rte_eth_dev *dev)
|
||||
{
|
||||
struct igc_hw *hw = IGC_DEV_PRIVATE_HW(dev);
|
||||
|
||||
return igc_led_off(hw) == IGC_SUCCESS ? 0 : -ENOTSUP;
|
||||
}
|
||||
|
||||
static int
|
||||
eth_igc_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
|
||||
uint16_t nb_rx_desc, unsigned int socket_id,
|
||||
@ -463,6 +1077,16 @@ eth_igc_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void eth_igc_tx_queue_release(void *txq)
|
||||
{
|
||||
RTE_SET_USED(txq);
|
||||
}
|
||||
|
||||
static void eth_igc_rx_queue_release(void *rxq)
|
||||
{
|
||||
RTE_SET_USED(rxq);
|
||||
}
|
||||
|
||||
static int
|
||||
eth_igc_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
|
||||
struct rte_pci_device *pci_dev)
|
||||
|
||||
@ -18,11 +18,19 @@ extern "C" {
|
||||
|
||||
#define IGC_QUEUE_PAIRS_NUM 4
|
||||
|
||||
/* structure for interrupt relative data */
|
||||
struct igc_interrupt {
|
||||
uint32_t flags;
|
||||
uint32_t mask;
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure to store private data for each driver instance (for each port).
|
||||
*/
|
||||
struct igc_adapter {
|
||||
struct igc_hw hw;
|
||||
struct igc_interrupt intr;
|
||||
bool stopped;
|
||||
};
|
||||
|
||||
#define IGC_DEV_PRIVATE(_dev) ((_dev)->data->dev_private)
|
||||
@ -30,6 +38,33 @@ struct igc_adapter {
|
||||
#define IGC_DEV_PRIVATE_HW(_dev) \
|
||||
(&((struct igc_adapter *)(_dev)->data->dev_private)->hw)
|
||||
|
||||
#define IGC_DEV_PRIVATE_INTR(_dev) \
|
||||
(&((struct igc_adapter *)(_dev)->data->dev_private)->intr)
|
||||
|
||||
static inline void
|
||||
igc_read_reg_check_set_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
|
||||
{
|
||||
uint32_t reg_val = IGC_READ_REG(hw, reg);
|
||||
|
||||
bits |= reg_val;
|
||||
if (bits == reg_val)
|
||||
return; /* no need to write back */
|
||||
|
||||
IGC_WRITE_REG(hw, reg, bits);
|
||||
}
|
||||
|
||||
static inline void
|
||||
igc_read_reg_check_clear_bits(struct igc_hw *hw, uint32_t reg, uint32_t bits)
|
||||
{
|
||||
uint32_t reg_val = IGC_READ_REG(hw, reg);
|
||||
|
||||
bits = reg_val & ~bits;
|
||||
if (bits == reg_val)
|
||||
return; /* no need to write back */
|
||||
|
||||
IGC_WRITE_REG(hw, reg, bits);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user