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net/qede: use common bit operations API

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Remove its own bit operation APIs and use the common one,
this can reduce the code duplication largely.

Signed-off-by: Joyce Kong <joyce.kong@arm.com>
Reviewed-by: Gavin Hu <gavin.hu@arm.com>
This commit is contained in:
Joyce Kong 2020-04-27 15:58:55 +08:00 committed by Thomas Monjalon
parent de6eab7c1e
commit 5018f1fc5f
13 changed files with 56 additions and 78 deletions
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22
drivers/net/qede/base/bcm_osal.c
View File

@ -46,26 +46,6 @@ u32 qede_osal_log2(u32 val)
return log;
}
inline void qede_set_bit(u32 nr, unsigned long *addr)
{
__sync_fetch_and_or(addr, (1UL << nr));
}
inline void qede_clr_bit(u32 nr, unsigned long *addr)
{
__sync_fetch_and_and(addr, ~(1UL << nr));
}
inline bool qede_test_bit(u32 nr, unsigned long *addr)
{
bool res;
rte_mb();
res = ((*addr) & (1UL << nr)) != 0;
rte_mb();
return res;
}
static inline u32 qede_ffb(unsigned long word)
{
unsigned long first_bit;
@ -95,7 +75,7 @@ static inline u32 qede_ffz(unsigned long word)
return first_zero ? (first_zero - 1) : OSAL_BITS_PER_UL;
}
inline u32 qede_find_first_zero_bit(unsigned long *addr, u32 limit)
inline u32 qede_find_first_zero_bit(u32 *addr, u32 limit)
{
u32 i;
u32 nwords = 0;

14
drivers/net/qede/base/bcm_osal.h
View File

@ -8,6 +8,7 @@
#define __BCM_OSAL_H
#include <stdbool.h>
#include <rte_bitops.h>
#include <rte_byteorder.h>
#include <rte_spinlock.h>
#include <rte_malloc.h>
@ -308,23 +309,20 @@ typedef struct osal_list_t {
#define OSAL_BITS_PER_UL_MASK (OSAL_BITS_PER_UL - 1)
/* Bitops */
void qede_set_bit(u32, unsigned long *);
#define OSAL_SET_BIT(bit, bitmap) \
qede_set_bit(bit, bitmap)
rte_bit_relaxed_set32(bit, bitmap)
void qede_clr_bit(u32, unsigned long *);
#define OSAL_CLEAR_BIT(bit, bitmap) \
qede_clr_bit(bit, bitmap)
rte_bit_relaxed_clear32(bit, bitmap)
bool qede_test_bit(u32, unsigned long *);
#define OSAL_TEST_BIT(bit, bitmap) \
qede_test_bit(bit, bitmap)
#define OSAL_GET_BIT(bit, bitmap) \
rte_bit_relaxed_get32(bit, bitmap)
u32 qede_find_first_bit(unsigned long *, u32);
#define OSAL_FIND_FIRST_BIT(bitmap, length) \
qede_find_first_bit(bitmap, length)
u32 qede_find_first_zero_bit(unsigned long *, u32);
u32 qede_find_first_zero_bit(u32 *bitmap, u32 length);
#define OSAL_FIND_FIRST_ZERO_BIT(bitmap, length) \
qede_find_first_zero_bit(bitmap, length)

6
drivers/net/qede/base/ecore.h
View File

@ -422,8 +422,8 @@ struct ecore_hw_info {
u8 max_chains_per_vf;
u32 port_mode;
u32 hw_mode;
unsigned long device_capabilities;
u32 hw_mode;
u32 device_capabilities;
/* Default DCBX mode */
u8 dcbx_mode;
@ -807,7 +807,7 @@ struct ecore_dev {
u8 path_id;
unsigned long mf_bits;
u32 mf_bits;
enum ecore_mf_mode mf_mode;
#define IS_MF_DEFAULT(_p_hwfn) \
(((_p_hwfn)->p_dev)->mf_mode == ECORE_MF_DEFAULT)

6
drivers/net/qede/base/ecore_cxt.c
View File

@ -154,7 +154,7 @@ struct ecore_ilt_client_cfg {
struct ecore_cid_acquired_map {
u32 start_cid;
u32 max_count;
unsigned long *cid_map;
u32 *cid_map;
};
struct ecore_src_t2 {
@ -1991,7 +1991,7 @@ static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
}
rel_cid = cid - (*pp_map)->start_cid;
if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
if (!OSAL_GET_BIT(rel_cid, (*pp_map)->cid_map)) {
DP_NOTICE(p_hwfn, true,
"CID %d [vifd %02x] not acquired", cid, vfid);
goto fail;
@ -2102,7 +2102,7 @@ enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn)
count = p_params->num_arfs_filters;
if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS,
if (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS,
&p_hwfn->p_dev->mf_bits))
p_hwfn->p_cxt_mngr->arfs_count = count;

8
drivers/net/qede/base/ecore_dcbx.c
View File

@ -148,7 +148,7 @@ ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,
p_data->arr[type].update = UPDATE_DCB_DSCP;
/* Do not add valn tag 0 when DCB is enabled and port is in UFP mode */
if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
p_data->arr[type].dont_add_vlan0 = true;
/* QM reconf data */
@ -156,8 +156,8 @@ ecore_dcbx_set_params(struct ecore_dcbx_results *p_data,
p_hwfn->hw_info.offload_tc = tc;
/* Configure dcbx vlan priority in doorbell block for roce EDPM */
if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits) &&
(type == DCBX_PROTOCOL_ROCE)) {
if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits) &&
type == DCBX_PROTOCOL_ROCE) {
ecore_wr(p_hwfn, p_ptt, DORQ_REG_TAG1_OVRD_MODE, 1);
ecore_wr(p_hwfn, p_ptt, DORQ_REG_PF_PCP, prio << 1);
}
@ -293,7 +293,7 @@ ecore_dcbx_process_tlv(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
}
/* If Eth TLV is not detected, use UFP TC as default TC */
if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC,
if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC,
&p_hwfn->p_dev->mf_bits) && !eth_tlv)
p_data->arr[DCBX_PROTOCOL_ETH].tc = p_hwfn->ufp_info.tc;

38
drivers/net/qede/base/ecore_dev.c
View File

@ -805,7 +805,7 @@ static enum _ecore_status_t ecore_llh_hw_init_pf(struct ecore_hwfn *p_hwfn,
ecore_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id);
}
if (OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
if (OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
!ECORE_IS_FCOE_PERSONALITY(p_hwfn)) {
rc = ecore_llh_add_mac_filter(p_dev, 0,
p_hwfn->hw_info.hw_mac_addr);
@ -1044,7 +1044,7 @@ ecore_llh_add_filter(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
filter_details.enable = 1;
filter_details.value = ((u64)high << 32) | low;
filter_details.hdr_sel =
OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits) ?
1 : /* inner/encapsulated header */
0; /* outer/tunnel header */
filter_details.protocol_type = filter_prot_type;
@ -1083,7 +1083,7 @@ enum _ecore_status_t ecore_llh_add_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
if (p_ptt == OSAL_NULL)
return ECORE_AGAIN;
if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
goto out;
OSAL_MEM_ZERO(&filter, sizeof(filter));
@ -1220,7 +1220,7 @@ ecore_llh_add_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
if (p_ptt == OSAL_NULL)
return ECORE_AGAIN;
if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
goto out;
rc = ecore_llh_protocol_filter_stringify(p_dev, type,
@ -1287,7 +1287,7 @@ void ecore_llh_remove_mac_filter(struct ecore_dev *p_dev, u8 ppfid,
if (p_ptt == OSAL_NULL)
return;
if (!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
if (!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
goto out;
OSAL_MEM_ZERO(&filter, sizeof(filter));
@ -1342,7 +1342,7 @@ void ecore_llh_remove_protocol_filter(struct ecore_dev *p_dev, u8 ppfid,
if (p_ptt == OSAL_NULL)
return;
if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits))
goto out;
rc = ecore_llh_protocol_filter_stringify(p_dev, type,
@ -1396,8 +1396,8 @@ void ecore_llh_clear_ppfid_filters(struct ecore_dev *p_dev, u8 ppfid)
if (p_ptt == OSAL_NULL)
return;
if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
goto out;
rc = ecore_abs_ppfid(p_dev, ppfid, &abs_ppfid);
@ -1423,8 +1423,8 @@ void ecore_llh_clear_all_filters(struct ecore_dev *p_dev)
{
u8 ppfid;
if (!OSAL_TEST_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
!OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
if (!OSAL_GET_BIT(ECORE_MF_LLH_PROTO_CLSS, &p_dev->mf_bits) &&
!OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits))
return;
for (ppfid = 0; ppfid < p_dev->p_llh_info->num_ppfid; ppfid++)
@ -2674,7 +2674,7 @@ static enum _ecore_status_t ecore_calc_hw_mode(struct ecore_hwfn *p_hwfn)
return ECORE_INVAL;
}
if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
hw_mode |= 1 << MODE_MF_SD;
else
hw_mode |= 1 << MODE_MF_SI;
@ -3382,7 +3382,7 @@ static enum _ecore_status_t ecore_hw_init_port(struct ecore_hwfn *p_hwfn,
* The ppfid should be set in the vector, except in BB which has
* a bug in the LLH where the ppfid is actually engine based.
*/
if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {
if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_dev->mf_bits)) {
u8 pf_id = p_hwfn->rel_pf_id;
if (!ECORE_IS_BB(p_dev))
@ -3715,11 +3715,11 @@ enum _ecore_status_t ecore_hw_init(struct ecore_dev *p_dev,
if (rc != ECORE_SUCCESS)
return rc;
if (IS_PF(p_dev) && (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
if (IS_PF(p_dev) && (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,
&p_dev->mf_bits) ||
OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
OSAL_GET_BIT(ECORE_MF_8021AD_TAGGING,
&p_dev->mf_bits))) {
if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING,
if (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING,
&p_dev->mf_bits))
ether_type = ETHER_TYPE_VLAN;
else
@ -4119,7 +4119,7 @@ enum _ecore_status_t ecore_hw_stop(struct ecore_dev *p_dev)
OSAL_MSLEEP(1);
if (IS_LEAD_HWFN(p_hwfn) &&
OSAL_TEST_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
OSAL_GET_BIT(ECORE_MF_LLH_MAC_CLSS, &p_dev->mf_bits) &&
!ECORE_IS_FCOE_PERSONALITY(p_hwfn))
ecore_llh_remove_mac_filter(p_dev, 0,
p_hwfn->hw_info.hw_mac_addr);
@ -5113,7 +5113,7 @@ ecore_hw_get_nvm_info(struct ecore_hwfn *p_hwfn,
p_hwfn->p_dev->mf_bits |= 1 << ECORE_MF_NEED_DEF_PF;
break;
}
DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n",
DP_INFO(p_hwfn, "Multi function mode is 0x%x\n",
p_hwfn->p_dev->mf_bits);
if (ECORE_IS_CMT(p_hwfn->p_dev))
@ -6218,7 +6218,7 @@ enum _ecore_status_t
ecore_llh_set_function_as_default(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt)
{
if (OSAL_TEST_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
if (OSAL_GET_BIT(ECORE_MF_NEED_DEF_PF, &p_hwfn->p_dev->mf_bits)) {
ecore_wr(p_hwfn, p_ptt,
NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR,
1 << p_hwfn->abs_pf_id / 2);
@ -6795,5 +6795,5 @@ void ecore_set_fw_mac_addr(__le16 *fw_msb,
bool ecore_is_mf_fip_special(struct ecore_dev *p_dev)
{
return !!OSAL_TEST_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
return !!OSAL_GET_BIT(ECORE_MF_FIP_SPECIAL, &p_dev->mf_bits);
}

2
drivers/net/qede/base/ecore_dev_api.h
View File

@ -212,7 +212,7 @@ enum _ecore_status_t ecore_db_recovery_del(struct ecore_dev *p_dev,
static OSAL_INLINE bool ecore_is_mf_ufp(struct ecore_hwfn *p_hwfn)
{
return !!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits);
return !!OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits);
}
#endif

6
drivers/net/qede/base/ecore_l2.c
View File

@ -29,7 +29,7 @@
struct ecore_l2_info {
u32 queues;
unsigned long **pp_qid_usage;
u32 **pp_qid_usage;
/* The lock is meant to synchronize access to the qid usage */
osal_mutex_t lock;
@ -38,7 +38,7 @@ struct ecore_l2_info {
enum _ecore_status_t ecore_l2_alloc(struct ecore_hwfn *p_hwfn)
{
struct ecore_l2_info *p_l2_info;
unsigned long **pp_qids;
u32 **pp_qids;
u32 i;
if (!ECORE_IS_L2_PERSONALITY(p_hwfn))
@ -2116,7 +2116,7 @@ void ecore_arfs_mode_configure(struct ecore_hwfn *p_hwfn,
struct ecore_ptt *p_ptt,
struct ecore_arfs_config_params *p_cfg_params)
{
if (OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits))
if (OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &p_hwfn->p_dev->mf_bits))
return;
if (p_cfg_params->mode != ECORE_FILTER_CONFIG_MODE_DISABLE) {

4
drivers/net/qede/base/ecore_mcp.c
View File

@ -1732,7 +1732,7 @@ static void ecore_mcp_update_stag(struct ecore_hwfn *p_hwfn,
p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
FUNC_MF_CFG_OV_STAG_MASK;
p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) {
if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits)) {
if (p_hwfn->hw_info.ovlan != ECORE_MCP_VLAN_UNSET) {
ecore_wr(p_hwfn, p_ptt, NIG_REG_LLH_FUNC_TAG_VALUE,
p_hwfn->hw_info.ovlan);
@ -2026,7 +2026,7 @@ ecore_mcp_read_ufp_config(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt)
struct public_func shmem_info;
u32 port_cfg, val;
if (!OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
if (!OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
return;
OSAL_MEMSET(&p_hwfn->ufp_info, 0, sizeof(p_hwfn->ufp_info));

12
drivers/net/qede/base/ecore_sp_commands.c
View File

@ -335,16 +335,16 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
p_ramrod->dont_log_ramrods = 0;
p_ramrod->log_type_mask = OSAL_CPU_TO_LE16(0x8f);
if (OSAL_TEST_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
if (OSAL_GET_BIT(ECORE_MF_OVLAN_CLSS, &p_hwfn->p_dev->mf_bits))
p_ramrod->mf_mode = MF_OVLAN;
else
p_ramrod->mf_mode = MF_NPAR;
p_ramrod->outer_tag_config.outer_tag.tci =
OSAL_CPU_TO_LE16(p_hwfn->hw_info.ovlan);
if (OSAL_TEST_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) {
if (OSAL_GET_BIT(ECORE_MF_8021Q_TAGGING, &p_hwfn->p_dev->mf_bits)) {
p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021Q;
} else if (OSAL_TEST_BIT(ECORE_MF_8021AD_TAGGING,
} else if (OSAL_GET_BIT(ECORE_MF_8021AD_TAGGING,
&p_hwfn->p_dev->mf_bits)) {
p_ramrod->outer_tag_config.outer_tag.tpid = ETH_P_8021AD;
p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
@ -357,7 +357,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
/* enable_stag_pri_change should be set if port is in BD mode or,
* UFP with Host Control mode.
*/
if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) {
if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits)) {
if (p_hwfn->ufp_info.pri_type == ECORE_UFP_PRI_OS)
p_ramrod->outer_tag_config.enable_stag_pri_change = 1;
else
@ -378,7 +378,7 @@ enum _ecore_status_t ecore_sp_pf_start(struct ecore_hwfn *p_hwfn,
ecore_tunn_set_pf_start_params(p_hwfn, p_tunn,
&p_ramrod->tunnel_config);
if (OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH,
if (OSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH,
&p_hwfn->p_dev->mf_bits))
p_ramrod->allow_npar_tx_switching = allow_npar_tx_switch;
@ -638,7 +638,7 @@ enum _ecore_status_t ecore_sp_heartbeat_ramrod(struct ecore_hwfn *p_hwfn)
if (rc != ECORE_SUCCESS)
return rc;
if (OSAL_TEST_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
if (OSAL_GET_BIT(ECORE_MF_UFP_SPECIFIC, &p_hwfn->p_dev->mf_bits))
p_ent->ramrod.pf_update.mf_vlan |=
OSAL_CPU_TO_LE16(((u16)p_hwfn->ufp_info.tc << 13));

2
drivers/net/qede/base/ecore_spq.c
View File

@ -977,7 +977,7 @@ enum _ecore_status_t ecore_spq_completion(struct ecore_hwfn *p_hwfn,
* for the first successive completed entries.
*/
SPQ_COMP_BMAP_SET_BIT(p_spq, echo);
while (SPQ_COMP_BMAP_TEST_BIT(p_spq,
while (SPQ_COMP_BMAP_GET_BIT(p_spq,
p_spq->comp_bitmap_idx)) {
SPQ_COMP_BMAP_CLEAR_BIT(p_spq,
p_spq->comp_bitmap_idx);

10
drivers/net/qede/base/ecore_spq.h
View File

@ -121,17 +121,17 @@ struct ecore_spq {
#define SPQ_RING_SIZE \
(CORE_SPQE_PAGE_SIZE_BYTES / sizeof(struct slow_path_element))
/* BITS_PER_LONG */
#define SPQ_COMP_BMAP_SIZE (SPQ_RING_SIZE / (sizeof(unsigned long) * 8))
unsigned long p_comp_bitmap[SPQ_COMP_BMAP_SIZE];
u8 comp_bitmap_idx;
#define SPQ_COMP_BMAP_SIZE (SPQ_RING_SIZE / (sizeof(u32) * 8))
u32 p_comp_bitmap[SPQ_COMP_BMAP_SIZE];
u8 comp_bitmap_idx;
#define SPQ_COMP_BMAP_SET_BIT(p_spq, idx) \
(OSAL_SET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))
#define SPQ_COMP_BMAP_CLEAR_BIT(p_spq, idx) \
(OSAL_CLEAR_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))
#define SPQ_COMP_BMAP_TEST_BIT(p_spq, idx) \
(OSAL_TEST_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))
#define SPQ_COMP_BMAP_GET_BIT(p_spq, idx) \
(OSAL_GET_BIT(((idx) % SPQ_RING_SIZE), (p_spq)->p_comp_bitmap))
/* Statistics */
u32 unlimited_pending_count;

4
drivers/net/qede/qede_main.c
View File

@ -382,8 +382,8 @@ qed_fill_dev_info(struct ecore_dev *edev, struct qed_dev_info *dev_info)
if (IS_PF(edev)) {
dev_info->b_inter_pf_switch =
OSAL_TEST_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits);
if (!OSAL_TEST_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits))
OSAL_GET_BIT(ECORE_MF_INTER_PF_SWITCH, &edev->mf_bits);
if (!OSAL_GET_BIT(ECORE_MF_DISABLE_ARFS, &edev->mf_bits))
dev_info->b_arfs_capable = true;
dev_info->tx_switching = false;