mempool/octeontx2: add NPA IRQ handler
Register and implement NPA IRQ handler for RAS and all type of error interrupts to get the fatal errors from HW. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Harman Kalra <hkalra@marvell.com>
This commit is contained in:
Jerin Jacob
Thomas Monjalon
parent
35e628db9d
commit
50b95c3ea7
@ -28,7 +28,8 @@ LIBABIVER := 1
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# all source are stored in SRCS-y
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#
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SRCS-$(CONFIG_RTE_LIBRTE_OCTEONTX2_MEMPOOL) += \
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otx2_mempool.c
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otx2_mempool.c \
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otx2_mempool_irq.c
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LDLIBS += -lrte_eal -lrte_mempool -lrte_mbuf
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LDLIBS += -lrte_common_octeontx2 -lrte_kvargs -lrte_bus_pci
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@ -3,6 +3,7 @@
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#
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sources = files('otx2_mempool.c',
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'otx2_mempool_irq.c',
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)
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extra_flags = []
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@ -195,6 +195,7 @@ otx2_npa_lf_fini(void)
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return -ENOMEM;
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if (rte_atomic16_add_return(&idev->npa_refcnt, -1) == 0) {
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otx2_npa_unregister_irqs(idev->npa_lf);
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rc |= npa_lf_fini(idev->npa_lf);
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rc |= npa_lf_detach(idev->npa_lf->mbox);
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otx2_npa_set_defaults(idev);
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@ -251,6 +252,9 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)
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idev->npa_pf_func = dev->pf_func;
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idev->npa_lf = lf;
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rte_smp_wmb();
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rc = otx2_npa_register_irqs(lf);
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if (rc)
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goto npa_fini;
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rte_mbuf_set_platform_mempool_ops("octeontx2_npa");
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otx2_npa_dbg("npa_lf=%p pools=%d sz=%d pf_func=0x%x msix=0x%x",
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@ -259,6 +263,8 @@ otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev)
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return 0;
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npa_fini:
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npa_lf_fini(idev->npa_lf);
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npa_detach:
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npa_lf_detach(dev->mbox);
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fail:
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@ -198,4 +198,8 @@ npa_lf_aura_op_range_set(uint64_t aura_handle, uint64_t start_iova,
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int otx2_npa_lf_init(struct rte_pci_device *pci_dev, void *otx2_dev);
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int otx2_npa_lf_fini(void);
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/* IRQ */
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int otx2_npa_register_irqs(struct otx2_npa_lf *lf);
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void otx2_npa_unregister_irqs(struct otx2_npa_lf *lf);
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#endif /* __OTX2_MEMPOOL_H__ */
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302
drivers/mempool/octeontx2/otx2_mempool_irq.c
Normal file
302
drivers/mempool/octeontx2/otx2_mempool_irq.c
Normal file
@ -0,0 +1,302 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#include <inttypes.h>
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#include <rte_common.h>
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#include <rte_bus_pci.h>
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#include "otx2_common.h"
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#include "otx2_irq.h"
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#include "otx2_mempool.h"
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static void
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npa_lf_err_irq(void *param)
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{
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struct otx2_npa_lf *lf = (struct otx2_npa_lf *)param;
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uint64_t intr;
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intr = otx2_read64(lf->base + NPA_LF_ERR_INT);
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if (intr == 0)
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return;
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otx2_err("Err_intr=0x%" PRIx64 "", intr);
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/* Clear interrupt */
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otx2_write64(intr, lf->base + NPA_LF_ERR_INT);
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}
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static int
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npa_lf_register_err_irq(struct otx2_npa_lf *lf)
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{
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struct rte_intr_handle *handle = lf->intr_handle;
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int rc, vec;
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vec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;
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/* Clear err interrupt */
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otx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);
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/* Register err interrupt vector */
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rc = otx2_register_irq(handle, npa_lf_err_irq, lf, vec);
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/* Enable hw interrupt */
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otx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1S);
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return rc;
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}
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static void
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npa_lf_unregister_err_irq(struct otx2_npa_lf *lf)
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{
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struct rte_intr_handle *handle = lf->intr_handle;
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int vec;
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vec = lf->npa_msixoff + NPA_LF_INT_VEC_ERR_INT;
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/* Clear err interrupt */
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otx2_write64(~0ull, lf->base + NPA_LF_ERR_INT_ENA_W1C);
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otx2_unregister_irq(handle, npa_lf_err_irq, lf, vec);
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}
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static void
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npa_lf_ras_irq(void *param)
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{
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struct otx2_npa_lf *lf = (struct otx2_npa_lf *)param;
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uint64_t intr;
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intr = otx2_read64(lf->base + NPA_LF_RAS);
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if (intr == 0)
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return;
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otx2_err("Ras_intr=0x%" PRIx64 "", intr);
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/* Clear interrupt */
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otx2_write64(intr, lf->base + NPA_LF_RAS);
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}
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static int
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npa_lf_register_ras_irq(struct otx2_npa_lf *lf)
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{
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struct rte_intr_handle *handle = lf->intr_handle;
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int rc, vec;
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vec = lf->npa_msixoff + NPA_LF_INT_VEC_POISON;
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/* Clear err interrupt */
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otx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C);
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/* Set used interrupt vectors */
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rc = otx2_register_irq(handle, npa_lf_ras_irq, lf, vec);
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/* Enable hw interrupt */
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otx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1S);
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return rc;
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}
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static void
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npa_lf_unregister_ras_irq(struct otx2_npa_lf *lf)
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{
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int vec;
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struct rte_intr_handle *handle = lf->intr_handle;
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vec = lf->npa_msixoff + NPA_LF_INT_VEC_POISON;
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/* Clear err interrupt */
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otx2_write64(~0ull, lf->base + NPA_LF_RAS_ENA_W1C);
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otx2_unregister_irq(handle, npa_lf_ras_irq, lf, vec);
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}
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static inline uint8_t
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npa_lf_q_irq_get_and_clear(struct otx2_npa_lf *lf, uint32_t q,
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uint32_t off, uint64_t mask)
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{
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uint64_t reg, wdata;
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uint8_t qint;
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wdata = (uint64_t)q << 44;
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reg = otx2_atomic64_add_nosync(wdata, (int64_t *)(lf->base + off));
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if (reg & BIT_ULL(42) /* OP_ERR */) {
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otx2_err("Failed execute irq get off=0x%x", off);
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return 0;
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}
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qint = reg & 0xff;
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wdata &= mask;
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otx2_write64(wdata, lf->base + off);
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return qint;
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}
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static inline uint8_t
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npa_lf_pool_irq_get_and_clear(struct otx2_npa_lf *lf, uint32_t p)
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{
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return npa_lf_q_irq_get_and_clear(lf, p, NPA_LF_POOL_OP_INT, ~0xff00);
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}
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static inline uint8_t
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npa_lf_aura_irq_get_and_clear(struct otx2_npa_lf *lf, uint32_t a)
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{
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return npa_lf_q_irq_get_and_clear(lf, a, NPA_LF_AURA_OP_INT, ~0xff00);
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}
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static void
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npa_lf_q_irq(void *param)
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{
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struct otx2_npa_qint *qint = (struct otx2_npa_qint *)param;
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struct otx2_npa_lf *lf = qint->lf;
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uint8_t irq, qintx = qint->qintx;
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uint32_t q, pool, aura;
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uint64_t intr;
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intr = otx2_read64(lf->base + NPA_LF_QINTX_INT(qintx));
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if (intr == 0)
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return;
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otx2_err("queue_intr=0x%" PRIx64 " qintx=%d", intr, qintx);
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/* Handle pool queue interrupts */
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for (q = 0; q < lf->nr_pools; q++) {
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/* Skip disabled POOL */
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if (rte_bitmap_get(lf->npa_bmp, q))
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continue;
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pool = q % lf->qints;
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irq = npa_lf_pool_irq_get_and_clear(lf, pool);
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if (irq & BIT_ULL(NPA_POOL_ERR_INT_OVFLS))
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otx2_err("Pool=%d NPA_POOL_ERR_INT_OVFLS", pool);
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if (irq & BIT_ULL(NPA_POOL_ERR_INT_RANGE))
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otx2_err("Pool=%d NPA_POOL_ERR_INT_RANGE", pool);
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if (irq & BIT_ULL(NPA_POOL_ERR_INT_PERR))
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otx2_err("Pool=%d NPA_POOL_ERR_INT_PERR", pool);
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}
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/* Handle aura queue interrupts */
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for (q = 0; q < lf->nr_pools; q++) {
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/* Skip disabled AURA */
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if (rte_bitmap_get(lf->npa_bmp, q))
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continue;
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aura = q % lf->qints;
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irq = npa_lf_aura_irq_get_and_clear(lf, aura);
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if (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_OVER))
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otx2_err("Aura=%d NPA_AURA_ERR_INT_ADD_OVER", aura);
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if (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_ADD_UNDER))
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otx2_err("Aura=%d NPA_AURA_ERR_INT_ADD_UNDER", aura);
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if (irq & BIT_ULL(NPA_AURA_ERR_INT_AURA_FREE_UNDER))
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otx2_err("Aura=%d NPA_AURA_ERR_INT_FREE_UNDER", aura);
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if (irq & BIT_ULL(NPA_AURA_ERR_INT_POOL_DIS))
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otx2_err("Aura=%d NPA_AURA_ERR_POOL_DIS", aura);
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}
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/* Clear interrupt */
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otx2_write64(intr, lf->base + NPA_LF_QINTX_INT(qintx));
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}
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static int
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npa_lf_register_queue_irqs(struct otx2_npa_lf *lf)
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{
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struct rte_intr_handle *handle = lf->intr_handle;
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int vec, q, qs, rc = 0;
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/* Figure out max qintx required */
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qs = RTE_MIN(lf->qints, lf->nr_pools);
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for (q = 0; q < qs; q++) {
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vec = lf->npa_msixoff + NPA_LF_INT_VEC_QINT_START + q;
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/* Clear QINT CNT */
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otx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q));
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/* Clear interrupt */
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otx2_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1C(q));
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struct otx2_npa_qint *qintmem = lf->npa_qint_mem;
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qintmem += q;
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qintmem->lf = lf;
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qintmem->qintx = q;
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/* Sync qints_mem update */
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rte_smp_wmb();
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/* Register queue irq vector */
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rc = otx2_register_irq(handle, npa_lf_q_irq, qintmem, vec);
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if (rc)
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break;
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otx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q));
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otx2_write64(0, lf->base + NPA_LF_QINTX_INT(q));
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/* Enable QINT interrupt */
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otx2_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1S(q));
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}
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return rc;
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}
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static void
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npa_lf_unregister_queue_irqs(struct otx2_npa_lf *lf)
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{
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struct rte_intr_handle *handle = lf->intr_handle;
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int vec, q, qs;
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/* Figure out max qintx required */
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qs = RTE_MIN(lf->qints, lf->nr_pools);
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for (q = 0; q < qs; q++) {
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vec = lf->npa_msixoff + NPA_LF_INT_VEC_QINT_START + q;
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/* Clear QINT CNT */
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otx2_write64(0, lf->base + NPA_LF_QINTX_CNT(q));
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otx2_write64(0, lf->base + NPA_LF_QINTX_INT(q));
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/* Clear interrupt */
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otx2_write64(~0ull, lf->base + NPA_LF_QINTX_ENA_W1C(q));
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struct otx2_npa_qint *qintmem = lf->npa_qint_mem;
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qintmem += q;
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/* Unregister queue irq vector */
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otx2_unregister_irq(handle, npa_lf_q_irq, qintmem, vec);
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qintmem->lf = NULL;
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qintmem->qintx = 0;
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}
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}
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int
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otx2_npa_register_irqs(struct otx2_npa_lf *lf)
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{
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int rc;
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if (lf->npa_msixoff == MSIX_VECTOR_INVALID) {
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otx2_err("Invalid NPALF MSIX vector offset vector: 0x%x",
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lf->npa_msixoff);
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return -EINVAL;
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}
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/* Register lf err interrupt */
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rc = npa_lf_register_err_irq(lf);
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/* Register RAS interrupt */
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rc |= npa_lf_register_ras_irq(lf);
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/* Register queue interrupts */
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rc |= npa_lf_register_queue_irqs(lf);
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return rc;
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}
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void
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otx2_npa_unregister_irqs(struct otx2_npa_lf *lf)
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{
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npa_lf_unregister_err_irq(lf);
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npa_lf_unregister_ras_irq(lf);
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npa_lf_unregister_queue_irqs(lf);
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}
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