net/mlx5: create relaxed ordering memory regions
In the current state, when preforming read/write transactions we must wait for a completion in order to run the next transaction, and all transactions are performed by order. Relaxed Ordering is a PCI optimization which by enabling it we allow the system to perform read/writes in a different order without having to wait for completion and improve the performance in that matter. This commit introduces the creation of relaxed ordering memory regions in mlx5. As relaxed ordering is an optimization, drivers that do not support it can simply ignore it and therefore it is enabled by default. Signed-off-by: Shiri Kuzin <shirik@mellanox.com> Acked-by: Matan Azrad <matan@mellanox.com>
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@ -93,6 +93,7 @@ New Features
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Updated Mellanox mlx5 driver with new features and improvements, including:
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* Added support for matching on IPv4 Time To Live and IPv6 Hop Limit.
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* Added support for creating Relaxed Ordering Memory Regions.
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* **Updated the AESNI MB crypto PMD.**
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@ -196,6 +196,10 @@ mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,
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MLX5_SET(mkc, mkc, pd, attr->pd);
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MLX5_SET(mkc, mkc, mkey_7_0, attr->umem_id & 0xFF);
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MLX5_SET(mkc, mkc, translations_octword_size, translation_size);
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if (attr->relaxed_ordering == 1) {
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MLX5_SET(mkc, mkc, relaxed_ordering_write, 0x1);
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MLX5_SET(mkc, mkc, relaxed_ordering_read, 0x1);
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}
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MLX5_SET64(mkc, mkc, start_addr, attr->addr);
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MLX5_SET64(mkc, mkc, len, attr->size);
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mkey->obj = mlx5_glue->devx_obj_create(ctx, in, in_size_dw * 4, out,
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@ -33,6 +33,7 @@ struct mlx5_devx_mkey_attr {
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uint32_t pd;
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uint32_t log_entity_size;
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uint32_t pg_access:1;
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uint32_t relaxed_ordering:1;
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struct mlx5_klm *klm_array;
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int klm_num;
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};
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@ -98,6 +98,10 @@ struct mlx5dv_var { uint32_t page_id; uint32_t length; off_t mmap_off;
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uint64_t comp_mask; };
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#endif
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#ifndef IBV_ACCESS_RELAXED_ORDERING
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#define IBV_ACCESS_RELAXED_ORDERING 0
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#endif
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/* LIB_GLUE_VERSION must be updated every time this structure is modified. */
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struct mlx5_glue {
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const char *version;
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@ -882,7 +882,9 @@ struct mlx5_ifc_mkc_bits {
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u8 translations_octword_size[0x20];
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u8 reserved_at_1c0[0x1b];
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u8 reserved_at_1c0[0x19];
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u8 relaxed_ordering_read[0x1];
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u8 reserved_at_1da[0x1];
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u8 log_page_size[0x5];
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u8 reserved_at_1e0[0x20];
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@ -3962,6 +3962,7 @@ flow_dv_create_counter_stat_mem_mng(struct rte_eth_dev *dev, int raws_n)
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mkey_attr.pg_access = 0;
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mkey_attr.klm_array = NULL;
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mkey_attr.klm_num = 0;
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mkey_attr.relaxed_ordering = 1;
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mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr);
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if (!mem_mng->dm) {
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mlx5_glue->devx_umem_dereg(mem_mng->umem);
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@ -768,7 +768,8 @@ alloc_resources:
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* through mlx5_alloc_verbs_buf().
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*/
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mr->ibv_mr = mlx5_glue->reg_mr(sh->pd, (void *)data.start, len,
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IBV_ACCESS_LOCAL_WRITE);
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IBV_ACCESS_LOCAL_WRITE |
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IBV_ACCESS_RELAXED_ORDERING);
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if (mr->ibv_mr == NULL) {
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DEBUG("port %u fail to create a verbs MR for address (%p)",
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dev->data->port_id, (void *)addr);
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@ -1217,7 +1218,8 @@ mlx5_create_mr_ext(struct rte_eth_dev *dev, uintptr_t addr, size_t len,
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if (mr == NULL)
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return NULL;
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mr->ibv_mr = mlx5_glue->reg_mr(priv->sh->pd, (void *)addr, len,
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IBV_ACCESS_LOCAL_WRITE);
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IBV_ACCESS_LOCAL_WRITE |
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IBV_ACCESS_RELAXED_ORDERING);
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if (mr->ibv_mr == NULL) {
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DRV_LOG(WARNING,
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"port %u fail to create a verbs MR for address (%p)",
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@ -39,6 +39,7 @@ mlx5_vdpa_dirty_bitmap_set(struct mlx5_vdpa_priv *priv, uint64_t log_base,
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.pg_access = 1,
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.klm_array = NULL,
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.klm_num = 0,
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.relaxed_ordering = 0,
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};
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struct mlx5_devx_virtq_attr attr = {
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.type = MLX5_VIRTQ_MODIFY_TYPE_DIRTY_BITMAP_PARAMS,
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@ -263,6 +263,7 @@ mlx5_vdpa_mem_register(struct mlx5_vdpa_priv *priv)
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mkey_attr.pg_access = 1;
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mkey_attr.klm_array = NULL;
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mkey_attr.klm_num = 0;
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mkey_attr.relaxed_ordering = 0;
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entry->mkey = mlx5_devx_cmd_mkey_create(priv->ctx, &mkey_attr);
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if (!entry->mkey) {
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DRV_LOG(ERR, "Failed to create direct Mkey.");
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