net/octeontx2: add device configure operation
Add device configure operation. This would call lf_alloc mailbox to allocate a NIX LF and upon return, AF will return the attributes for the select LF. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Vamsi Attunuru <vattunuru@marvell.com> Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
This commit is contained in:
Jerin Jacob
Ferruh Yigit
parent
60bb09ad2a
commit
548b5839a3
@ -39,6 +39,52 @@ nix_get_tx_offload_capa(struct otx2_eth_dev *dev)
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return NIX_TX_OFFLOAD_CAPA;
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}
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static int
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nix_lf_alloc(struct otx2_eth_dev *dev, uint32_t nb_rxq, uint32_t nb_txq)
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{
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struct otx2_mbox *mbox = dev->mbox;
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struct nix_lf_alloc_req *req;
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struct nix_lf_alloc_rsp *rsp;
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int rc;
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req = otx2_mbox_alloc_msg_nix_lf_alloc(mbox);
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req->rq_cnt = nb_rxq;
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req->sq_cnt = nb_txq;
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req->cq_cnt = nb_rxq;
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/* XQE_SZ should be in Sync with NIX_CQ_ENTRY_SZ */
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RTE_BUILD_BUG_ON(NIX_CQ_ENTRY_SZ != 128);
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req->xqe_sz = NIX_XQESZ_W16;
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req->rss_sz = dev->rss_info.rss_size;
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req->rss_grps = NIX_RSS_GRPS;
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req->npa_func = otx2_npa_pf_func_get();
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req->sso_func = otx2_sso_pf_func_get();
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req->rx_cfg = BIT_ULL(35 /* DIS_APAD */);
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if (dev->rx_offloads & (DEV_RX_OFFLOAD_TCP_CKSUM |
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DEV_RX_OFFLOAD_UDP_CKSUM)) {
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req->rx_cfg |= BIT_ULL(37 /* CSUM_OL4 */);
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req->rx_cfg |= BIT_ULL(36 /* CSUM_IL4 */);
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}
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rc = otx2_mbox_process_msg(mbox, (void *)&rsp);
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if (rc)
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return rc;
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dev->sqb_size = rsp->sqb_size;
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dev->tx_chan_base = rsp->tx_chan_base;
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dev->rx_chan_base = rsp->rx_chan_base;
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dev->rx_chan_cnt = rsp->rx_chan_cnt;
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dev->tx_chan_cnt = rsp->tx_chan_cnt;
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dev->lso_tsov4_idx = rsp->lso_tsov4_idx;
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dev->lso_tsov6_idx = rsp->lso_tsov6_idx;
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dev->lf_tx_stats = rsp->lf_tx_stats;
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dev->lf_rx_stats = rsp->lf_rx_stats;
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dev->cints = rsp->cints;
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dev->qints = rsp->qints;
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dev->npc_flow.channel = dev->rx_chan_base;
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return 0;
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}
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static int
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nix_lf_free(struct otx2_eth_dev *dev)
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{
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@ -64,9 +110,114 @@ nix_lf_free(struct otx2_eth_dev *dev)
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return otx2_mbox_process(mbox);
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}
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static int
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otx2_nix_configure(struct rte_eth_dev *eth_dev)
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{
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struct otx2_eth_dev *dev = otx2_eth_pmd_priv(eth_dev);
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struct rte_eth_dev_data *data = eth_dev->data;
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struct rte_eth_conf *conf = &data->dev_conf;
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struct rte_eth_rxmode *rxmode = &conf->rxmode;
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struct rte_eth_txmode *txmode = &conf->txmode;
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char ea_fmt[RTE_ETHER_ADDR_FMT_SIZE];
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struct rte_ether_addr *ea;
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uint8_t nb_rxq, nb_txq;
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int rc;
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rc = -EINVAL;
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/* Sanity checks */
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if (rte_eal_has_hugepages() == 0) {
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otx2_err("Huge page is not configured");
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goto fail;
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}
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if (rte_eal_iova_mode() != RTE_IOVA_VA) {
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otx2_err("iova mode should be va");
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goto fail;
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}
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if (conf->link_speeds & ETH_LINK_SPEED_FIXED) {
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otx2_err("Setting link speed/duplex not supported");
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goto fail;
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}
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if (conf->dcb_capability_en == 1) {
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otx2_err("dcb enable is not supported");
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goto fail;
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}
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if (conf->fdir_conf.mode != RTE_FDIR_MODE_NONE) {
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otx2_err("Flow director is not supported");
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goto fail;
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}
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if (rxmode->mq_mode != ETH_MQ_RX_NONE &&
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rxmode->mq_mode != ETH_MQ_RX_RSS) {
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otx2_err("Unsupported mq rx mode %d", rxmode->mq_mode);
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goto fail;
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}
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if (txmode->mq_mode != ETH_MQ_TX_NONE) {
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otx2_err("Unsupported mq tx mode %d", txmode->mq_mode);
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goto fail;
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}
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/* Free the resources allocated from the previous configure */
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if (dev->configured == 1)
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nix_lf_free(dev);
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if (otx2_dev_is_A0(dev) &&
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(txmode->offloads & DEV_TX_OFFLOAD_SCTP_CKSUM) &&
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((txmode->offloads & DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM) ||
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(txmode->offloads & DEV_TX_OFFLOAD_OUTER_UDP_CKSUM))) {
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otx2_err("Outer IP and SCTP checksum unsupported");
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rc = -EINVAL;
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goto fail;
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}
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dev->rx_offloads = rxmode->offloads;
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dev->tx_offloads = txmode->offloads;
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dev->rss_info.rss_grps = NIX_RSS_GRPS;
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nb_rxq = RTE_MAX(data->nb_rx_queues, 1);
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nb_txq = RTE_MAX(data->nb_tx_queues, 1);
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/* Alloc a nix lf */
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rc = nix_lf_alloc(dev, nb_rxq, nb_txq);
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if (rc) {
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otx2_err("Failed to init nix_lf rc=%d", rc);
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goto fail;
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}
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/* Update the mac address */
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ea = eth_dev->data->mac_addrs;
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memcpy(ea, dev->mac_addr, RTE_ETHER_ADDR_LEN);
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if (rte_is_zero_ether_addr(ea))
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rte_eth_random_addr((uint8_t *)ea);
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rte_ether_format_addr(ea_fmt, RTE_ETHER_ADDR_FMT_SIZE, ea);
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otx2_nix_dbg("Configured port%d mac=%s nb_rxq=%d nb_txq=%d"
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" rx_offloads=0x%" PRIx64 " tx_offloads=0x%" PRIx64 ""
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" rx_flags=0x%x tx_flags=0x%x",
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eth_dev->data->port_id, ea_fmt, nb_rxq,
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nb_txq, dev->rx_offloads, dev->tx_offloads,
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dev->rx_offload_flags, dev->tx_offload_flags);
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/* All good */
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dev->configured = 1;
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dev->configured_nb_rx_qs = data->nb_rx_queues;
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dev->configured_nb_tx_qs = data->nb_tx_queues;
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return 0;
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fail:
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return rc;
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}
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/* Initialize and register driver with DPDK Application */
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static const struct eth_dev_ops otx2_eth_dev_ops = {
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.dev_infos_get = otx2_nix_info_get,
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.dev_configure = otx2_nix_configure,
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};
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static inline int
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@ -59,11 +59,14 @@
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#define NIX_MAX_SQB 512
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#define NIX_MIN_SQB 32
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/* Group 0 will be used for RSS, 1 -7 will be used for rte_flow RSS action*/
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#define NIX_RSS_GRPS 8
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#define NIX_HASH_KEY_SIZE 48 /* 352 Bits */
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#define NIX_RSS_RETA_SIZE 64
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#define NIX_RX_MIN_DESC 16
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#define NIX_RX_MIN_DESC_ALIGN 16
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#define NIX_RX_NB_SEG_MAX 6
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#define NIX_CQ_ENTRY_SZ 128
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/* If PTP is enabled additional SEND MEM DESC is required which
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* takes 2 words, hence max 7 iova address are possible
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@ -105,9 +108,11 @@
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struct otx2_rss_info {
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uint16_t rss_size;
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uint8_t rss_grps;
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};
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struct otx2_npc_flow_info {
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uint16_t channel; /*rx channel */
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uint16_t flow_prealloc_size;
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uint16_t flow_max_priority;
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};
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@ -124,7 +129,13 @@ struct otx2_eth_dev {
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uint8_t lso_tsov6_idx;
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uint8_t mac_addr[RTE_ETHER_ADDR_LEN];
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uint8_t max_mac_entries;
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uint8_t lf_tx_stats;
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uint8_t lf_rx_stats;
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uint16_t cints;
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uint16_t qints;
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uint8_t configured;
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uint8_t configured_nb_rx_qs;
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uint8_t configured_nb_tx_qs;
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uint16_t nix_msixoff;
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uintptr_t base;
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uintptr_t lmt_addr;
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