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crypto/armv8: add documentation

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Add documentation about the driver and update
release notes.

Signed-off-by: Zbigniew Bodek <zbigniew.bodek@caviumnetworks.com>
Reviewed-by: Jerin Jacob <jerin.jacob@caviumnetworks.com>
This commit is contained in:
Zbigniew Bodek 2017-01-18 21:01:58 +01:00 committed by Thomas Monjalon
parent ead51dc017
commit 54c7fdba7c
5 changed files with 153 additions and 47 deletions
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1
MAINTAINERS
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@ -425,6 +425,7 @@ ARMv8 Crypto PMD
M: Zbigniew Bodek <zbigniew.bodek@caviumnetworks.com>
M: Jerin Jacob <jerin.jacob@caviumnetworks.com>
F: drivers/crypto/armv8/
F: doc/guides/cryptodevs/armv8.rst
Intel AES-NI GCM PMD
M: Declan Doherty <declan.doherty@intel.com>

98
doc/guides/cryptodevs/armv8.rst Normal file
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@ -0,0 +1,98 @@
.. BSD LICENSE
Copyright (C) Cavium networks Ltd. 2017.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
* Neither the name of Cavium networks nor the names of its
contributors may be used to endorse or promote products derived
from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ARMv8 Crypto Poll Mode Driver
=============================
This code provides the initial implementation of the ARMv8 crypto PMD.
The driver uses ARMv8 cryptographic extensions to process chained crypto
operations in an optimized way. The core functionality is provided by
a low-level library, written in the assembly code.
Features
--------
ARMv8 Crypto PMD has support for the following algorithm pairs:
Supported cipher algorithms:
* ``RTE_CRYPTO_CIPHER_AES_CBC``
Supported authentication algorithms:
* ``RTE_CRYPTO_AUTH_SHA1_HMAC``
* ``RTE_CRYPTO_AUTH_SHA256_HMAC``
Installation
------------
In order to enable this virtual crypto PMD, user must:
* Download ARMv8 crypto library source code from
`here <https://github.com/caviumnetworks/armv8_crypto>`_
* Export the environmental variable ARMV8_CRYPTO_LIB_PATH with
the path where the ``armv8_crypto`` library was downloaded
or cloned.
* Build the library by invoking:
.. code-block:: console
make -C $ARMV8_CRYPTO_LIB_PATH/
* Set CONFIG_RTE_LIBRTE_PMD_ARMV8_CRYPTO=y in
config/defconfig_arm64-armv8a-linuxapp-gcc
The corresponding device can be created only if the following features
are supported by the CPU:
* ``RTE_CPUFLAG_AES``
* ``RTE_CPUFLAG_SHA1``
* ``RTE_CPUFLAG_SHA2``
* ``RTE_CPUFLAG_NEON``
Initialization
--------------
User can use app/test application to check how to use this PMD and to verify
crypto processing.
Test name is cryptodev_sw_armv8_autotest.
For performance test cryptodev_sw_armv8_perftest can be used.
Limitations
-----------
* Maximum number of sessions is 2048.
* Only chained operations are supported.
* AES-128-CBC is the only supported cipher variant.
* Cipher input data has to be a multiple of 16 bytes.
* Digest input data has to be a multiple of 8 bytes.

1
doc/guides/cryptodevs/index.rst
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@ -38,6 +38,7 @@ Crypto Device Drivers
overview
aesni_mb
aesni_gcm
armv8
kasumi
openssl
null

94
doc/guides/cryptodevs/overview.rst
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@ -33,70 +33,70 @@ Crypto Device Supported Functionality Matrices
Supported Feature Flags
.. csv-table::
:header: "Feature Flags", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc"
:header: "Feature Flags", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc", "armv8"
:stub-columns: 1
"RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO",x,x,x,x,x,x,x
"RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO",,,,,,,
"RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING",x,x,x,x,x,x,x
"RTE_CRYPTODEV_FF_CPU_SSE",,,x,,x,x,
"RTE_CRYPTODEV_FF_CPU_AVX",,,x,,x,x,
"RTE_CRYPTODEV_FF_CPU_AVX2",,,x,,,,
"RTE_CRYPTODEV_FF_CPU_AVX512",,,x,,,,
"RTE_CRYPTODEV_FF_CPU_AESNI",,,x,x,,,
"RTE_CRYPTODEV_FF_HW_ACCELERATED",x,,,,,,
"RTE_CRYPTODEV_FF_CPU_NEON",,,,,,,
"RTE_CRYPTODEV_FF_CPU_ARM_CE",,,,,,,
"RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO",x,x,x,x,x,x,x,x
"RTE_CRYPTODEV_FF_ASYMMETRIC_CRYPTO",,,,,,,,
"RTE_CRYPTODEV_FF_SYM_OPERATION_CHAINING",x,x,x,x,x,x,x,x
"RTE_CRYPTODEV_FF_CPU_SSE",,,x,,x,x,,
"RTE_CRYPTODEV_FF_CPU_AVX",,,x,,x,x,,
"RTE_CRYPTODEV_FF_CPU_AVX2",,,x,,,,,
"RTE_CRYPTODEV_FF_CPU_AVX512",,,x,,,,,
"RTE_CRYPTODEV_FF_CPU_AESNI",,,x,x,,,,
"RTE_CRYPTODEV_FF_HW_ACCELERATED",x,,,,,,,
"RTE_CRYPTODEV_FF_CPU_NEON",,,,,,,,x
"RTE_CRYPTODEV_FF_CPU_ARM_CE",,,,,,,,x
Supported Cipher Algorithms
.. csv-table::
:header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc"
:header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc", "armv8"
:stub-columns: 1
"NULL",,x,,,,,
"AES_CBC_128",x,,x,,,,
"AES_CBC_192",x,,x,,,,
"AES_CBC_256",x,,x,,,,
"AES_CTR_128",x,,x,,,,
"AES_CTR_192",x,,x,,,,
"AES_CTR_256",x,,x,,,,
"DES_CBC",x,,,,,,
"SNOW3G_UEA2",x,,,,x,,
"KASUMI_F8",,,,,,x,
"ZUC_EEA3",,,,,,,x
"NULL",,x,,,,,,
"AES_CBC_128",x,,x,,,,,x
"AES_CBC_192",x,,x,,,,,
"AES_CBC_256",x,,x,,,,,
"AES_CTR_128",x,,x,,,,,
"AES_CTR_192",x,,x,,,,,
"AES_CTR_256",x,,x,,,,,
"DES_CBC",x,,,,,,,
"SNOW3G_UEA2",x,,,,x,,,
"KASUMI_F8",,,,,,x,,
"ZUC_EEA3",,,,,,,x,
Supported Authentication Algorithms
.. csv-table::
:header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc"
:header: "Cipher Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc", "armv8"
:stub-columns: 1
"NONE",,x,,,,,
"MD5",,,,,,,
"MD5_HMAC",,,x,,,,
"SHA1",,,,,,,
"SHA1_HMAC",x,,x,,,,
"SHA224",,,,,,,
"SHA224_HMAC",,,x,,,,
"SHA256",,,,,,,
"SHA256_HMAC",x,,x,,,,
"SHA384",,,,,,,
"SHA384_HMAC",,,x,,,,
"SHA512",,,,,,,
"SHA512_HMAC",x,,x,,,,
"AES_XCBC",x,,x,,,,
"AES_GMAC",,,,x,,,
"SNOW3G_UIA2",x,,,,x,,
"KASUMI_F9",,,,,,x,
"ZUC_EIA3",,,,,,,x
"NONE",,x,,,,,,
"MD5",,,,,,,,
"MD5_HMAC",,,x,,,,,
"SHA1",,,,,,,,
"SHA1_HMAC",x,,x,,,,,x
"SHA224",,,,,,,,
"SHA224_HMAC",,,x,,,,,
"SHA256",,,,,,,,
"SHA256_HMAC",x,,x,,,,,x
"SHA384",,,,,,,,
"SHA384_HMAC",,,x,,,,,
"SHA512",,,,,,,,
"SHA512_HMAC",x,,x,,,,,
"AES_XCBC",x,,x,,,,,
"AES_GMAC",,,,x,,,,
"SNOW3G_UIA2",x,,,,x,,,
"KASUMI_F9",,,,,,x,,
"ZUC_EIA3",,,,,,,x,
Supported AEAD Algorithms
.. csv-table::
:header: "AEAD Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc"
:header: "AEAD Algorithms", "qat", "null", "aesni_mb", "aesni_gcm", "snow3g", "kasumi", "zuc", "armv8"
:stub-columns: 1
"AES_GCM_128",x,,,x,,,
"AES_GCM_192",x,,,,,,
"AES_GCM_256",x,,,x,,,
"AES_GCM_128",x,,,x,,,,
"AES_GCM_192",x,,,,,,,
"AES_GCM_256",x,,,x,,,,

6
doc/guides/rel_notes/release_17_02.rst
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@ -148,6 +148,12 @@ New Features
See the :ref:`Virtio Interrupt Mode <virtio_interrupt_mode>` documentation
for more information.
* **Added ARMv8 crypto PMD.**
A new crypto PMD has been added, which provides combined mode cryptografic
operations optimized for ARMv8 processors. The driver can be used to enhance
performance in processing chained operations such as cipher + HMAC.
* **Updated the QAT PMD.**
The QAT PMD was updated with additional support for: