net/ice/base: add code to work with the NVM
Add code to read/write/query the NVM image. Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Reviewed-by: Ferruh Yigit <ferruh.yigit@intel.com>
This commit is contained in:
Paul M Stillwell Jr
Ferruh Yigit
parent
c7dd159311
commit
557fa75bcf
387
drivers/net/ice/base/ice_nvm.c
Normal file
387
drivers/net/ice/base/ice_nvm.c
Normal file
@ -0,0 +1,387 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2001-2018
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*/
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#include "ice_common.h"
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/**
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* ice_aq_read_nvm
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* @hw: pointer to the hw struct
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* @module_typeid: module pointer location in words from the NVM beginning
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* @offset: byte offset from the module beginning
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* @length: length of the section to be read (in bytes from the offset)
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* @data: command buffer (size [bytes] = length)
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* @last_command: tells if this is the last command in a series
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* @cd: pointer to command details structure or NULL
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*
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* Read the NVM using the admin queue commands (0x0701)
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*/
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static enum ice_status
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ice_aq_read_nvm(struct ice_hw *hw, u16 module_typeid, u32 offset, u16 length,
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void *data, bool last_command, struct ice_sq_cd *cd)
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{
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struct ice_aq_desc desc;
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struct ice_aqc_nvm *cmd;
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ice_debug(hw, ICE_DBG_TRACE, "ice_aq_read_nvm");
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cmd = &desc.params.nvm;
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/* In offset the highest byte must be zeroed. */
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if (offset & 0xFF000000)
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return ICE_ERR_PARAM;
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ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_read);
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/* If this is the last command in a series, set the proper flag. */
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if (last_command)
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cmd->cmd_flags |= ICE_AQC_NVM_LAST_CMD;
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cmd->module_typeid = CPU_TO_LE16(module_typeid);
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cmd->offset_low = CPU_TO_LE16(offset & 0xFFFF);
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cmd->offset_high = (offset >> 16) & 0xFF;
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cmd->length = CPU_TO_LE16(length);
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return ice_aq_send_cmd(hw, &desc, data, length, cd);
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}
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/**
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* ice_check_sr_access_params - verify params for Shadow RAM R/W operations.
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* @hw: pointer to the HW structure
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* @offset: offset in words from module start
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* @words: number of words to access
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*/
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static enum ice_status
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ice_check_sr_access_params(struct ice_hw *hw, u32 offset, u16 words)
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{
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if ((offset + words) > hw->nvm.sr_words) {
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ice_debug(hw, ICE_DBG_NVM,
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"NVM error: offset beyond SR lmt.\n");
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return ICE_ERR_PARAM;
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}
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if (words > ICE_SR_SECTOR_SIZE_IN_WORDS) {
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/* We can access only up to 4KB (one sector), in one AQ write */
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ice_debug(hw, ICE_DBG_NVM,
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"NVM error: tried to access %d words, limit is %d.\n",
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words, ICE_SR_SECTOR_SIZE_IN_WORDS);
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return ICE_ERR_PARAM;
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}
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if (((offset + (words - 1)) / ICE_SR_SECTOR_SIZE_IN_WORDS) !=
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(offset / ICE_SR_SECTOR_SIZE_IN_WORDS)) {
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/* A single access cannot spread over two sectors */
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ice_debug(hw, ICE_DBG_NVM,
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"NVM error: cannot spread over two sectors.\n");
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return ICE_ERR_PARAM;
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}
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return ICE_SUCCESS;
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}
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/**
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* ice_read_sr_aq - Read Shadow RAM.
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* @hw: pointer to the HW structure
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* @offset: offset in words from module start
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* @words: number of words to read
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* @data: buffer for words reads from Shadow RAM
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* @last_command: tells the AdminQ that this is the last command
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*
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* Reads 16-bit word buffers from the Shadow RAM using the admin command.
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*/
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static enum ice_status
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ice_read_sr_aq(struct ice_hw *hw, u32 offset, u16 words, u16 *data,
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bool last_command)
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{
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enum ice_status status;
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ice_debug(hw, ICE_DBG_TRACE, "ice_read_sr_aq");
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status = ice_check_sr_access_params(hw, offset, words);
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/* values in "offset" and "words" parameters are sized as words
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* (16 bits) but ice_aq_read_nvm expects these values in bytes.
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* So do this conversion while calling ice_aq_read_nvm.
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*/
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if (!status)
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status = ice_aq_read_nvm(hw, 0, 2 * offset, 2 * words, data,
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last_command, NULL);
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return status;
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}
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/**
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* ice_read_sr_word_aq - Reads Shadow RAM via AQ
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
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* @data: word read from the Shadow RAM
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*
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* Reads one 16 bit word from the Shadow RAM using the ice_read_sr_aq method.
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*/
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static enum ice_status
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ice_read_sr_word_aq(struct ice_hw *hw, u16 offset, u16 *data)
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{
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enum ice_status status;
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ice_debug(hw, ICE_DBG_TRACE, "ice_read_sr_word_aq");
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status = ice_read_sr_aq(hw, offset, 1, data, true);
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if (!status)
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*data = LE16_TO_CPU(*(__le16 *)data);
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return status;
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}
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/**
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* ice_read_sr_buf_aq - Reads Shadow RAM buf via AQ
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
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* @words: (in) number of words to read; (out) number of words actually read
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* @data: words read from the Shadow RAM
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*
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* Reads 16 bit words (data buf) from the SR using the ice_read_sr_aq
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* method. Ownership of the NVM is taken before reading the buffer and later
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* released.
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*/
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static enum ice_status
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ice_read_sr_buf_aq(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
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{
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enum ice_status status;
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bool last_cmd = false;
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u16 words_read = 0;
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u16 i = 0;
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ice_debug(hw, ICE_DBG_TRACE, "ice_read_sr_buf_aq");
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do {
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u16 read_size, off_w;
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/* Calculate number of bytes we should read in this step.
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* It's not allowed to read more than one page at a time or
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* to cross page boundaries.
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*/
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off_w = offset % ICE_SR_SECTOR_SIZE_IN_WORDS;
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read_size = off_w ?
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min(*words,
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(u16)(ICE_SR_SECTOR_SIZE_IN_WORDS - off_w)) :
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min((*words - words_read), ICE_SR_SECTOR_SIZE_IN_WORDS);
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/* Check if this is last command, if so set proper flag */
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if ((words_read + read_size) >= *words)
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last_cmd = true;
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status = ice_read_sr_aq(hw, offset, read_size,
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data + words_read, last_cmd);
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if (status)
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goto read_nvm_buf_aq_exit;
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/* Increment counter for words already read and move offset to
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* new read location
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*/
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words_read += read_size;
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offset += read_size;
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} while (words_read < *words);
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for (i = 0; i < *words; i++)
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data[i] = LE16_TO_CPU(((__le16 *)data)[i]);
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read_nvm_buf_aq_exit:
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*words = words_read;
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return status;
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}
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/**
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* ice_acquire_nvm - Generic request for acquiring the NVM ownership
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* @hw: pointer to the HW structure
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* @access: NVM access type (read or write)
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*
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* This function will request NVM ownership.
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*/
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static enum ice_status
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ice_acquire_nvm(struct ice_hw *hw, enum ice_aq_res_access_type access)
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{
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ice_debug(hw, ICE_DBG_TRACE, "ice_acquire_nvm");
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if (hw->nvm.blank_nvm_mode)
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return ICE_SUCCESS;
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return ice_acquire_res(hw, ICE_NVM_RES_ID, access, ICE_NVM_TIMEOUT);
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}
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/**
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* ice_release_nvm - Generic request for releasing the NVM ownership
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* @hw: pointer to the HW structure
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*
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* This function will release NVM ownership.
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*/
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static void ice_release_nvm(struct ice_hw *hw)
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{
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ice_debug(hw, ICE_DBG_TRACE, "ice_release_nvm");
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if (hw->nvm.blank_nvm_mode)
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return;
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ice_release_res(hw, ICE_NVM_RES_ID);
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}
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/**
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* ice_read_sr_word - Reads Shadow RAM word and acquire NVM if necessary
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
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* @data: word read from the Shadow RAM
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*
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* Reads one 16 bit word from the Shadow RAM using the ice_read_sr_word_aq.
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*/
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enum ice_status ice_read_sr_word(struct ice_hw *hw, u16 offset, u16 *data)
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{
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enum ice_status status;
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status = ice_acquire_nvm(hw, ICE_RES_READ);
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if (!status) {
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status = ice_read_sr_word_aq(hw, offset, data);
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ice_release_nvm(hw);
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}
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return status;
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}
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/**
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* ice_init_nvm - initializes NVM setting
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* @hw: pointer to the hw struct
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*
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* This function reads and populates NVM settings such as Shadow RAM size,
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* max_timeout, and blank_nvm_mode
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*/
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enum ice_status ice_init_nvm(struct ice_hw *hw)
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{
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struct ice_nvm_info *nvm = &hw->nvm;
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u16 oem_hi, oem_lo, cfg_ptr;
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u16 eetrack_lo, eetrack_hi;
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enum ice_status status = ICE_SUCCESS;
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u32 fla, gens_stat;
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u8 sr_size;
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ice_debug(hw, ICE_DBG_TRACE, "ice_init_nvm");
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/* The SR size is stored regardless of the nvm programming mode
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* as the blank mode may be used in the factory line.
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*/
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gens_stat = rd32(hw, GLNVM_GENS);
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sr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;
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/* Switching to words (sr_size contains power of 2) */
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nvm->sr_words = BIT(sr_size) * ICE_SR_WORDS_IN_1KB;
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/* Check if we are in the normal or blank NVM programming mode */
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fla = rd32(hw, GLNVM_FLA);
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if (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */
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nvm->blank_nvm_mode = false;
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} else { /* Blank programming mode */
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nvm->blank_nvm_mode = true;
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status = ICE_ERR_NVM_BLANK_MODE;
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ice_debug(hw, ICE_DBG_NVM,
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"NVM init error: unsupported blank mode.\n");
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return status;
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}
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status = ice_read_sr_word(hw, ICE_SR_NVM_DEV_STARTER_VER, &hw->nvm.ver);
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if (status) {
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ice_debug(hw, ICE_DBG_INIT,
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"Failed to read DEV starter version.\n");
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return status;
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}
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status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_LO, &eetrack_lo);
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if (status) {
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ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK lo.\n");
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return status;
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}
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status = ice_read_sr_word(hw, ICE_SR_NVM_EETRACK_HI, &eetrack_hi);
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if (status) {
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ice_debug(hw, ICE_DBG_INIT, "Failed to read EETRACK hi.\n");
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return status;
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}
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hw->nvm.eetrack = (eetrack_hi << 16) | eetrack_lo;
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status = ice_read_sr_word(hw, ICE_SR_BOOT_CFG_PTR, &cfg_ptr);
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if (status) {
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ice_debug(hw, ICE_DBG_INIT, "Failed to read BOOT_CONFIG_PTR.\n");
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return status;
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}
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status = ice_read_sr_word(hw, (cfg_ptr + ICE_NVM_OEM_VER_OFF), &oem_hi);
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if (status) {
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ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER hi.\n");
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return status;
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}
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status = ice_read_sr_word(hw, (cfg_ptr + (ICE_NVM_OEM_VER_OFF + 1)),
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&oem_lo);
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if (status) {
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ice_debug(hw, ICE_DBG_INIT, "Failed to read OEM_VER lo.\n");
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return status;
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}
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hw->nvm.oem_ver = ((u32)oem_hi << 16) | oem_lo;
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return status;
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}
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/**
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* ice_read_sr_buf - Reads Shadow RAM buf and acquire lock if necessary
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
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* @words: (in) number of words to read; (out) number of words actually read
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* @data: words read from the Shadow RAM
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*
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* Reads 16 bit words (data buf) from the SR using the ice_read_nvm_buf_aq
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* method. The buf read is preceded by the NVM ownership take
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* and followed by the release.
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*/
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enum ice_status
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ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data)
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{
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enum ice_status status;
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status = ice_acquire_nvm(hw, ICE_RES_READ);
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if (!status) {
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status = ice_read_sr_buf_aq(hw, offset, words, data);
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ice_release_nvm(hw);
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}
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return status;
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}
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/**
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* ice_nvm_validate_checksum
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* @hw: pointer to the hw struct
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*
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* Verify NVM PFA checksum validity (0x0706)
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*/
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enum ice_status ice_nvm_validate_checksum(struct ice_hw *hw)
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{
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struct ice_aqc_nvm_checksum *cmd;
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struct ice_aq_desc desc;
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enum ice_status status;
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status = ice_acquire_nvm(hw, ICE_RES_READ);
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if (status)
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return status;
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cmd = &desc.params.nvm_checksum;
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ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_nvm_checksum);
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cmd->flags = ICE_AQC_NVM_CHECKSUM_VERIFY;
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status = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
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ice_release_nvm(hw);
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if (!status)
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if (LE16_TO_CPU(cmd->checksum) != ICE_AQC_NVM_CHECKSUM_CORRECT)
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status = ICE_ERR_NVM_CHECKSUM;
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return status;
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}
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