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net/cnxk: support Tx security offload on cn10k

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Add support to create and submit CPT instructions on Tx
on CN10K.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
This commit is contained in:
Nithin Dabilpuram 2021-10-01 19:10:15 +05:30 committed by Jerin Jacob
parent 4382a7ccf7
commit 55bfac717c
9 changed files with 929 additions and 182 deletions
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15
drivers/event/cnxk/cn10k_eventdev.c
View File

@ -17,7 +17,8 @@
#define CN10K_SET_EVDEV_ENQ_OP(dev, enq_op, enq_ops) \
(enq_op = \
enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)] \
enq_ops[!!(dev->tx_offloads & NIX_TX_OFFLOAD_SECURITY_F)] \
[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSTAMP_F)] \
[!!(dev->tx_offloads & NIX_TX_OFFLOAD_TSO_F)] \
[!!(dev->tx_offloads & NIX_TX_OFFLOAD_MBUF_NOFF_F)] \
[!!(dev->tx_offloads & NIX_TX_OFFLOAD_VLAN_QINQ_F)] \
@ -380,17 +381,17 @@ cn10k_sso_fp_fns_set(struct rte_eventdev *event_dev)
/* Tx modes */
const event_tx_adapter_enqueue
sso_hws_tx_adptr_enq[2][2][2][2][2][2] = {
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_##name,
sso_hws_tx_adptr_enq[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_##name,
NIX_TX_FASTPATH_MODES
#undef T
};
const event_tx_adapter_enqueue
sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2] = {
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
[f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
sso_hws_tx_adptr_enq_seg[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = cn10k_sso_hws_tx_adptr_enq_seg_##name,
NIX_TX_FASTPATH_MODES
#undef T
};

72
drivers/event/cnxk/cn10k_worker.h
View File

@ -423,7 +423,11 @@ cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,
((queue[0] ^ queue[1]) & (queue[2] ^ queue[3]))) {
for (j = 0; j < 4; j++) {
uint8_t lnum = 0, loff = 0, shft = 0;
struct rte_mbuf *m = mbufs[i + j];
uintptr_t laddr;
uint16_t segdw;
bool sec;
txq = (struct cn10k_eth_txq *)
txq_data[port[j]][queue[j]];
@ -434,19 +438,35 @@ cn10k_sso_vwqe_split_tx(struct rte_mbuf **mbufs, uint16_t nb_mbufs,
if (flags & NIX_TX_OFFLOAD_TSO_F)
cn10k_nix_xmit_prepare_tso(m, flags);
cn10k_nix_xmit_prepare(m, cmd, lmt_addr, flags,
txq->lso_tun_fmt);
cn10k_nix_xmit_prepare(m, cmd, flags,
txq->lso_tun_fmt, &sec);
laddr = lmt_addr;
/* Prepare CPT instruction and get nixtx addr if
* it is for CPT on same lmtline.
*/
if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
cn10k_nix_prep_sec(m, cmd, &laddr,
lmt_addr, &lnum,
&loff, &shft,
txq->sa_base, flags);
/* Move NIX desc to LMT/NIXTX area */
cn10k_nix_xmit_mv_lmt_base(laddr, cmd, flags);
if (flags & NIX_TX_MULTI_SEG_F) {
const uint16_t segdw =
cn10k_nix_prepare_mseg(
m, (uint64_t *)lmt_addr,
flags);
pa = txq->io_addr | ((segdw - 1) << 4);
segdw = cn10k_nix_prepare_mseg(m,
(uint64_t *)laddr, flags);
} else {
pa = txq->io_addr |
(cn10k_nix_tx_ext_subs(flags) + 1)
<< 4;
segdw = cn10k_nix_tx_ext_subs(flags) +
2;
}
if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
pa = txq->cpt_io_addr | 3 << 4;
else
pa = txq->io_addr | ((segdw - 1) << 4);
if (!sched_type)
roc_sso_hws_head_wait(base +
SSOW_LF_GWS_TAG);
@ -469,15 +489,19 @@ cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
const uint64_t txq_data[][RTE_MAX_QUEUES_PER_PORT],
const uint32_t flags)
{
uint8_t lnum = 0, loff = 0, shft = 0;
struct cn10k_eth_txq *txq;
uint16_t ref_cnt, segdw;
struct rte_mbuf *m;
uintptr_t lmt_addr;
uint16_t ref_cnt;
uintptr_t c_laddr;
uint16_t lmt_id;
uintptr_t pa;
bool sec;
lmt_addr = ws->lmt_base;
ROC_LMT_BASE_ID_GET(lmt_addr, lmt_id);
c_laddr = lmt_addr;
if (ev->event_type & RTE_EVENT_TYPE_VECTOR) {
struct rte_mbuf **mbufs = ev->vec->mbufs;
@ -508,14 +532,28 @@ cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
if (flags & NIX_TX_OFFLOAD_TSO_F)
cn10k_nix_xmit_prepare_tso(m, flags);
cn10k_nix_xmit_prepare(m, cmd, lmt_addr, flags, txq->lso_tun_fmt);
cn10k_nix_xmit_prepare(m, cmd, flags, txq->lso_tun_fmt, &sec);
/* Prepare CPT instruction and get nixtx addr if
* it is for CPT on same lmtline.
*/
if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
cn10k_nix_prep_sec(m, cmd, &lmt_addr, c_laddr, &lnum, &loff,
&shft, txq->sa_base, flags);
/* Move NIX desc to LMT/NIXTX area */
cn10k_nix_xmit_mv_lmt_base(lmt_addr, cmd, flags);
if (flags & NIX_TX_MULTI_SEG_F) {
const uint16_t segdw =
cn10k_nix_prepare_mseg(m, (uint64_t *)lmt_addr, flags);
pa = txq->io_addr | ((segdw - 1) << 4);
segdw = cn10k_nix_prepare_mseg(m, (uint64_t *)lmt_addr, flags);
} else {
pa = txq->io_addr | (cn10k_nix_tx_ext_subs(flags) + 1) << 4;
segdw = cn10k_nix_tx_ext_subs(flags) + 2;
}
if (flags & NIX_TX_OFFLOAD_SECURITY_F && sec)
pa = txq->cpt_io_addr | 3 << 4;
else
pa = txq->io_addr | ((segdw - 1) << 4);
if (!ev->sched_type)
roc_sso_hws_head_wait(ws->tx_base + SSOW_LF_GWS_TAG);
@ -531,7 +569,7 @@ cn10k_sso_hws_event_tx(struct cn10k_sso_hws *ws, struct rte_event *ev,
return 1;
}
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_##name( \
void *port, struct rte_event ev[], uint16_t nb_events); \
uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_seg_##name( \

2
drivers/event/cnxk/cn10k_worker_tx_enq.c
View File

@ -4,7 +4,7 @@
#include "cn10k_worker.h"
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_##name( \
void *port, struct rte_event ev[], uint16_t nb_events) \
{ \

2
drivers/event/cnxk/cn10k_worker_tx_enq_seg.c
View File

@ -4,7 +4,7 @@
#include "cn10k_worker.h"
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
uint16_t __rte_hot cn10k_sso_hws_tx_adptr_enq_seg_##name( \
void *port, struct rte_event ev[], uint16_t nb_events) \
{ \

31
drivers/net/cnxk/cn10k_tx.c
View File

@ -5,7 +5,7 @@
#include "cn10k_ethdev.h"
#include "cn10k_tx.h"
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
uint16_t __rte_noinline __rte_hot cn10k_nix_xmit_pkts_##name( \
void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts) \
{ \
@ -24,12 +24,13 @@ NIX_TX_FASTPATH_MODES
static inline void
pick_tx_func(struct rte_eth_dev *eth_dev,
const eth_tx_burst_t tx_burst[2][2][2][2][2][2])
const eth_tx_burst_t tx_burst[2][2][2][2][2][2][2])
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
/* [TSP] [TSO] [NOFF] [VLAN] [OL3_OL4_CSUM] [IL3_IL4_CSUM] */
/* [SEC] [TSP] [TSO] [NOFF] [VLAN] [OL3_OL4_CSUM] [IL3_IL4_CSUM] */
eth_dev->tx_pkt_burst = tx_burst
[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_SECURITY_F)]
[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSTAMP_F)]
[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_TSO_F)]
[!!(dev->tx_offload_flags & NIX_TX_OFFLOAD_MBUF_NOFF_F)]
@ -43,33 +44,33 @@ cn10k_eth_set_tx_function(struct rte_eth_dev *eth_dev)
{
struct cnxk_eth_dev *dev = cnxk_eth_pmd_priv(eth_dev);
const eth_tx_burst_t nix_eth_tx_burst[2][2][2][2][2][2] = {
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
[f5][f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_##name,
const eth_tx_burst_t nix_eth_tx_burst[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_##name,
NIX_TX_FASTPATH_MODES
#undef T
};
const eth_tx_burst_t nix_eth_tx_burst_mseg[2][2][2][2][2][2] = {
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
[f5][f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_mseg_##name,
const eth_tx_burst_t nix_eth_tx_burst_mseg[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_mseg_##name,
NIX_TX_FASTPATH_MODES
#undef T
};
const eth_tx_burst_t nix_eth_tx_vec_burst[2][2][2][2][2][2] = {
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
[f5][f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_vec_##name,
const eth_tx_burst_t nix_eth_tx_vec_burst[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_vec_##name,
NIX_TX_FASTPATH_MODES
#undef T
};
const eth_tx_burst_t nix_eth_tx_vec_burst_mseg[2][2][2][2][2][2] = {
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
[f5][f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_vec_mseg_##name,
const eth_tx_burst_t nix_eth_tx_vec_burst_mseg[2][2][2][2][2][2][2] = {
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
[f6][f5][f4][f3][f2][f1][f0] = cn10k_nix_xmit_pkts_vec_mseg_##name,
NIX_TX_FASTPATH_MODES
#undef T

983
drivers/net/cnxk/cn10k_tx.h
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File diff suppressed because it is too large Load Diff

2
drivers/net/cnxk/cn10k_tx_mseg.c
View File

@ -5,7 +5,7 @@
#include "cn10k_ethdev.h"
#include "cn10k_tx.h"
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
uint16_t __rte_noinline __rte_hot \
cn10k_nix_xmit_pkts_mseg_##name(void *tx_queue, \
struct rte_mbuf **tx_pkts, \

2
drivers/net/cnxk/cn10k_tx_vec.c
View File

@ -5,7 +5,7 @@
#include "cn10k_ethdev.h"
#include "cn10k_tx.h"
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
uint16_t __rte_noinline __rte_hot \
cn10k_nix_xmit_pkts_vec_##name(void *tx_queue, \
struct rte_mbuf **tx_pkts, \

2
drivers/net/cnxk/cn10k_tx_vec_mseg.c
View File

@ -5,7 +5,7 @@
#include "cn10k_ethdev.h"
#include "cn10k_tx.h"
#define T(name, f5, f4, f3, f2, f1, f0, sz, flags) \
#define T(name, f6, f5, f4, f3, f2, f1, f0, sz, flags) \
uint16_t __rte_noinline __rte_hot cn10k_nix_xmit_pkts_vec_mseg_##name( \
void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t pkts) \
{ \