common/cnxk: add VF support to base device class
Add VF specific handling such as BAR4 setup, forwarding VF mbox messages to AF and vice-versa, VF FLR handling etc. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Acked-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
This commit is contained in:
Jerin Jacob
parent
665ff1ccc2
commit
585bb3e538
@ -17,6 +17,337 @@
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/* Single Root I/O Virtualization */
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#define ROC_PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
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static void *
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mbox_mem_map(off_t off, size_t size)
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{
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void *va = MAP_FAILED;
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int mem_fd;
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if (size <= 0 || !off) {
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plt_err("Invalid mbox area off 0x%lx size %lu", off, size);
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goto error;
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}
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mem_fd = open("/dev/mem", O_RDWR);
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if (mem_fd < 0)
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goto error;
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va = plt_mmap(NULL, size, PLT_PROT_READ | PLT_PROT_WRITE,
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PLT_MAP_SHARED, mem_fd, off);
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close(mem_fd);
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if (va == MAP_FAILED)
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plt_err("Failed to mmap sz=0x%zx, fd=%d, off=%jd", size, mem_fd,
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(intmax_t)off);
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error:
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return va;
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}
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static void
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mbox_mem_unmap(void *va, size_t size)
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{
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if (va)
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munmap(va, size);
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}
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static int
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pf_af_sync_msg(struct dev *dev, struct mbox_msghdr **rsp)
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{
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uint32_t timeout = 0, sleep = 1;
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struct mbox *mbox = dev->mbox;
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struct mbox_dev *mdev = &mbox->dev[0];
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volatile uint64_t int_status;
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struct mbox_msghdr *msghdr;
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uint64_t off;
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int rc = 0;
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/* We need to disable PF interrupts. We are in timer interrupt */
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plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
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/* Send message */
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mbox_msg_send(mbox, 0);
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do {
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plt_delay_ms(sleep);
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timeout += sleep;
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if (timeout >= mbox->rsp_tmo) {
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plt_err("Message timeout: %dms", mbox->rsp_tmo);
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rc = -EIO;
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break;
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}
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int_status = plt_read64(dev->bar2 + RVU_PF_INT);
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} while ((int_status & 0x1) != 0x1);
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/* Clear */
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plt_write64(int_status, dev->bar2 + RVU_PF_INT);
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/* Enable interrupts */
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plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
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if (rc == 0) {
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/* Get message */
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off = mbox->rx_start +
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PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
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msghdr = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + off);
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if (rsp)
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*rsp = msghdr;
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rc = msghdr->rc;
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}
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return rc;
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}
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static int
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af_pf_wait_msg(struct dev *dev, uint16_t vf, int num_msg)
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{
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uint32_t timeout = 0, sleep = 1;
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struct mbox *mbox = dev->mbox;
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struct mbox_dev *mdev = &mbox->dev[0];
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volatile uint64_t int_status;
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struct mbox_hdr *req_hdr;
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struct mbox_msghdr *msg;
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struct mbox_msghdr *rsp;
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uint64_t offset;
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size_t size;
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int i;
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/* We need to disable PF interrupts. We are in timer interrupt */
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plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
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/* Send message */
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mbox_msg_send(mbox, 0);
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do {
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plt_delay_ms(sleep);
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timeout++;
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if (timeout >= mbox->rsp_tmo) {
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plt_err("Routed messages %d timeout: %dms", num_msg,
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mbox->rsp_tmo);
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break;
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}
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int_status = plt_read64(dev->bar2 + RVU_PF_INT);
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} while ((int_status & 0x1) != 0x1);
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/* Clear */
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plt_write64(~0ull, dev->bar2 + RVU_PF_INT);
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/* Enable interrupts */
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plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
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plt_spinlock_lock(&mdev->mbox_lock);
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req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
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if (req_hdr->num_msgs != num_msg)
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plt_err("Routed messages: %d received: %d", num_msg,
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req_hdr->num_msgs);
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/* Get messages from mbox */
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offset = mbox->rx_start +
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PLT_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
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for (i = 0; i < req_hdr->num_msgs; i++) {
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msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
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size = mbox->rx_start + msg->next_msgoff - offset;
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/* Reserve PF/VF mbox message */
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size = PLT_ALIGN(size, MBOX_MSG_ALIGN);
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rsp = mbox_alloc_msg(&dev->mbox_vfpf, vf, size);
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mbox_rsp_init(msg->id, rsp);
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/* Copy message from AF<->PF mbox to PF<->VF mbox */
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mbox_memcpy((uint8_t *)rsp + sizeof(struct mbox_msghdr),
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(uint8_t *)msg + sizeof(struct mbox_msghdr),
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size - sizeof(struct mbox_msghdr));
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/* Set status and sender pf_func data */
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rsp->rc = msg->rc;
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rsp->pcifunc = msg->pcifunc;
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offset = mbox->rx_start + msg->next_msgoff;
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}
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plt_spinlock_unlock(&mdev->mbox_lock);
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return req_hdr->num_msgs;
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}
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static int
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vf_pf_process_msgs(struct dev *dev, uint16_t vf)
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{
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struct mbox *mbox = &dev->mbox_vfpf;
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struct mbox_dev *mdev = &mbox->dev[vf];
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struct mbox_hdr *req_hdr;
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struct mbox_msghdr *msg;
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int offset, routed = 0;
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size_t size;
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uint16_t i;
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req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
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if (!req_hdr->num_msgs)
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return 0;
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offset = mbox->rx_start + PLT_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
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for (i = 0; i < req_hdr->num_msgs; i++) {
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msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
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size = mbox->rx_start + msg->next_msgoff - offset;
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/* RVU_PF_FUNC_S */
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msg->pcifunc = dev_pf_func(dev->pf, vf);
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if (msg->id == MBOX_MSG_READY) {
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struct ready_msg_rsp *rsp;
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uint16_t max_bits = sizeof(dev->active_vfs[0]) * 8;
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/* Handle READY message in PF */
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dev->active_vfs[vf / max_bits] |=
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BIT_ULL(vf % max_bits);
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rsp = (struct ready_msg_rsp *)mbox_alloc_msg(
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mbox, vf, sizeof(*rsp));
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mbox_rsp_init(msg->id, rsp);
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/* PF/VF function ID */
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rsp->hdr.pcifunc = msg->pcifunc;
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rsp->hdr.rc = 0;
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} else {
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struct mbox_msghdr *af_req;
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/* Reserve AF/PF mbox message */
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size = PLT_ALIGN(size, MBOX_MSG_ALIGN);
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af_req = mbox_alloc_msg(dev->mbox, 0, size);
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if (af_req == NULL)
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return -ENOSPC;
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mbox_req_init(msg->id, af_req);
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/* Copy message from VF<->PF mbox to PF<->AF mbox */
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mbox_memcpy((uint8_t *)af_req +
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sizeof(struct mbox_msghdr),
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(uint8_t *)msg + sizeof(struct mbox_msghdr),
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size - sizeof(struct mbox_msghdr));
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af_req->pcifunc = msg->pcifunc;
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routed++;
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}
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offset = mbox->rx_start + msg->next_msgoff;
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}
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if (routed > 0) {
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plt_base_dbg("pf:%d routed %d messages from vf:%d to AF",
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dev->pf, routed, vf);
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af_pf_wait_msg(dev, vf, routed);
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mbox_reset(dev->mbox, 0);
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}
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/* Send mbox responses to VF */
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if (mdev->num_msgs) {
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plt_base_dbg("pf:%d reply %d messages to vf:%d", dev->pf,
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mdev->num_msgs, vf);
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mbox_msg_send(mbox, vf);
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}
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return i;
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}
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static int
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vf_pf_process_up_msgs(struct dev *dev, uint16_t vf)
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{
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struct mbox *mbox = &dev->mbox_vfpf_up;
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struct mbox_dev *mdev = &mbox->dev[vf];
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struct mbox_hdr *req_hdr;
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struct mbox_msghdr *msg;
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int msgs_acked = 0;
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int offset;
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uint16_t i;
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req_hdr = (struct mbox_hdr *)((uintptr_t)mdev->mbase + mbox->rx_start);
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if (req_hdr->num_msgs == 0)
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return 0;
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offset = mbox->rx_start + PLT_ALIGN(sizeof(*req_hdr), MBOX_MSG_ALIGN);
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for (i = 0; i < req_hdr->num_msgs; i++) {
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msg = (struct mbox_msghdr *)((uintptr_t)mdev->mbase + offset);
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msgs_acked++;
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/* RVU_PF_FUNC_S */
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msg->pcifunc = dev_pf_func(dev->pf, vf);
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switch (msg->id) {
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case MBOX_MSG_CGX_LINK_EVENT:
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plt_base_dbg("PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)",
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msg->id, mbox_id2name(msg->id),
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msg->pcifunc, dev_get_pf(msg->pcifunc),
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dev_get_vf(msg->pcifunc));
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break;
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case MBOX_MSG_CGX_PTP_RX_INFO:
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plt_base_dbg("PF: Msg 0x%x (%s) fn:0x%x (pf:%d,vf:%d)",
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msg->id, mbox_id2name(msg->id),
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msg->pcifunc, dev_get_pf(msg->pcifunc),
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dev_get_vf(msg->pcifunc));
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break;
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default:
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plt_err("Not handled UP msg 0x%x (%s) func:0x%x",
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msg->id, mbox_id2name(msg->id), msg->pcifunc);
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}
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offset = mbox->rx_start + msg->next_msgoff;
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}
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mbox_reset(mbox, vf);
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mdev->msgs_acked = msgs_acked;
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plt_wmb();
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return i;
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}
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static void
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roc_vf_pf_mbox_handle_msg(void *param)
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{
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uint16_t vf, max_vf, max_bits;
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struct dev *dev = param;
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max_bits = sizeof(dev->intr.bits[0]) * sizeof(uint64_t);
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max_vf = max_bits * MAX_VFPF_DWORD_BITS;
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for (vf = 0; vf < max_vf; vf++) {
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if (dev->intr.bits[vf / max_bits] & BIT_ULL(vf % max_bits)) {
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plt_base_dbg("Process vf:%d request (pf:%d, vf:%d)", vf,
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dev->pf, dev->vf);
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vf_pf_process_msgs(dev, vf);
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/* UP messages */
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vf_pf_process_up_msgs(dev, vf);
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dev->intr.bits[vf / max_bits] &=
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~(BIT_ULL(vf % max_bits));
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}
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}
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dev->timer_set = 0;
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}
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static void
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roc_vf_pf_mbox_irq(void *param)
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{
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struct dev *dev = param;
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bool alarm_set = false;
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uint64_t intr;
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int vfpf;
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for (vfpf = 0; vfpf < MAX_VFPF_DWORD_BITS; ++vfpf) {
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intr = plt_read64(dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
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if (!intr)
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continue;
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plt_base_dbg("vfpf: %d intr: 0x%" PRIx64 " (pf:%d, vf:%d)",
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vfpf, intr, dev->pf, dev->vf);
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/* Save and clear intr bits */
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dev->intr.bits[vfpf] |= intr;
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plt_write64(intr, dev->bar2 + RVU_PF_VFPF_MBOX_INTX(vfpf));
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alarm_set = true;
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}
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if (!dev->timer_set && alarm_set) {
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dev->timer_set = 1;
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/* Start timer to handle messages */
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plt_alarm_set(VF_PF_MBOX_TIMER_MS, roc_vf_pf_mbox_handle_msg,
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dev);
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}
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}
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static void
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process_msgs(struct dev *dev, struct mbox *mbox)
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{
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@ -62,6 +393,112 @@ process_msgs(struct dev *dev, struct mbox *mbox)
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plt_wmb();
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}
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/* Copies the message received from AF and sends it to VF */
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static void
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pf_vf_mbox_send_up_msg(struct dev *dev, void *rec_msg)
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{
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uint16_t max_bits = sizeof(dev->active_vfs[0]) * sizeof(uint64_t);
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struct mbox *vf_mbox = &dev->mbox_vfpf_up;
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struct msg_req *msg = rec_msg;
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struct mbox_msghdr *vf_msg;
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uint16_t vf;
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size_t size;
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size = PLT_ALIGN(mbox_id2size(msg->hdr.id), MBOX_MSG_ALIGN);
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/* Send UP message to all VF's */
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for (vf = 0; vf < vf_mbox->ndevs; vf++) {
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/* VF active */
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if (!(dev->active_vfs[vf / max_bits] & (BIT_ULL(vf))))
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continue;
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plt_base_dbg("(%s) size: %zx to VF: %d",
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mbox_id2name(msg->hdr.id), size, vf);
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/* Reserve PF/VF mbox message */
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vf_msg = mbox_alloc_msg(vf_mbox, vf, size);
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if (!vf_msg) {
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plt_err("Failed to alloc VF%d UP message", vf);
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continue;
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}
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mbox_req_init(msg->hdr.id, vf_msg);
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/*
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* Copy message from AF<->PF UP mbox
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* to PF<->VF UP mbox
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*/
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mbox_memcpy((uint8_t *)vf_msg + sizeof(struct mbox_msghdr),
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(uint8_t *)msg + sizeof(struct mbox_msghdr),
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size - sizeof(struct mbox_msghdr));
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vf_msg->rc = msg->hdr.rc;
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/* Set PF to be a sender */
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vf_msg->pcifunc = dev->pf_func;
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/* Send to VF */
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mbox_msg_send(vf_mbox, vf);
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}
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}
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static int
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mbox_up_handler_cgx_link_event(struct dev *dev, struct cgx_link_info_msg *msg,
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struct msg_rsp *rsp)
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{
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struct cgx_link_user_info *linfo = &msg->link_info;
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void *roc_nix = dev->roc_nix;
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plt_base_dbg("pf:%d/vf:%d NIC Link %s --> 0x%x (%s) from: pf:%d/vf:%d",
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dev_get_pf(dev->pf_func), dev_get_vf(dev->pf_func),
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linfo->link_up ? "UP" : "DOWN", msg->hdr.id,
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mbox_id2name(msg->hdr.id), dev_get_pf(msg->hdr.pcifunc),
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dev_get_vf(msg->hdr.pcifunc));
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/* PF gets link notification from AF */
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if (dev_get_pf(msg->hdr.pcifunc) == 0) {
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if (dev->ops && dev->ops->link_status_update)
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dev->ops->link_status_update(roc_nix, linfo);
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/* Forward the same message as received from AF to VF */
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pf_vf_mbox_send_up_msg(dev, msg);
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} else {
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/* VF gets link up notification */
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if (dev->ops && dev->ops->link_status_update)
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dev->ops->link_status_update(roc_nix, linfo);
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}
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rsp->hdr.rc = 0;
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return 0;
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}
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static int
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mbox_up_handler_cgx_ptp_rx_info(struct dev *dev,
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struct cgx_ptp_rx_info_msg *msg,
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struct msg_rsp *rsp)
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{
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void *roc_nix = dev->roc_nix;
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plt_base_dbg("pf:%d/vf:%d PTP mode %s --> 0x%x (%s) from: pf:%d/vf:%d",
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dev_get_pf(dev->pf_func), dev_get_vf(dev->pf_func),
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msg->ptp_en ? "ENABLED" : "DISABLED", msg->hdr.id,
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mbox_id2name(msg->hdr.id), dev_get_pf(msg->hdr.pcifunc),
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dev_get_vf(msg->hdr.pcifunc));
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/* PF gets PTP notification from AF */
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if (dev_get_pf(msg->hdr.pcifunc) == 0) {
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if (dev->ops && dev->ops->ptp_info_update)
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dev->ops->ptp_info_update(roc_nix, msg->ptp_en);
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/* Forward the same message as received from AF to VF */
|
||||
pf_vf_mbox_send_up_msg(dev, msg);
|
||||
} else {
|
||||
/* VF gets PTP notification */
|
||||
if (dev->ops && dev->ops->ptp_info_update)
|
||||
dev->ops->ptp_info_update(roc_nix, msg->ptp_en);
|
||||
}
|
||||
|
||||
rsp->hdr.rc = 0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
mbox_process_msgs_up(struct dev *dev, struct mbox_msghdr *req)
|
||||
{
|
||||
@ -73,6 +510,24 @@ mbox_process_msgs_up(struct dev *dev, struct mbox_msghdr *req)
|
||||
default:
|
||||
reply_invalid_msg(&dev->mbox_up, 0, 0, req->id);
|
||||
break;
|
||||
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
|
||||
case _id: { \
|
||||
struct _rsp_type *rsp; \
|
||||
int err; \
|
||||
rsp = (struct _rsp_type *)mbox_alloc_msg( \
|
||||
&dev->mbox_up, 0, sizeof(struct _rsp_type)); \
|
||||
if (!rsp) \
|
||||
return -ENOMEM; \
|
||||
rsp->hdr.id = _id; \
|
||||
rsp->hdr.sig = MBOX_RSP_SIG; \
|
||||
rsp->hdr.pcifunc = dev->pf_func; \
|
||||
rsp->hdr.rc = 0; \
|
||||
err = mbox_up_handler_##_fn_name(dev, (struct _req_type *)req, \
|
||||
rsp); \
|
||||
return err; \
|
||||
}
|
||||
MBOX_UP_CGX_MESSAGES
|
||||
#undef M
|
||||
}
|
||||
|
||||
return -ENODEV;
|
||||
@ -110,6 +565,26 @@ process_msgs_up(struct dev *dev, struct mbox *mbox)
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
roc_pf_vf_mbox_irq(void *param)
|
||||
{
|
||||
struct dev *dev = param;
|
||||
uint64_t intr;
|
||||
|
||||
intr = plt_read64(dev->bar2 + RVU_VF_INT);
|
||||
if (intr == 0)
|
||||
plt_base_dbg("Proceeding to check mbox UP messages if any");
|
||||
|
||||
plt_write64(intr, dev->bar2 + RVU_VF_INT);
|
||||
plt_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
|
||||
|
||||
/* First process all configuration messages */
|
||||
process_msgs(dev, dev->mbox);
|
||||
|
||||
/* Process Uplink messages */
|
||||
process_msgs_up(dev, &dev->mbox_up);
|
||||
}
|
||||
|
||||
static void
|
||||
roc_af_pf_mbox_irq(void *param)
|
||||
{
|
||||
@ -121,7 +596,7 @@ roc_af_pf_mbox_irq(void *param)
|
||||
plt_base_dbg("Proceeding to check mbox UP messages if any");
|
||||
|
||||
plt_write64(intr, dev->bar2 + RVU_PF_INT);
|
||||
plt_base_dbg("Irq 0x%" PRIx64 "(pf:%d)", intr, dev->pf);
|
||||
plt_base_dbg("Irq 0x%" PRIx64 "(pf:%d,vf:%d)", intr, dev->pf, dev->vf);
|
||||
|
||||
/* First process all configuration messages */
|
||||
process_msgs(dev, dev->mbox);
|
||||
@ -134,10 +609,33 @@ static int
|
||||
mbox_register_pf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
|
||||
int rc;
|
||||
int i, rc;
|
||||
|
||||
/* HW clear irq */
|
||||
for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
|
||||
plt_write64(~0ull,
|
||||
dev->bar2 + RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
|
||||
|
||||
plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
|
||||
|
||||
dev->timer_set = 0;
|
||||
|
||||
/* MBOX interrupt for VF(0...63) <-> PF */
|
||||
rc = dev_irq_register(intr_handle, roc_vf_pf_mbox_irq, dev,
|
||||
RVU_PF_INT_VEC_VFPF_MBOX0);
|
||||
|
||||
if (rc) {
|
||||
plt_err("Fail to register PF(VF0-63) mbox irq");
|
||||
return rc;
|
||||
}
|
||||
/* MBOX interrupt for VF(64...128) <-> PF */
|
||||
rc = dev_irq_register(intr_handle, roc_vf_pf_mbox_irq, dev,
|
||||
RVU_PF_INT_VEC_VFPF_MBOX1);
|
||||
|
||||
if (rc) {
|
||||
plt_err("Fail to register PF(VF64-128) mbox irq");
|
||||
return rc;
|
||||
}
|
||||
/* MBOX interrupt AF <-> PF */
|
||||
rc = dev_irq_register(intr_handle, roc_af_pf_mbox_irq, dev,
|
||||
RVU_PF_INT_VEC_AFPF_MBOX);
|
||||
@ -146,15 +644,47 @@ mbox_register_pf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* HW enable intr */
|
||||
for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
|
||||
plt_write64(~0ull,
|
||||
dev->bar2 + RVU_PF_VFPF_MBOX_INT_ENA_W1SX(i));
|
||||
|
||||
plt_write64(~0ull, dev->bar2 + RVU_PF_INT);
|
||||
plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1S);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int
|
||||
mbox_register_vf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
|
||||
int rc;
|
||||
|
||||
/* Clear irq */
|
||||
plt_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
|
||||
|
||||
/* MBOX interrupt PF <-> VF */
|
||||
rc = dev_irq_register(intr_handle, roc_pf_vf_mbox_irq, dev,
|
||||
RVU_VF_INT_VEC_MBOX);
|
||||
if (rc) {
|
||||
plt_err("Fail to register PF<->VF mbox irq");
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* HW enable intr */
|
||||
plt_write64(~0ull, dev->bar2 + RVU_VF_INT);
|
||||
plt_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1S);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int
|
||||
mbox_register_irq(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
if (dev_is_vf(dev))
|
||||
return mbox_register_vf_irq(pci_dev, dev);
|
||||
else
|
||||
return mbox_register_pf_irq(pci_dev, dev);
|
||||
}
|
||||
|
||||
@ -162,20 +692,229 @@ static void
|
||||
mbox_unregister_pf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
|
||||
int i;
|
||||
|
||||
/* HW clear irq */
|
||||
for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i)
|
||||
plt_write64(~0ull,
|
||||
dev->bar2 + RVU_PF_VFPF_MBOX_INT_ENA_W1CX(i));
|
||||
|
||||
plt_write64(~0ull, dev->bar2 + RVU_PF_INT_ENA_W1C);
|
||||
|
||||
dev->timer_set = 0;
|
||||
|
||||
plt_alarm_cancel(roc_vf_pf_mbox_handle_msg, dev);
|
||||
|
||||
/* Unregister the interrupt handler for each vectors */
|
||||
/* MBOX interrupt for VF(0...63) <-> PF */
|
||||
dev_irq_unregister(intr_handle, roc_vf_pf_mbox_irq, dev,
|
||||
RVU_PF_INT_VEC_VFPF_MBOX0);
|
||||
|
||||
/* MBOX interrupt for VF(64...128) <-> PF */
|
||||
dev_irq_unregister(intr_handle, roc_vf_pf_mbox_irq, dev,
|
||||
RVU_PF_INT_VEC_VFPF_MBOX1);
|
||||
|
||||
/* MBOX interrupt AF <-> PF */
|
||||
dev_irq_unregister(intr_handle, roc_af_pf_mbox_irq, dev,
|
||||
RVU_PF_INT_VEC_AFPF_MBOX);
|
||||
}
|
||||
|
||||
static void
|
||||
mbox_unregister_vf_irq(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
|
||||
|
||||
/* Clear irq */
|
||||
plt_write64(~0ull, dev->bar2 + RVU_VF_INT_ENA_W1C);
|
||||
|
||||
/* Unregister the interrupt handler */
|
||||
dev_irq_unregister(intr_handle, roc_pf_vf_mbox_irq, dev,
|
||||
RVU_VF_INT_VEC_MBOX);
|
||||
}
|
||||
|
||||
static void
|
||||
mbox_unregister_irq(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
if (dev_is_vf(dev))
|
||||
mbox_unregister_vf_irq(pci_dev, dev);
|
||||
else
|
||||
mbox_unregister_pf_irq(pci_dev, dev);
|
||||
}
|
||||
|
||||
static int
|
||||
vf_flr_send_msg(struct dev *dev, uint16_t vf)
|
||||
{
|
||||
struct mbox *mbox = dev->mbox;
|
||||
struct msg_req *req;
|
||||
int rc;
|
||||
|
||||
req = mbox_alloc_msg_vf_flr(mbox);
|
||||
if (req == NULL)
|
||||
return -ENOSPC;
|
||||
/* Overwrite pcifunc to indicate VF */
|
||||
req->hdr.pcifunc = dev_pf_func(dev->pf, vf);
|
||||
|
||||
/* Sync message in interrupt context */
|
||||
rc = pf_af_sync_msg(dev, NULL);
|
||||
if (rc)
|
||||
plt_err("Failed to send VF FLR mbox msg, rc=%d", rc);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
static void
|
||||
roc_pf_vf_flr_irq(void *param)
|
||||
{
|
||||
struct dev *dev = (struct dev *)param;
|
||||
uint16_t max_vf = 64, vf;
|
||||
uintptr_t bar2;
|
||||
uint64_t intr;
|
||||
int i;
|
||||
|
||||
max_vf = (dev->maxvf > 0) ? dev->maxvf : 64;
|
||||
bar2 = dev->bar2;
|
||||
|
||||
plt_base_dbg("FLR VF interrupt: max_vf: %d", max_vf);
|
||||
|
||||
for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {
|
||||
intr = plt_read64(bar2 + RVU_PF_VFFLR_INTX(i));
|
||||
if (!intr)
|
||||
continue;
|
||||
|
||||
for (vf = 0; vf < max_vf; vf++) {
|
||||
if (!(intr & (1ULL << vf)))
|
||||
continue;
|
||||
|
||||
plt_base_dbg("FLR: i :%d intr: 0x%" PRIx64 ", vf-%d", i,
|
||||
intr, (64 * i + vf));
|
||||
/* Clear interrupt */
|
||||
plt_write64(BIT_ULL(vf), bar2 + RVU_PF_VFFLR_INTX(i));
|
||||
/* Disable the interrupt */
|
||||
plt_write64(BIT_ULL(vf),
|
||||
bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));
|
||||
/* Inform AF about VF reset */
|
||||
vf_flr_send_msg(dev, vf);
|
||||
|
||||
/* Signal FLR finish */
|
||||
plt_write64(BIT_ULL(vf), bar2 + RVU_PF_VFTRPENDX(i));
|
||||
/* Enable interrupt */
|
||||
plt_write64(~0ull, bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
vf_flr_unregister_irqs(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
struct plt_intr_handle *intr_handle = &pci_dev->intr_handle;
|
||||
int i;
|
||||
|
||||
plt_base_dbg("Unregister VF FLR interrupts for %s", pci_dev->name);
|
||||
|
||||
/* HW clear irq */
|
||||
for (i = 0; i < MAX_VFPF_DWORD_BITS; i++)
|
||||
plt_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1CX(i));
|
||||
|
||||
dev_irq_unregister(intr_handle, roc_pf_vf_flr_irq, dev,
|
||||
RVU_PF_INT_VEC_VFFLR0);
|
||||
|
||||
dev_irq_unregister(intr_handle, roc_pf_vf_flr_irq, dev,
|
||||
RVU_PF_INT_VEC_VFFLR1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
vf_flr_register_irqs(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
struct plt_intr_handle *handle = &pci_dev->intr_handle;
|
||||
int i, rc;
|
||||
|
||||
plt_base_dbg("Register VF FLR interrupts for %s", pci_dev->name);
|
||||
|
||||
rc = dev_irq_register(handle, roc_pf_vf_flr_irq, dev,
|
||||
RVU_PF_INT_VEC_VFFLR0);
|
||||
if (rc)
|
||||
plt_err("Failed to init RVU_PF_INT_VEC_VFFLR0 rc=%d", rc);
|
||||
|
||||
rc = dev_irq_register(handle, roc_pf_vf_flr_irq, dev,
|
||||
RVU_PF_INT_VEC_VFFLR1);
|
||||
if (rc)
|
||||
plt_err("Failed to init RVU_PF_INT_VEC_VFFLR1 rc=%d", rc);
|
||||
|
||||
/* Enable HW interrupt */
|
||||
for (i = 0; i < MAX_VFPF_DWORD_BITS; ++i) {
|
||||
plt_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INTX(i));
|
||||
plt_write64(~0ull, dev->bar2 + RVU_PF_VFTRPENDX(i));
|
||||
plt_write64(~0ull, dev->bar2 + RVU_PF_VFFLR_INT_ENA_W1SX(i));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
dev_active_vfs(struct dev *dev)
|
||||
{
|
||||
int i, count = 0;
|
||||
|
||||
for (i = 0; i < MAX_VFPF_DWORD_BITS; i++)
|
||||
count += __builtin_popcount(dev->active_vfs[i]);
|
||||
|
||||
return count;
|
||||
}
|
||||
|
||||
static void
|
||||
dev_vf_hwcap_update(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
switch (pci_dev->id.device_id) {
|
||||
case PCI_DEVID_CNXK_RVU_PF:
|
||||
break;
|
||||
case PCI_DEVID_CNXK_RVU_SSO_TIM_VF:
|
||||
case PCI_DEVID_CNXK_RVU_NPA_VF:
|
||||
case PCI_DEVID_CNXK_RVU_AF_VF:
|
||||
case PCI_DEVID_CNXK_RVU_VF:
|
||||
case PCI_DEVID_CNXK_RVU_SDP_VF:
|
||||
dev->hwcap |= DEV_HWCAP_F_VF;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static uintptr_t
|
||||
dev_vf_mbase_get(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
void *vf_mbase = NULL;
|
||||
uintptr_t pa;
|
||||
|
||||
if (dev_is_vf(dev))
|
||||
return 0;
|
||||
|
||||
/* For CN10K onwards, it is just after PF MBOX */
|
||||
if (!roc_model_is_cn9k())
|
||||
return dev->bar4 + MBOX_SIZE;
|
||||
|
||||
pa = plt_read64(dev->bar2 + RVU_PF_VF_BAR4_ADDR);
|
||||
if (!pa) {
|
||||
plt_err("Invalid VF mbox base pa");
|
||||
return pa;
|
||||
}
|
||||
|
||||
vf_mbase = mbox_mem_map(pa, MBOX_SIZE * pci_dev->max_vfs);
|
||||
if (vf_mbase == MAP_FAILED) {
|
||||
plt_err("Failed to mmap vf mbase at pa 0x%lx, rc=%d", pa,
|
||||
errno);
|
||||
return 0;
|
||||
}
|
||||
return (uintptr_t)vf_mbase;
|
||||
}
|
||||
|
||||
static void
|
||||
dev_vf_mbase_put(struct plt_pci_device *pci_dev, uintptr_t vf_mbase)
|
||||
{
|
||||
if (!vf_mbase || !pci_dev->max_vfs || !roc_model_is_cn9k())
|
||||
return;
|
||||
|
||||
mbox_mem_unmap((void *)vf_mbase, MBOX_SIZE * pci_dev->max_vfs);
|
||||
}
|
||||
|
||||
static uint16_t
|
||||
dev_pf_total_vfs(struct plt_pci_device *pci_dev)
|
||||
{
|
||||
@ -213,7 +952,6 @@ dev_setup_shared_lmt_region(struct mbox *mbox)
|
||||
static int
|
||||
dev_lmt_setup(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
{
|
||||
uint64_t bar4_mbox_sz = MBOX_SIZE;
|
||||
struct idev_cfg *idev;
|
||||
int rc;
|
||||
|
||||
@ -237,6 +975,20 @@ dev_lmt_setup(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
dev->pf_func, rc);
|
||||
}
|
||||
|
||||
if (dev_is_vf(dev)) {
|
||||
/* VF BAR4 should always be sufficient enough to
|
||||
* hold LMT lines.
|
||||
*/
|
||||
if (pci_dev->mem_resource[4].len <
|
||||
(RVU_LMT_LINE_MAX * RVU_LMT_SZ)) {
|
||||
plt_err("Not enough bar4 space for lmt lines");
|
||||
return -EFAULT;
|
||||
}
|
||||
|
||||
dev->lmt_base = dev->bar4;
|
||||
} else {
|
||||
uint64_t bar4_mbox_sz = MBOX_SIZE;
|
||||
|
||||
/* PF BAR4 should always be sufficient enough to
|
||||
* hold PF-AF MBOX + PF-VF MBOX + LMT lines.
|
||||
*/
|
||||
@ -249,6 +1001,7 @@ dev_lmt_setup(struct plt_pci_device *pci_dev, struct dev *dev)
|
||||
/* LMT base is just after total VF MBOX area */
|
||||
bar4_mbox_sz += (MBOX_SIZE * dev_pf_total_vfs(pci_dev));
|
||||
dev->lmt_base = dev->bar4 + bar4_mbox_sz;
|
||||
}
|
||||
|
||||
/* Base LMT address should be chosen from only those pci funcs which
|
||||
* participate in LMT shared mode.
|
||||
@ -270,6 +1023,7 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
|
||||
{
|
||||
int direction, up_direction, rc;
|
||||
uintptr_t bar2, bar4, mbox;
|
||||
uintptr_t vf_mbase = 0;
|
||||
uint64_t intr_offset;
|
||||
|
||||
bar2 = (uintptr_t)pci_dev->mem_resource[2].addr;
|
||||
@ -293,13 +1047,23 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
|
||||
goto error;
|
||||
}
|
||||
|
||||
dev->maxvf = pci_dev->max_vfs;
|
||||
dev->bar2 = bar2;
|
||||
dev->bar4 = bar4;
|
||||
dev_vf_hwcap_update(pci_dev, dev);
|
||||
|
||||
if (dev_is_vf(dev)) {
|
||||
mbox = (roc_model_is_cn9k() ?
|
||||
bar4 : (bar2 + RVU_VF_MBOX_REGION));
|
||||
direction = MBOX_DIR_VFPF;
|
||||
up_direction = MBOX_DIR_VFPF_UP;
|
||||
intr_offset = RVU_VF_INT;
|
||||
} else {
|
||||
mbox = bar4;
|
||||
direction = MBOX_DIR_PFAF;
|
||||
up_direction = MBOX_DIR_PFAF_UP;
|
||||
intr_offset = RVU_PF_INT;
|
||||
}
|
||||
|
||||
/* Initialize the local mbox */
|
||||
rc = mbox_init(&dev->mbox_local, mbox, bar2, direction, 1, intr_offset);
|
||||
@ -322,7 +1086,43 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
|
||||
goto mbox_unregister;
|
||||
|
||||
dev->pf = dev_get_pf(dev->pf_func);
|
||||
dev->vf = dev_get_vf(dev->pf_func);
|
||||
memset(&dev->active_vfs, 0, sizeof(dev->active_vfs));
|
||||
|
||||
/* Allocate memory for device ops */
|
||||
dev->ops = plt_zmalloc(sizeof(struct dev_ops), 0);
|
||||
if (dev->ops == NULL) {
|
||||
rc = -ENOMEM;
|
||||
goto mbox_unregister;
|
||||
}
|
||||
|
||||
/* Found VF devices in a PF device */
|
||||
if (pci_dev->max_vfs > 0) {
|
||||
/* Remap mbox area for all vf's */
|
||||
vf_mbase = dev_vf_mbase_get(pci_dev, dev);
|
||||
if (!vf_mbase) {
|
||||
rc = -ENODEV;
|
||||
goto mbox_unregister;
|
||||
}
|
||||
/* Init mbox object */
|
||||
rc = mbox_init(&dev->mbox_vfpf, vf_mbase, bar2, MBOX_DIR_PFVF,
|
||||
pci_dev->max_vfs, intr_offset);
|
||||
if (rc)
|
||||
goto iounmap;
|
||||
|
||||
/* PF -> VF UP messages */
|
||||
rc = mbox_init(&dev->mbox_vfpf_up, vf_mbase, bar2,
|
||||
MBOX_DIR_PFVF_UP, pci_dev->max_vfs, intr_offset);
|
||||
if (rc)
|
||||
goto iounmap;
|
||||
}
|
||||
|
||||
/* Register VF-FLR irq handlers */
|
||||
if (!dev_is_vf(dev)) {
|
||||
rc = vf_flr_register_irqs(pci_dev, dev);
|
||||
if (rc)
|
||||
goto iounmap;
|
||||
}
|
||||
dev->mbox_active = 1;
|
||||
|
||||
/* Setup LMT line base */
|
||||
@ -332,8 +1132,11 @@ dev_init(struct dev *dev, struct plt_pci_device *pci_dev)
|
||||
|
||||
return rc;
|
||||
iounmap:
|
||||
dev_vf_mbase_put(pci_dev, vf_mbase);
|
||||
mbox_unregister:
|
||||
mbox_unregister_irq(pci_dev, dev);
|
||||
if (dev->ops)
|
||||
plt_free(dev->ops);
|
||||
mbox_fini:
|
||||
mbox_fini(dev->mbox);
|
||||
mbox_fini(&dev->mbox_up);
|
||||
@ -349,6 +1152,20 @@ dev_fini(struct dev *dev, struct plt_pci_device *pci_dev)
|
||||
|
||||
mbox_unregister_irq(pci_dev, dev);
|
||||
|
||||
if (!dev_is_vf(dev))
|
||||
vf_flr_unregister_irqs(pci_dev, dev);
|
||||
/* Release PF - VF */
|
||||
mbox = &dev->mbox_vfpf;
|
||||
if (mbox->hwbase && mbox->dev)
|
||||
dev_vf_mbase_put(pci_dev, mbox->hwbase);
|
||||
|
||||
if (dev->ops)
|
||||
plt_free(dev->ops);
|
||||
|
||||
mbox_fini(mbox);
|
||||
mbox = &dev->mbox_vfpf_up;
|
||||
mbox_fini(mbox);
|
||||
|
||||
/* Release PF - AF */
|
||||
mbox = dev->mbox;
|
||||
mbox_fini(mbox);
|
||||
|
||||
@ -5,12 +5,38 @@
|
||||
#ifndef _ROC_DEV_PRIV_H
|
||||
#define _ROC_DEV_PRIV_H
|
||||
|
||||
#define DEV_HWCAP_F_VF BIT_ULL(0) /* VF device */
|
||||
|
||||
#define RVU_PFVF_PF_SHIFT 10
|
||||
#define RVU_PFVF_PF_MASK 0x3F
|
||||
#define RVU_PFVF_FUNC_SHIFT 0
|
||||
#define RVU_PFVF_FUNC_MASK 0x3FF
|
||||
#define RVU_MAX_VF 64 /* RVU_PF_VFPF_MBOX_INT(0..1) */
|
||||
#define RVU_MAX_INT_RETRY 3
|
||||
|
||||
/* PF/VF message handling timer */
|
||||
#define VF_PF_MBOX_TIMER_MS (20 * 1000)
|
||||
|
||||
typedef struct {
|
||||
/* 128 devices translate to two 64 bits dwords */
|
||||
#define MAX_VFPF_DWORD_BITS 2
|
||||
uint64_t bits[MAX_VFPF_DWORD_BITS];
|
||||
} dev_intr_t;
|
||||
|
||||
/* Link status update callback */
|
||||
typedef void (*link_info_t)(void *roc_nix,
|
||||
struct cgx_link_user_info *link);
|
||||
|
||||
/* PTP info callback */
|
||||
typedef int (*ptp_info_t)(void *roc_nix, bool enable);
|
||||
|
||||
struct dev_ops {
|
||||
link_info_t link_status_update;
|
||||
ptp_info_t ptp_info_update;
|
||||
};
|
||||
|
||||
#define dev_is_vf(dev) ((dev)->hwcap & DEV_HWCAP_F_VF)
|
||||
|
||||
static inline int
|
||||
dev_get_vf(uint16_t pf_func)
|
||||
{
|
||||
@ -29,18 +55,33 @@ dev_pf_func(int pf, int vf)
|
||||
return (pf << RVU_PFVF_PF_SHIFT) | ((vf << RVU_PFVF_FUNC_SHIFT) + 1);
|
||||
}
|
||||
|
||||
static inline int
|
||||
dev_is_afvf(uint16_t pf_func)
|
||||
{
|
||||
return !(pf_func & ~RVU_PFVF_FUNC_MASK);
|
||||
}
|
||||
|
||||
struct dev {
|
||||
uint16_t pf;
|
||||
int16_t vf;
|
||||
uint16_t pf_func;
|
||||
uint8_t mbox_active;
|
||||
bool drv_inited;
|
||||
uint64_t active_vfs[MAX_VFPF_DWORD_BITS];
|
||||
uintptr_t bar2;
|
||||
uintptr_t bar4;
|
||||
uintptr_t lmt_base;
|
||||
struct mbox mbox_local;
|
||||
struct mbox mbox_up;
|
||||
struct mbox mbox_vfpf;
|
||||
struct mbox mbox_vfpf_up;
|
||||
dev_intr_t intr;
|
||||
int timer_set; /* ~0 : no alarm handling */
|
||||
uint64_t hwcap;
|
||||
struct mbox *mbox;
|
||||
uint16_t maxvf;
|
||||
struct dev_ops *ops;
|
||||
void *roc_nix;
|
||||
bool disable_shared_lmt; /* false(default): shared lmt mode enabled */
|
||||
} __plt_cache_aligned;
|
||||
|
||||
@ -49,6 +90,7 @@ extern uint16_t dev_sclk_freq;
|
||||
|
||||
int dev_init(struct dev *dev, struct plt_pci_device *pci_dev);
|
||||
int dev_fini(struct dev *dev, struct plt_pci_device *pci_dev);
|
||||
int dev_active_vfs(struct dev *dev);
|
||||
|
||||
int dev_irq_register(struct plt_intr_handle *intr_handle,
|
||||
plt_intr_callback_fn cb, void *data, unsigned int vec);
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user