net/virtio: add vectorized packed ring NEON Rx
Optimize packed ring Rx batch path with NEON instructions. Signed-off-by: Joyce Kong <joyce.kong@arm.com> Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>
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@ -19,9 +19,16 @@
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#include "virtqueue.h"
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#define BYTE_SIZE 8
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#ifdef CC_AVX512_SUPPORT
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/* flag bits offset in packed ring desc higher 64bits */
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#define FLAGS_BITS_OFFSET ((offsetof(struct vring_packed_desc, flags) - \
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offsetof(struct vring_packed_desc, len)) * BYTE_SIZE)
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#elif defined(RTE_ARCH_ARM)
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/* flag bits offset in packed ring desc from ID */
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#define FLAGS_BITS_OFFSET ((offsetof(struct vring_packed_desc, flags) - \
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offsetof(struct vring_packed_desc, id)) * BYTE_SIZE)
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#endif
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#define PACKED_FLAGS_MASK ((0ULL | VRING_PACKED_DESC_F_AVAIL_USED) << \
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FLAGS_BITS_OFFSET)
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@ -44,8 +51,16 @@
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/* net hdr short size mask */
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#define NET_HDR_MASK 0x3F
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#ifdef RTE_ARCH_ARM
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/* The cache line size on different Arm platforms are different, so
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* put a four batch size here to match with the minimum cache line
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* size and accommodate NEON register size.
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*/
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#define PACKED_BATCH_SIZE 4
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#else
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#define PACKED_BATCH_SIZE (RTE_CACHE_LINE_SIZE / \
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sizeof(struct vring_packed_desc))
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#endif
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#define PACKED_BATCH_MASK (PACKED_BATCH_SIZE - 1)
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#ifdef VIRTIO_GCC_UNROLL_PRAGMA
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150
drivers/net/virtio/virtio_rxtx_packed_neon.h
Normal file
150
drivers/net/virtio/virtio_rxtx_packed_neon.h
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@ -0,0 +1,150 @@
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2020 Arm Corporation
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*/
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <errno.h>
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#include <rte_net.h>
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#include <rte_vect.h>
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#include "virtio_ethdev.h"
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#include "virtio_pci.h"
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#include "virtio_rxtx_packed.h"
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#include "virtqueue.h"
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static inline int
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virtqueue_dequeue_batch_packed_vec(struct virtnet_rx *rxvq,
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struct rte_mbuf **rx_pkts)
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{
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struct virtqueue *vq = rxvq->vq;
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struct virtio_hw *hw = vq->hw;
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uint16_t head_size = hw->vtnet_hdr_size;
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uint16_t id = vq->vq_used_cons_idx;
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struct vring_packed_desc *p_desc;
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uint16_t i;
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if (id & PACKED_BATCH_MASK)
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return -1;
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if (unlikely((id + PACKED_BATCH_SIZE) > vq->vq_nentries))
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return -1;
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/* Map packed descriptor to mbuf fields. */
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uint8x16_t shuf_msk1 = {
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0xFF, 0xFF, 0xFF, 0xFF, /* pkt_type set as unknown */
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0, 1, /* octet 1~0, low 16 bits pkt_len */
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0xFF, 0xFF, /* skip high 16 bits of pkt_len, zero out */
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0, 1, /* octet 1~0, 16 bits data_len */
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0xFF, 0xFF, /* vlan tci set as unknown */
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0xFF, 0xFF, 0xFF, 0xFF
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};
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uint8x16_t shuf_msk2 = {
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0xFF, 0xFF, 0xFF, 0xFF, /* pkt_type set as unknown */
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8, 9, /* octet 9~8, low 16 bits pkt_len */
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0xFF, 0xFF, /* skip high 16 bits of pkt_len, zero out */
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8, 9, /* octet 9~8, 16 bits data_len */
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0xFF, 0xFF, /* vlan tci set as unknown */
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0xFF, 0xFF, 0xFF, 0xFF
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};
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/* Subtract the header length. */
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uint16x8_t len_adjust = {
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0, 0, /* ignore pkt_type field */
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head_size, /* sub head_size on pkt_len */
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0, /* ignore high 16 bits of pkt_len */
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head_size, /* sub head_size on data_len */
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0, 0, 0 /* ignore non-length fields */
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};
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uint64x2_t desc[PACKED_BATCH_SIZE / 2];
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uint64x2x2_t mbp[PACKED_BATCH_SIZE / 2];
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uint64x2_t pkt_mb[PACKED_BATCH_SIZE];
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p_desc = &vq->vq_packed.ring.desc[id];
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/* Load high 64 bits of packed descriptor 0,1. */
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desc[0] = vld2q_u64((uint64_t *)(p_desc)).val[1];
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/* Load high 64 bits of packed descriptor 2,3. */
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desc[1] = vld2q_u64((uint64_t *)(p_desc + 2)).val[1];
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/* Only care avail/used bits. */
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uint32x4_t v_mask = vdupq_n_u32(PACKED_FLAGS_MASK);
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/* Extract high 32 bits of packed descriptor (id, flags). */
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uint32x4_t v_desc = vuzp2q_u32(vreinterpretq_u32_u64(desc[0]),
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vreinterpretq_u32_u64(desc[1]));
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uint32x4_t v_flag = vandq_u32(v_desc, v_mask);
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uint32x4_t v_used_flag = vdupq_n_u32(0);
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if (vq->vq_packed.used_wrap_counter)
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v_used_flag = vdupq_n_u32(PACKED_FLAGS_MASK);
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poly128_t desc_stats = vreinterpretq_p128_u32(~vceqq_u32(v_flag, v_used_flag));
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/* Check all descs are used. */
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if (desc_stats)
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return -1;
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/* Load 2 mbuf pointers per time. */
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mbp[0] = vld2q_u64((uint64_t *)&vq->vq_descx[id]);
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vst1q_u64((uint64_t *)&rx_pkts[0], mbp[0].val[0]);
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mbp[1] = vld2q_u64((uint64_t *)&vq->vq_descx[id + 2]);
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vst1q_u64((uint64_t *)&rx_pkts[2], mbp[1].val[0]);
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/**
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* Update data length and packet length for descriptor.
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* structure of pkt_mb:
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* --------------------------------------------------------------------
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* |32 bits pkt_type|32 bits pkt_len|16 bits data_len|16 bits vlan_tci|
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* --------------------------------------------------------------------
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*/
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pkt_mb[0] = vreinterpretq_u64_u8(vqtbl1q_u8(
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vreinterpretq_u8_u64(desc[0]), shuf_msk1));
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pkt_mb[1] = vreinterpretq_u64_u8(vqtbl1q_u8(
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vreinterpretq_u8_u64(desc[0]), shuf_msk2));
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pkt_mb[2] = vreinterpretq_u64_u8(vqtbl1q_u8(
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vreinterpretq_u8_u64(desc[1]), shuf_msk1));
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pkt_mb[3] = vreinterpretq_u64_u8(vqtbl1q_u8(
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vreinterpretq_u8_u64(desc[1]), shuf_msk2));
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pkt_mb[0] = vreinterpretq_u64_u16(vsubq_u16(
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vreinterpretq_u16_u64(pkt_mb[0]), len_adjust));
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pkt_mb[1] = vreinterpretq_u64_u16(vsubq_u16(
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vreinterpretq_u16_u64(pkt_mb[1]), len_adjust));
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pkt_mb[2] = vreinterpretq_u64_u16(vsubq_u16(
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vreinterpretq_u16_u64(pkt_mb[2]), len_adjust));
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pkt_mb[3] = vreinterpretq_u64_u16(vsubq_u16(
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vreinterpretq_u16_u64(pkt_mb[3]), len_adjust));
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vst1q_u64((void *)&rx_pkts[0]->rx_descriptor_fields1, pkt_mb[0]);
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vst1q_u64((void *)&rx_pkts[1]->rx_descriptor_fields1, pkt_mb[1]);
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vst1q_u64((void *)&rx_pkts[2]->rx_descriptor_fields1, pkt_mb[2]);
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vst1q_u64((void *)&rx_pkts[3]->rx_descriptor_fields1, pkt_mb[3]);
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if (hw->has_rx_offload) {
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virtio_for_each_try_unroll(i, 0, PACKED_BATCH_SIZE) {
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char *addr = (char *)rx_pkts[i]->buf_addr +
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RTE_PKTMBUF_HEADROOM - head_size;
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virtio_vec_rx_offload(rx_pkts[i],
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(struct virtio_net_hdr *)addr);
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}
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}
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virtio_update_batch_stats(&rxvq->stats, rx_pkts[0]->pkt_len,
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rx_pkts[1]->pkt_len, rx_pkts[2]->pkt_len,
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rx_pkts[3]->pkt_len);
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vq->vq_free_cnt += PACKED_BATCH_SIZE;
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vq->vq_used_cons_idx += PACKED_BATCH_SIZE;
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if (vq->vq_used_cons_idx >= vq->vq_nentries) {
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vq->vq_used_cons_idx -= vq->vq_nentries;
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vq->vq_packed.used_wrap_counter ^= 1;
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}
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return 0;
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}
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