net/ice/base: update macros
Update macros for metadata and package flags. Signed-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com> Signed-off-by: Qi Zhang <qi.z.zhang@intel.com> Reviewed-by: Qiming Yang <qiming.yang@intel.com> Reviewed-by: Wenzhuo Lu <wenzhuo.lu@intel.com>
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@ -365,22 +365,22 @@ static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
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*/
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case ICE_RXDID_FLEX_NIC:
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case ICE_RXDID_FLEX_NIC_2:
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_FRG,
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ICE_RXFLG_UDP_GRE, ICE_RXFLG_PKT_DSI,
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ICE_RXFLG_FIN, idx++);
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_FRG,
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ICE_FLG_UDP_GRE, ICE_FLG_PKT_DSI,
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ICE_FLG_FIN, idx++);
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/* flex flag 1 is not used for flexi-flag programming, skipping
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* these four FLG64 bits.
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*/
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_SYN, ICE_RXFLG_RST,
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ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx++);
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_PKT_DSI,
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ICE_RXFLG_PKT_DSI, ICE_RXFLG_EVLAN_x8100,
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ICE_RXFLG_EVLAN_x9100, idx++);
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_VLAN_x8100,
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ICE_RXFLG_TNL_VLAN, ICE_RXFLG_TNL_MAC,
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ICE_RXFLG_TNL0, idx++);
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_RXFLG_TNL1, ICE_RXFLG_TNL2,
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ICE_RXFLG_PKT_DSI, ICE_RXFLG_PKT_DSI, idx);
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_SYN, ICE_FLG_RST,
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ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx++);
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_PKT_DSI,
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ICE_FLG_PKT_DSI, ICE_FLG_EVLAN_x8100,
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ICE_FLG_EVLAN_x9100, idx++);
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_VLAN_x8100,
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ICE_FLG_TNL_VLAN, ICE_FLG_TNL_MAC,
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ICE_FLG_TNL0, idx++);
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ICE_PROG_FLG_ENTRY(hw, prof_id, ICE_FLG_TNL1, ICE_FLG_TNL2,
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ICE_FLG_PKT_DSI, ICE_FLG_PKT_DSI, idx);
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break;
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default:
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@ -399,17 +399,17 @@ static void ice_init_flex_flags(struct ice_hw *hw, enum ice_rxdid prof_id)
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*/
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static void ice_init_flex_flds(struct ice_hw *hw, enum ice_rxdid prof_id)
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{
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enum ice_flex_rx_mdid mdid;
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enum ice_flex_mdid mdid;
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switch (prof_id) {
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case ICE_RXDID_FLEX_NIC:
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case ICE_RXDID_FLEX_NIC_2:
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ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_LOW, 0);
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ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_HASH_HIGH, 1);
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ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_RX_MDID_FLOW_ID_LOWER, 2);
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ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_LOW, 0);
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ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_RX_HASH_HIGH, 1);
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ICE_PROG_FLEX_ENTRY(hw, prof_id, ICE_MDID_FLOW_ID_LOWER, 2);
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mdid = (prof_id == ICE_RXDID_FLEX_NIC_2) ?
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ICE_RX_MDID_SRC_VSI : ICE_RX_MDID_FLOW_ID_HIGH;
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ICE_MDID_SRC_VSI : ICE_MDID_FLOW_ID_HIGH;
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ICE_PROG_FLEX_ENTRY(hw, prof_id, mdid, 3);
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@ -278,14 +278,23 @@ enum ice_flow_action_type {
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ICE_FLOW_ACT_NOP,
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ICE_FLOW_ACT_ALLOW,
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ICE_FLOW_ACT_DROP,
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ICE_FLOW_ACT_COUNT,
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ICE_FLOW_ACT_CNTR_PKT,
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ICE_FLOW_ACT_FWD_VSI,
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ICE_FLOW_ACT_FWD_VSI_LIST, /* Should be abstracted away */
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ICE_FLOW_ACT_FWD_QUEUE, /* Can Queues be abstracted away? */
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ICE_FLOW_ACT_FWD_QUEUE_GROUP, /* Can Queues be abstracted away? */
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ICE_FLOW_ACTION_PUSH,
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ICE_FLOW_ACTION_POP,
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ICE_FLOW_ACTION_MODIFY,
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ICE_FLOW_ACT_PUSH,
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ICE_FLOW_ACT_POP,
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ICE_FLOW_ACT_MODIFY,
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ICE_FLOW_ACT_CNTR_BYTES,
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ICE_FLOW_ACT_CNTR_PKT_BYTES,
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ICE_FLOW_ACT_GENERIC_0,
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ICE_FLOW_ACT_GENERIC_1,
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ICE_FLOW_ACT_GENERIC_2,
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ICE_FLOW_ACT_GENERIC_3,
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ICE_FLOW_ACT_GENERIC_4,
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ICE_FLOW_ACT_RPT_FLOW_ID,
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ICE_FLOW_ACT_BUILD_PROF_IDX,
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};
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struct ice_flow_action {
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@ -627,39 +627,60 @@ enum ice_flex_opcode {
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ICE_RX_OPC_PROTID
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};
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/* Receive Descriptor MDID values */
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enum ice_flex_rx_mdid {
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ICE_RX_MDID_FLOW_ID_LOWER = 5,
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ICE_RX_MDID_FLOW_ID_HIGH,
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ICE_RX_MDID_DST_VSI = 13,
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ICE_RX_MDID_SRC_VSI = 19,
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ICE_RX_MDID_HASH_LOW = 56,
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ICE_RX_MDID_HASH_HIGH,
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ICE_RX_MDID_ACL_CTR0 = ICE_RX_MDID_HASH_LOW,
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ICE_RX_MDID_ACL_CTR1 = ICE_RX_MDID_HASH_HIGH,
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ICE_RX_MDID_ACL_CTR2 = 59
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/* Receive Descriptor MDID values that access packet flags */
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enum ice_flex_mdid_pkt_flags {
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ICE_RX_MDID_PKT_FLAGS_15_0 = 20,
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ICE_RX_MDID_PKT_FLAGS_31_16,
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ICE_RX_MDID_PKT_FLAGS_47_32,
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ICE_RX_MDID_PKT_FLAGS_63_48,
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};
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/* Generic descriptor MDID values */
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enum ice_flex_mdid {
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ICE_MDID_GENERIC_WORD_0,
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ICE_MDID_GENERIC_WORD_1,
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ICE_MDID_GENERIC_WORD_2,
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ICE_MDID_GENERIC_WORD_3,
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ICE_MDID_GENERIC_WORD_4,
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ICE_MDID_FLOW_ID_LOWER,
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ICE_MDID_FLOW_ID_HIGH,
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ICE_MDID_RX_DESCR_PROF_IDX,
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ICE_MDID_RX_PKT_DROP,
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ICE_MDID_RX_DST_Q = 12,
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ICE_MDID_RX_DST_VSI,
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ICE_MDID_SRC_VSI = 19,
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ICE_MDID_ACL_NOP = 55,
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/* Entry 56 */
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ICE_MDID_RX_HASH_LOW,
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ICE_MDID_ACL_CNTR_PKT = ICE_MDID_RX_HASH_LOW,
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/* Entry 57 */
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ICE_MDID_RX_HASH_HIGH,
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ICE_MDID_ACL_CNTR_BYTES = ICE_MDID_RX_HASH_HIGH,
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ICE_MDID_ACL_CNTR_PKT_BYTES
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};
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/* for ice_32byte_rx_flex_desc.mir_id_umb_cast member */
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#define ICE_RX_FLEX_DESC_MIRROR_M (0x3F) /* 6-bits */
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/* Rx Flag64 packet flag bits */
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enum ice_rx_flg64_bits {
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ICE_RXFLG_PKT_DSI = 0,
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ICE_RXFLG_EVLAN_x8100 = 15,
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ICE_RXFLG_EVLAN_x9100,
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ICE_RXFLG_VLAN_x8100,
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ICE_RXFLG_TNL_MAC = 22,
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ICE_RXFLG_TNL_VLAN,
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ICE_RXFLG_PKT_FRG,
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ICE_RXFLG_FIN = 32,
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ICE_RXFLG_SYN,
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ICE_RXFLG_RST,
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ICE_RXFLG_TNL0 = 38,
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ICE_RXFLG_TNL1,
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ICE_RXFLG_TNL2,
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ICE_RXFLG_UDP_GRE,
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ICE_RXFLG_RSVD = 63
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/* Rx/Tx Flag64 packet flag bits */
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enum ice_flg64_bits {
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ICE_FLG_PKT_DSI = 0,
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/* If there is a 1 in this bit position then that means Rx packet */
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ICE_FLG_PKT_DIR = 4,
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ICE_FLG_EVLAN_x8100 = 15,
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ICE_FLG_EVLAN_x9100,
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ICE_FLG_VLAN_x8100,
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ICE_FLG_TNL_MAC = 22,
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ICE_FLG_TNL_VLAN,
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ICE_FLG_PKT_FRG,
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ICE_FLG_FIN = 32,
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ICE_FLG_SYN,
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ICE_FLG_RST,
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ICE_FLG_TNL0 = 38,
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ICE_FLG_TNL1,
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ICE_FLG_TNL2,
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ICE_FLG_UDP_GRE,
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ICE_FLG_RSVD = 63
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};
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enum ice_rx_flex_desc_umb_cast_bits { /* field is 2 bits long */
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