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baseband/acc100: add LDPC processing functions

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Adding LDPC decode and encode processing operations

Signed-off-by: Nicolas Chautru <nicolas.chautru@intel.com>
Acked-by: Liu Tianjiao <tianjiao.liu@intel.com>
Acked-by: Dave Burley <dave.burley@accelercomm.com>
Acked-by: Maxime Coquelin <maxime.coquelin@redhat.com>
This commit is contained in:
Nicolas Chautru 2020-10-05 15:12:44 -07:00 committed by Akhil Goyal
parent 060e767293
commit 5ad5060f8f
3 changed files with 1629 additions and 5 deletions
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8
doc/guides/bbdevs/features/acc100.ini
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@ -6,9 +6,9 @@
[Features]
Turbo Decoder (4G) = N
Turbo Encoder (4G) = N
LDPC Decoder (5G) = N
LDPC Encoder (5G) = N
LLR/HARQ Compression = N
External DDR Access = N
LDPC Decoder (5G) = Y
LDPC Encoder (5G) = Y
LLR/HARQ Compression = Y
External DDR Access = Y
HW Accelerated = Y
BBDEV API = Y

1620
drivers/baseband/acc100/rte_acc100_pmd.c
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File diff suppressed because it is too large Load Diff

6
drivers/baseband/acc100/rte_acc100_pmd.h
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@ -88,6 +88,8 @@
#define ACC100_TMPL_PRI_3 0x0f0e0d0c
#define ACC100_QUEUE_ENABLE 0x80000000 /* Bit to mark Queue as Enabled */
#define ACC100_WORDS_IN_ARAM_SIZE (128 * 1024 / 4)
#define ACC100_FDONE 0x80000000
#define ACC100_SDONE 0x40000000
#define ACC100_NUM_TMPL 32
/* Mapping of signals for the available engines */
@ -120,6 +122,9 @@
#define ACC100_FCW_TD_BLEN 24
#define ACC100_FCW_LE_BLEN 32
#define ACC100_FCW_LD_BLEN 36
#define ACC100_5GUL_SIZE_0 16
#define ACC100_5GUL_SIZE_1 40
#define ACC100_5GUL_OFFSET_0 36
#define ACC100_FCW_VER 2
#define ACC100_MUX_5GDL_DESC 6
@ -402,6 +407,7 @@ struct __rte_packed acc100_dma_req_desc {
union acc100_dma_desc {
struct acc100_dma_req_desc req;
union acc100_dma_rsp_desc rsp;
uint64_t atom_hdr;
};