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net/mlx5: modify advanced RxQ object via DevX

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Implement function mlx5_devx_cmd_modify_rq() to modify RQ.
Add related structs in mlx5.h and mlx5_prm.h.

Signed-off-by: Dekel Peled <dekelp@mellanox.com>
Acked-by: Matan Azrad <matan@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
This commit is contained in:
Dekel Peled 2019-07-22 14:52:07 +00:00 committed by Ferruh Yigit
parent 86fc67fc93
commit 5bf204fef1
3 changed files with 95 additions and 0 deletions
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16
drivers/net/mlx5/mlx5.h
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@ -306,6 +306,20 @@ struct mlx5_devx_create_rq_attr {
struct mlx5_devx_wq_attr wq_attr;
};
/* Modify RQ attributes structure, used by modify RQ operation. */
struct mlx5_devx_modify_rq_attr {
uint32_t rqn:24;
uint32_t rq_state:4; /* Current RQ state. */
uint32_t state:4; /* Required RQ state. */
uint32_t scatter_fcs:1;
uint32_t vsd:1;
uint32_t counter_set_id:8;
uint32_t hairpin_peer_sq:24;
uint32_t hairpin_peer_vhca:16;
uint64_t modify_bitmask;
uint32_t lwm:16; /* Contained WQ lwm. */
};
/**
* Type of object being allocated.
*/
@ -789,5 +803,7 @@ int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,
struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
struct mlx5_devx_create_rq_attr *rq_attr,
int socket);
int mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
struct mlx5_devx_modify_rq_attr *rq_attr);
#endif /* RTE_PMD_MLX5_H_ */

50
drivers/net/mlx5/mlx5_devx_cmds.c
View File

@ -526,3 +526,53 @@ mlx5_devx_cmd_create_rq(struct ibv_context *ctx,
rq->id = MLX5_GET(create_rq_out, out, rqn);
return rq;
}
/**
* Modify RQ using DevX API.
*
* @param[in] rq
* Pointer to RQ object structure.
* @param [in] rq_attr
* Pointer to modify RQ attributes structure.
*
* @return
* 0 on success, a negative errno value otherwise and rte_errno is set.
*/
int
mlx5_devx_cmd_modify_rq(struct mlx5_devx_obj *rq,
struct mlx5_devx_modify_rq_attr *rq_attr)
{
uint32_t in[MLX5_ST_SZ_DW(modify_rq_in)] = {0};
uint32_t out[MLX5_ST_SZ_DW(modify_rq_out)] = {0};
void *rq_ctx, *wq_ctx;
int ret;
MLX5_SET(modify_rq_in, in, opcode, MLX5_CMD_OP_MODIFY_RQ);
MLX5_SET(modify_rq_in, in, rq_state, rq_attr->rq_state);
MLX5_SET(modify_rq_in, in, rqn, rq->id);
MLX5_SET64(modify_rq_in, in, modify_bitmask, rq_attr->modify_bitmask);
rq_ctx = MLX5_ADDR_OF(modify_rq_in, in, ctx);
MLX5_SET(rqc, rq_ctx, state, rq_attr->state);
if (rq_attr->modify_bitmask &
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS)
MLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);
if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD)
MLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);
if (rq_attr->modify_bitmask &
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID)
MLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);
MLX5_SET(rqc, rq_ctx, hairpin_peer_sq, rq_attr->hairpin_peer_sq);
MLX5_SET(rqc, rq_ctx, hairpin_peer_vhca, rq_attr->hairpin_peer_vhca);
if (rq_attr->modify_bitmask & MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM) {
wq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);
MLX5_SET(wq, wq_ctx, lwm, rq_attr->lwm);
}
ret = mlx5_glue->devx_obj_modify(rq->obj, in, sizeof(in),
out, sizeof(out));
if (ret) {
DRV_LOG(ERR, "Failed to modify RQ using DevX");
rte_errno = errno;
return -errno;
}
return ret;
}

29
drivers/net/mlx5/mlx5_prm.h
View File

@ -628,6 +628,7 @@ enum {
MLX5_CMD_OP_CREATE_MKEY = 0x200,
MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
MLX5_CMD_OP_CREATE_RQ = 0x908,
MLX5_CMD_OP_MODIFY_RQ = 0x909,
MLX5_CMD_OP_QUERY_TIS = 0x915,
MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
@ -1378,6 +1379,34 @@ struct mlx5_ifc_create_rq_in_bits {
struct mlx5_ifc_rqc_bits ctx;
};
struct mlx5_ifc_modify_rq_out_bits {
u8 status[0x8];
u8 reserved_at_8[0x18];
u8 syndrome[0x20];
u8 reserved_at_40[0x40];
};
enum {
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_WQ_LWM = 1ULL << 0,
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
};
struct mlx5_ifc_modify_rq_in_bits {
u8 opcode[0x10];
u8 uid[0x10];
u8 reserved_at_20[0x10];
u8 op_mod[0x10];
u8 rq_state[0x4];
u8 reserved_at_44[0x4];
u8 rqn[0x18];
u8 reserved_at_60[0x20];
u8 modify_bitmask[0x40];
u8 reserved_at_c0[0x40];
struct mlx5_ifc_rqc_bits ctx;
};
/* CQE format mask. */
#define MLX5E_CQE_FORMAT_MASK 0xc