common/qat: add gen-specific queue pair function
This patch adds the queue pair data structure and function prototypes for different QAT generations. Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com> Acked-by: Ciara Power <ciara.power@intel.com>
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@ -34,6 +34,9 @@
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ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
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(ADF_ARB_REG_SLOT * index), value)
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struct qat_qp_hw_spec_funcs*
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qat_qp_hw_spec[QAT_N_GENS];
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__extension__
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const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
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[ADF_MAX_QPS_ON_ANY_SERVICE] = {
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@ -7,8 +7,6 @@
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#include "qat_common.h"
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#include "adf_transport_access_macros.h"
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struct qat_pci_device;
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#define QAT_CSR_HEAD_WRITE_THRESH 32U
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/* number of requests to accumulate before writing head CSR */
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@ -24,37 +22,7 @@ struct qat_pci_device;
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#define QAT_GEN4_BUNDLE_NUM 4
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#define QAT_GEN4_QPS_PER_BUNDLE_NUM 1
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/**
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* Structure with data needed for creation of queue pair.
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*/
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struct qat_qp_hw_data {
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enum qat_service_type service_type;
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uint8_t hw_bundle_num;
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uint8_t tx_ring_num;
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uint8_t rx_ring_num;
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uint16_t tx_msg_size;
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uint16_t rx_msg_size;
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};
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/**
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* Structure with data needed for creation of queue pair on gen4.
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*/
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struct qat_qp_gen4_data {
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struct qat_qp_hw_data qat_qp_hw_data;
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uint8_t reserved;
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uint8_t valid;
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};
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/**
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* Structure with data needed for creation of queue pair.
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*/
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struct qat_qp_config {
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const struct qat_qp_hw_data *hw;
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uint32_t nb_descriptors;
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uint32_t cookie_size;
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int socket_id;
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const char *service_str;
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};
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struct qat_pci_device;
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/**
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* Structure associated with each queue.
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@ -96,8 +64,28 @@ struct qat_qp {
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uint16_t min_enq_burst_threshold;
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} __rte_cache_aligned;
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extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
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extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
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/**
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* Structure with data needed for creation of queue pair.
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*/
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struct qat_qp_hw_data {
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enum qat_service_type service_type;
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uint8_t hw_bundle_num;
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uint8_t tx_ring_num;
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uint8_t rx_ring_num;
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uint16_t tx_msg_size;
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uint16_t rx_msg_size;
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};
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/**
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* Structure with data needed for creation of queue pair.
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*/
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struct qat_qp_config {
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const struct qat_qp_hw_data *hw;
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uint32_t nb_descriptors;
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uint32_t cookie_size;
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int socket_id;
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const char *service_str;
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};
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uint16_t
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qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
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@ -136,4 +124,49 @@ qat_select_valid_queue(struct qat_pci_device *qat_dev, int qp_id,
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int
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qat_read_qp_config(struct qat_pci_device *qat_dev);
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/**
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* Function prototypes for GENx specific queue pair operations.
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**/
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typedef int (*qat_qp_rings_per_service_t)
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(struct qat_pci_device *, enum qat_service_type);
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typedef void (*qat_qp_build_ring_base_t)(void *, struct qat_queue *);
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typedef void (*qat_qp_adf_arb_enable_t)(const struct qat_queue *, void *,
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rte_spinlock_t *);
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typedef void (*qat_qp_adf_arb_disable_t)(const struct qat_queue *, void *,
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rte_spinlock_t *);
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typedef void (*qat_qp_adf_configure_queues_t)(struct qat_qp *);
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typedef void (*qat_qp_csr_write_tail_t)(struct qat_qp *qp, struct qat_queue *q);
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typedef void (*qat_qp_csr_write_head_t)(struct qat_qp *qp, struct qat_queue *q,
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uint32_t new_head);
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typedef void (*qat_qp_csr_setup_t)(struct qat_pci_device*, void *,
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struct qat_qp *);
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typedef const struct qat_qp_hw_data * (*qat_qp_get_hw_data_t)(
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struct qat_pci_device *dev, enum qat_service_type service_type,
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uint16_t qp_id);
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struct qat_qp_hw_spec_funcs {
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qat_qp_rings_per_service_t qat_qp_rings_per_service;
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qat_qp_build_ring_base_t qat_qp_build_ring_base;
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qat_qp_adf_arb_enable_t qat_qp_adf_arb_enable;
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qat_qp_adf_arb_disable_t qat_qp_adf_arb_disable;
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qat_qp_adf_configure_queues_t qat_qp_adf_configure_queues;
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qat_qp_csr_write_tail_t qat_qp_csr_write_tail;
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qat_qp_csr_write_head_t qat_qp_csr_write_head;
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qat_qp_csr_setup_t qat_qp_csr_setup;
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qat_qp_get_hw_data_t qat_qp_get_hw_data;
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};
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extern struct qat_qp_hw_spec_funcs *qat_qp_hw_spec[];
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extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
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extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
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#endif /* _QAT_QP_H_ */
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