net/sfc: introduce common driver library

Move libefx (base driver) into common driver.

Prepare to add vDPA driver which will use the common driver as well.

Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Reviewed-by: Andy Moreton <amoreton@xilinx.com>

MAINTAINERS

@@ -853,6 +853,7 @@ F: doc/guides/nics/features/qede*.ini
 
 Solarflare sfc_efx
 M: Andrew Rybchenko <arybchenko@solarflare.com>
+F: drivers/common/sfc_efx/
 F: drivers/net/sfc/
 F: doc/guides/nics/sfc_efx.rst
 F: doc/guides/nics/features/sfc_efx.ini

drivers/common/meson.build

@@ -6,6 +6,6 @@ if is_windows
 endif
 
 std_deps = ['eal']
-drivers = ['cpt', 'dpaax', 'iavf', 'mvep', 'octeontx', 'octeontx2', 'qat']
+drivers = ['cpt', 'dpaax', 'iavf', 'mvep', 'octeontx', 'octeontx2', 'qat', 'sfc_efx']
 config_flag_fmt = 'RTE_LIBRTE_@0@_COMMON'
 driver_name_fmt = 'rte_common_@0@'

drivers/common/sfc_efx/efsys.h

@@ -25,15 +25,16 @@
 #include <rte_log.h>
 #include <rte_io.h>
 
-#include "sfc_debug.h"
-#include "sfc_log.h"
+#include "sfc_efx_debug.h"
+#include "sfc_efx_log.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
-/* No specific decorations required since all functions are local now */
-#define LIBEFX_API
+#define LIBEFX_API		__rte_internal
+
+/* No specific decorations required since functions are local by default */
 #define LIBEFX_INTERNAL
 
 #define EFSYS_HAS_UINT64 1
@@ -228,8 +229,8 @@ typedef struct efsys_mem_s {
 		volatile uint32_t *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_dword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_dword_t)));	\
 									\
 		_addr = (volatile uint32_t *)(_base + (_offset));	\
 		(_edp)->ed_u32[0] = _addr[0];				\
@@ -246,8 +247,8 @@ typedef struct efsys_mem_s {
 		volatile uint64_t *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_qword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_qword_t)));	\
 									\
 		_addr = (volatile uint64_t *)(_base + (_offset));	\
 		(_eqp)->eq_u64[0] = _addr[0];				\
@@ -265,8 +266,8 @@ typedef struct efsys_mem_s {
 		volatile __m128i *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_oword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_oword_t)));	\
 									\
 		_addr = (volatile __m128i *)(_base + (_offset));	\
 		(_eop)->eo_u128[0] = _addr[0];				\
@@ -287,8 +288,8 @@ typedef struct efsys_mem_s {
 		volatile uint32_t *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_dword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_dword_t)));	\
 									\
 		EFSYS_PROBE2(mem_writed, unsigned int, (_offset),	\
 					 uint32_t, (_edp)->ed_u32[0]);	\
@@ -305,8 +306,8 @@ typedef struct efsys_mem_s {
 		volatile uint64_t *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_qword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_qword_t)));	\
 									\
 		EFSYS_PROBE3(mem_writeq, unsigned int, (_offset),	\
 					 uint32_t, (_eqp)->eq_u32[1],	\
@@ -324,8 +325,8 @@ typedef struct efsys_mem_s {
 		volatile __m128i *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_oword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_oword_t)));	\
 									\
 									\
 		EFSYS_PROBE5(mem_writeo, unsigned int, (_offset),	\
@@ -390,8 +391,8 @@ typedef struct efsys_bar_s {
 		volatile uint32_t *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_dword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_dword_t)));	\
 		_NOTE(CONSTANTCONDITION);				\
 		if (_lock)						\
 			SFC_BAR_LOCK(_esbp);				\
@@ -415,8 +416,8 @@ typedef struct efsys_bar_s {
 		volatile uint64_t *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_qword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_qword_t)));	\
 									\
 		SFC_BAR_LOCK(_esbp);					\
 									\
@@ -438,8 +439,8 @@ typedef struct efsys_bar_s {
 		volatile __m128i *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_oword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_oword_t)));	\
 									\
 		_NOTE(CONSTANTCONDITION);				\
 		if (_lock)						\
@@ -469,8 +470,8 @@ typedef struct efsys_bar_s {
 		volatile uint32_t *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_dword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_dword_t)));	\
 									\
 		_NOTE(CONSTANTCONDITION);				\
 		if (_lock)						\
@@ -495,8 +496,8 @@ typedef struct efsys_bar_s {
 		volatile uint64_t *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_qword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_qword_t)));	\
 									\
 		SFC_BAR_LOCK(_esbp);					\
 									\
@@ -530,8 +531,8 @@ typedef struct efsys_bar_s {
 		volatile __m128i *_addr;				\
 									\
 		_NOTE(CONSTANTCONDITION);				\
-		SFC_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,		\
-					    sizeof(efx_oword_t)));	\
+		SFC_EFX_ASSERT(EFX_IS_P2ALIGNED(size_t, _offset,	\
+						sizeof(efx_oword_t)));	\
 									\
 		_NOTE(CONSTANTCONDITION);				\
 		if (_lock)						\
@@ -629,7 +630,7 @@ typedef rte_spinlock_t efsys_lock_t;
 #define SFC_EFSYS_UNLOCK(_eslp)				\
 	rte_spinlock_unlock((_eslp))
 #define SFC_EFSYS_LOCK_ASSERT_OWNED(_eslp)		\
-	SFC_ASSERT(rte_spinlock_is_locked((_eslp)))
+	SFC_EFX_ASSERT(rte_spinlock_is_locked((_eslp)))
 
 typedef int efsys_lock_state_t;
 
@@ -644,7 +645,7 @@ typedef int efsys_lock_state_t;
 
 #define EFSYS_UNLOCK(_lockp, _state)				\
 	do {							\
-		SFC_ASSERT((_state) == EFSYS_LOCK_MAGIC);	\
+		SFC_EFX_ASSERT((_state) == EFSYS_LOCK_MAGIC);	\
 		SFC_EFSYS_UNLOCK(_lockp);			\
 		_NOTE(CONSTANTCONDITION);			\
 	} while (B_FALSE)
@@ -701,7 +702,7 @@ typedef uint64_t	efsys_stat_t;
 #define EFSYS_ERR(_esip, _code, _dword0, _dword1)			\
 	do {								\
 		(void)(_esip);						\
-		SFC_GENERIC_LOG(ERR, "FATAL ERROR #%u (0x%08x%08x)",	\
+		SFC_EFX_LOG(ERR, "FATAL ERROR #%u (0x%08x%08x)",	\
 			(_code), (_dword0), (_dword1));			\
 		_NOTE(CONSTANTCONDITION);				\
 	} while (B_FALSE)

drivers/common/sfc_efx/meson.build

@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Copyright(c) 2019-2020 Xilinx, Inc.
+#
+# This software was jointly developed between OKTET Labs (under contract
+# for Solarflare) and Solarflare Communications, Inc.
+
+if arch_subdir != 'x86' or not dpdk_conf.get('RTE_ARCH_64')
+	build = false
+	reason = 'only supported on x86_64'
+endif
+
+extra_flags = []
+
+# Enable more warnings
+extra_flags += [
+	'-Wdisabled-optimization'
+]
+
+# Compiler and version dependent flags
+extra_flags += [
+	'-Waggregate-return',
+	'-Wbad-function-cast'
+]
+
+foreach flag: extra_flags
+	if cc.has_argument(flag)
+		cflags += flag
+	endif
+endforeach
+
+subdir('base')
+objs = [base_objs]
+
+sources = files(
+	'sfc_efx.c',
+)
+
+includes += include_directories('base')

drivers/common/sfc_efx/rte_common_sfc_efx_version.map

@@ -0,0 +1,182 @@
+INTERNAL {
+	global:
+
+	efx_crc32_calculate;
+
+	efx_ev_fini;
+	efx_ev_init;
+	efx_ev_qcreate;
+	efx_ev_qdestroy;
+	efx_ev_qmoderate;
+	efx_ev_qpending;
+	efx_ev_qpoll;
+	efx_ev_qpost;
+	efx_ev_qprime;
+	efx_ev_usecs_to_ticks;
+
+	efx_evq_nbufs;
+	efx_evq_size;
+
+	efx_family;
+
+	efx_filter_fini;
+	efx_filter_init;
+	efx_filter_insert;
+	efx_filter_remove;
+	efx_filter_restore;
+	efx_filter_spec_init_rx;
+	efx_filter_spec_init_tx;
+	efx_filter_spec_set_encap_type;
+	efx_filter_spec_set_eth_local;
+	efx_filter_spec_set_ether_type;
+	efx_filter_spec_set_geneve;
+	efx_filter_spec_set_ipv4_full;
+	efx_filter_spec_set_ipv4_local;
+	efx_filter_spec_set_mc_def;
+	efx_filter_spec_set_nvgre;
+	efx_filter_spec_set_rss_context;
+	efx_filter_spec_set_uc_def;
+	efx_filter_spec_set_vxlan;
+	efx_filter_supported_filters;
+
+	efx_hash_bytes;
+	efx_hash_dwords;
+
+	efx_intr_disable;
+	efx_intr_disable_unlocked;
+	efx_intr_enable;
+	efx_intr_fatal;
+	efx_intr_fini;
+	efx_intr_init;
+	efx_intr_status_line;
+	efx_intr_status_message;
+	efx_intr_trigger;
+
+	efx_loopback_mask;
+	efx_loopback_type_name;
+
+	efx_mac_addr_set;
+	efx_mac_drain;
+	efx_mac_fcntl_get;
+	efx_mac_fcntl_set;
+	efx_mac_filter_default_rxq_clear;
+	efx_mac_filter_default_rxq_set;
+	efx_mac_filter_get_all_ucast_mcast;
+	efx_mac_filter_set;
+	efx_mac_multicast_list_set;
+	efx_mac_pdu_get;
+	efx_mac_pdu_set;
+	efx_mac_stat_name;
+	efx_mac_stats_clear;
+	efx_mac_stats_get_mask;
+	efx_mac_stats_periodic;
+	efx_mac_stats_update;
+	efx_mac_stats_upload;
+	efx_mac_up;
+
+	efx_mcdi_fini;
+	efx_mcdi_get_proxy_handle;
+	efx_mcdi_get_timeout;
+	efx_mcdi_init;
+	efx_mcdi_new_epoch;
+	efx_mcdi_reboot;
+	efx_mcdi_request_abort;
+	efx_mcdi_request_poll;
+	efx_mcdi_request_start;
+
+	efx_mon_fini;
+	efx_mon_init;
+	efx_mon_name;
+
+	efx_nic_calculate_pcie_link_bandwidth;
+	efx_nic_cfg_get;
+	efx_nic_check_pcie_link_speed;
+	efx_nic_create;
+	efx_nic_destroy;
+	efx_nic_fini;
+	efx_nic_get_bar_region;
+	efx_nic_get_fw_subvariant;
+	efx_nic_get_fw_version;
+	efx_nic_get_vi_pool;
+	efx_nic_hw_unavailable;
+	efx_nic_init;
+	efx_nic_probe;
+	efx_nic_reset;
+	efx_nic_set_drv_limits;
+	efx_nic_set_drv_version;
+	efx_nic_set_fw_subvariant;
+	efx_nic_set_hw_unavailable;
+	efx_nic_unprobe;
+
+	efx_phy_adv_cap_get;
+	efx_phy_adv_cap_set;
+	efx_phy_fec_type_get;
+	efx_phy_link_state_get;
+	efx_phy_lp_cap_get;
+	efx_phy_media_type_get;
+	efx_phy_module_get_info;
+	efx_phy_oui_get;
+	efx_phy_verify;
+
+	efx_port_fini;
+	efx_port_init;
+	efx_port_loopback_set;
+	efx_port_poll;
+
+	efx_pseudo_hdr_hash_get;
+	efx_pseudo_hdr_pkt_length_get;
+
+	efx_rx_fini;
+	efx_rx_hash_default_support_get;
+	efx_rx_init;
+	efx_rx_qcreate;
+	efx_rx_qcreate_es_super_buffer;
+	efx_rx_qdestroy;
+	efx_rx_qenable;
+	efx_rx_qflush;
+	efx_rx_qpost;
+	efx_rx_qpush;
+	efx_rx_scale_context_alloc;
+	efx_rx_scale_context_free;
+	efx_rx_scale_default_support_get;
+	efx_rx_scale_hash_flags_get;
+	efx_rx_scale_key_set;
+	efx_rx_scale_mode_set;
+	efx_rx_scale_tbl_set;
+	efx_rxq_nbufs;
+	efx_rxq_size;
+
+	efx_sram_buf_tbl_clear;
+	efx_sram_buf_tbl_set;
+
+	efx_tunnel_config_clear;
+	efx_tunnel_config_udp_add;
+	efx_tunnel_config_udp_remove;
+	efx_tunnel_fini;
+	efx_tunnel_init;
+	efx_tunnel_reconfigure;
+
+	efx_tx_fini;
+	efx_tx_init;
+	efx_tx_qcreate;
+	efx_tx_qdesc_checksum_create;
+	efx_tx_qdesc_dma_create;
+	efx_tx_qdesc_post;
+	efx_tx_qdesc_tso_create;
+	efx_tx_qdesc_tso2_create;
+	efx_tx_qdesc_vlantci_create;
+	efx_tx_qdestroy;
+	efx_tx_qenable;
+	efx_tx_qflush;
+	efx_tx_qpace;
+	efx_tx_qpio_disable;
+	efx_tx_qpio_enable;
+	efx_tx_qpio_post;
+	efx_tx_qpio_write;
+	efx_tx_qpost;
+	efx_tx_qpush;
+	efx_txq_nbufs;
+	efx_txq_size;
+
+	local: *;
+};

drivers/common/sfc_efx/sfc_efx.c

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019 Solarflare Communications Inc.
+ *
+ * This software was jointly developed between OKTET Labs (under contract
+ * for Solarflare) and Solarflare Communications, Inc.
+ */
+
+#include <rte_log.h>
+
+#include "sfc_efx_log.h"
+
+uint32_t sfc_efx_logtype;
+
+RTE_INIT(sfc_efx_register_logtype)
+{
+	int ret;
+
+	ret = rte_log_register_type_and_pick_level("pmd.common.sfc_efx",
+						   RTE_LOG_NOTICE);
+	sfc_efx_logtype = (ret < 0) ? RTE_LOGTYPE_PMD : ret;
+}

drivers/common/sfc_efx/sfc_efx_debug.h

@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019 Solarflare Communications Inc.
+ *
+ * This software was jointly developed between OKTET Labs (under contract
+ * for Solarflare) and Solarflare Communications, Inc.
+ */
+
+#ifndef _SFC_EFX_DEBUG_H_
+#define _SFC_EFX_DEBUG_H_
+
+#include <rte_debug.h>
+
+#ifndef RTE_DEBUG_COMMON_SFC_EFX
+#define RTE_DEBUG_COMMON_SFC_EFX	0
+#endif
+
+#ifdef RTE_DEBUG_COMMON_SFC_EFX
+/* Avoid dependency from RTE_LOG_DP_LEVEL to be able to enable debug check
+ * in the driver only.
+ */
+#define SFC_EFX_ASSERT(exp)		RTE_VERIFY(exp)
+#else
+/* If the driver debug is not enabled, follow DPDK debug/non-debug */
+#define SFC_EFX_ASSERT(exp)		RTE_ASSERT(exp)
+#endif
+
+#endif /* _SFC_EFX_DEBUG_H_ */

drivers/common/sfc_efx/sfc_efx_log.h

@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Copyright(c) 2019-2020 Xilinx, Inc.
+ * Copyright(c) 2019 Solarflare Communications Inc.
+ *
+ * This software was jointly developed between OKTET Labs (under contract
+ * for Solarflare) and Solarflare Communications, Inc.
+ */
+
+#ifndef _SFC_EFX_LOG_H_
+#define _SFC_EFX_LOG_H_
+
+/** Generic driver log type */
+extern uint32_t sfc_efx_logtype;
+
+/** Log message, add a prefix and a line break */
+#define SFC_EFX_LOG(level, ...) \
+	rte_log(RTE_LOG_ ## level, sfc_efx_logtype,			\
+		RTE_FMT("sfc_efx: " RTE_FMT_HEAD(__VA_ARGS__ ,) "\n",	\
+			RTE_FMT_TAIL(__VA_ARGS__ ,)))
+
+#endif /* _SFC_EFX_LOG_H_ */

drivers/net/sfc/meson.build

@@ -33,9 +33,7 @@ foreach flag: extra_flags
 	endif
 endforeach
 
-subdir('base')
-objs = [base_objs]
-
+deps += ['common_sfc_efx']
 sources = files(
 	'sfc_ethdev.c',
 	'sfc_kvargs.c',
@@ -54,5 +52,3 @@ sources = files(
 	'sfc_ef10_essb_rx.c',
 	'sfc_ef10_tx.c'
 )
-
-includes += include_directories('base')